JP2009105119A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 109
- 238000005304 joining Methods 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 description 12
- 239000000956 alloy Substances 0.000 description 12
- 238000006722 reduction reaction Methods 0.000 description 12
- 230000004907 flux Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Abstract
【解決手段】本発明は、第1半導体チップ10と、第1半導体チップ10に設けられた第1電極12と、第1半導体チップ10が実装される第2半導体チップ20と、第2半導体チップ20に設けられた、突起24を有する第2電極22と、第1電極12と第2電極22を接合し、前記突起24の側面の少なくとも一部を覆う半田バンプ14とを具備している半導体装置及びその製造方法である。
【選択図】図1
Description
12 第1電極
14 半田バンプ
16 絶縁層
18 ツール
20 第2半導体チップ
22 第2電極
24 突起
26 絶縁層
26a 材料層
28 ステージ
34 突起
42 金属ポスト
44 半田層
100 半導体装置
Claims (10)
- 実装部と、
前記実装部に設けられた第1電極と、
前記実装部が実装される被実装部と、
前記被実装部に設けられた、突起を有する第2電極と、
前記第1電極と前記第2電極を接合し、前記突起の側面の少なくとも一部を覆う半田を含む接合端子とを具備し、
前記実装部と前記被実装部との少なくとも一方は半導体チップを含むことを特徴とする半導体装置。 - 前記接合端子は、半田からなることを特徴とする請求項1記載の半導体装置。
- 前記接合端子は、金属ポストと、前記金属ポストの前記第2電極と対向している面に設けられた半田層とにより構成されていることを特徴とする請求項1記載の半導体装置。
- 前記被実装部は、前記突起内の下部に前記第2電極の表面より熱伝導率の低い材料層を有することを特徴とする請求項1から3のいずれか一項記載の半導体装置。
- 前記実装部に設けられた前記第1電極を、前記被実装部に設けられた前記突起を有する前記第2電極に、前記突起の先端部と、前記第1電極に設けられた前記接合端子と、を接触させることにより仮接合する工程と、
前記第1電極と、前記第2電極と、前記接合端子に含まれている前記半田と、を還元ガス中に暴露する工程と、
前記第1電極を前記第2電極に、前記突起の側面の少なくとも一部を前記接合端子に含まれる前記半田で覆うことにより本接合する工程とを含み、
前記実装部と前記被実装部との少なくとも一方は半導体チップを含むことを特徴とする半導体装置の製造方法。 - 前記仮接合する工程は、前記第2電極の側面と、前記半田の前記突起の先端部との接触面以外の表面と、が露出するように仮接合する工程であることを特徴とする、請求項5記載の半導体装置の製造方法。
- 前記仮接合する工程は、前記突起の先端部の温度が前記半田の融点以上になり、かつ前記第2電極の前記突起の先端部を除いた部分の温度が前記半田の融点未満になるように加熱する工程を含むことを特徴とする請求項5から6記載の半導体装置の製造方法。
- 前記仮接合する工程は、前記実装部と前記被実装部との少なくとも一方に超音波振動を加え、前記金属ポストの表面と前記突起の先端部とを擦り合わせる工程を含むことを特徴とする請求項5から6記載の半導体装置の製造方法。
- 前記仮接合する工程は、前記突起の側面と、前記半田の前記金属ポストとの接触面以外及び前記半田の前記突起の先端部との接触面以外の表面と、を露出させる工程を含むことを特徴とする請求項8記載の半導体製造方法。
- 前記本接合する工程は、前記実装部と前記被実装部との少なくとも一方を、正対しないように仮接合された前記第1電極と前記第2電極とが正対する方向に移動させる工程を含むことを特徴とする請求項5から9いずれか一項記載の半導体装置の製造方法。
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US9437573B2 (en) | 2016-09-06 |
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US20140113411A1 (en) | 2014-04-24 |
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