JP2009099165A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily increase the number of redundancies in an SRAM, etc., by reducing area penalty in a similar way as a conventional dynamic column shift method. <P>SOLUTION: This semiconductor storage device includes a column shift redundancy circuit for dynamically shifting columns when an address input hits on a defective address. The redundancy column cell is divided into N pieces and column addresses different from each other are allocated to the divided cells. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a column shift redundancy circuit that dynamically shifts a column when a defective address is hit, and is used, for example, in an SRAM.

  In a semiconductor memory device, a column shift type redundant circuit (see, for example, Patent Document 1) that performs a column shift when replacing a defective column with a spare column is often employed. The column shift method is roughly classified into a static column shift method that statically performs column shift and a dynamic column shift method that dynamically performs column shift.

  The conventional static column shift method and the conventional dynamic column shift method are compared with defective column addressing contents, area penalty, and speed penalty. In the static column shift method, the I / O area where the defective cell exists is statically switched with the spare on an I / O basis, so there is no need for bad cell hit information and there is no speed penalty. The penalty is large.

  On the other hand, in the dynamic column shift method, switching is performed in units of blocks in which defective cells exist based on the hit information of defective cells, so there is a slight speed penalty, but the area penalty is greatly improved over the static column shift method.

  FIG. 6 schematically shows a configuration of a part of an SRAM having a conventional dynamic column shift type redundant circuit. In this SRAM, as shown in FIG. 6A, word lines (Word lines) are arranged in a row direction and bit lines (Bit lines) are arranged in a column direction on a memory cell array in which SRAM cells are arranged in a matrix. Has been. Normally, a normal I / O area of a memory cell array has four blocks (No. <0>, <1>, <2>, <3) for each I / O area as shown in FIG. As shown in FIG. 6C, each block is provided with a column selector (MUX), a global sense amplifier (G_S / A), and a write buffer (not shown). The sense amplifier output data line and the write buffer input line of each block are connected to a common data line via a block selection circuit (BMUX).

  On the other hand, the spare I / O (I / O spare) area of the memory cell array is, for example, one block that is 1/4 of the number of blocks in the normal I / O area, as shown in FIG. Yes, redundant cells having a smaller number of columns (for example, 8 columns) than the normal I / O area are arranged. A global sense amplifier (G_S / A) and a write buffer (not shown) are provided for one block in this spare I / O (I / O spare) area. Is possible.

  FIG. 7 shows in detail an example of operation of a conventional dynamic column shift redundant circuit. The input address is compared with the address of the defective cell set by a fuse or the like. If there is no defective cell, the address comparison does not match as shown in FIG. 7A, and no spare redundant cell is used.

  On the other hand, when there is a defective cell and the address comparison matches (hits), as shown in FIG. 7B, the I / O area including the defective cell is not used and another I / O area is used. Control the shifter circuit to use (switch). For example, when there is a defective cell (NG) in block No. <2> in the I / O 1 area, the connection between the common data line in each I / O area and the I / O circuit section is dynamically switched. Here, the I / O 1 area cannot be used, the I / O 2 area is reassigned to the I / O1 area, and the I / O spare area is reassigned to the <2> area of I / O2. When there is a defective cell and the address comparison does not match (hit), the spare redundant cell is not used as shown in FIG.

  As for the area penalty, it seems that it is only necessary to perform column shift in units of one column. However, in SRAM, transfer in units of one column is not a good idea. The reason is that in the normal I / O area, global sense amplifiers and write buffers are controlled by blocks in units of multiple columns for convenience of layout, etc., so the spare I / O area is also the normal I / O area. This is because the control in the same column block unit as above has good consistency with the normal I / O area.

By the way, if the device is miniaturized and the storage capacity is increased, it is necessary to increase the number of redundancy because the defect repair rate is reduced. However, the conventional dynamic column shift method has a problem that the number of redundancy is insufficient. Occurs. That is, in order to increase the number of redundancy in the conventional dynamic column shift method, for each of a plurality of defective address hits, a shift for one column, a shift for two columns, a shift for three columns,. Control method. However, column shift control using such a method is difficult, and considering the increase in area penalty, the shift of two columns is considered to be the limit.
JP 2004-355744 A

  The present invention has been made to solve the above-described conventional problems, and the conventional dynamic column shift method has the same effect as the area penalty reduction effect compared with the conventional static column shift method, It is an object of the present invention to provide a semiconductor memory device capable of easily extending the number of redundancy as compared with it.

  The semiconductor memory device of the present invention has a dynamic column shift type redundant circuit capable of dynamically performing a column shift in each input / output circuit unit of an input / output circuit section composed of a plurality of input / output circuits. A semiconductor memory device having a normal block in which normal memory cells are arranged and a redundant block in which redundant memory cells are arranged, and the columns of the redundant block are divided into N, and different column addresses are assigned to the divided column bundles. The memory cell array to which is assigned, the column shift circuit capable of switching the connection relationship between the block used in the memory cell array and the input / output circuit unit, the bad column address stored in advance and the input address are compared and matched In some cases, the column shift operation of the column shift circuit to replace a defective column with a redundant column Comprising a shift control circuit for dynamically controlling, characterized by the N specify the relief addressable.

  According to the semiconductor memory device of the present invention, the conventional dynamic column shift method has the same effect as the area penalty reduction effect compared to the conventional static column shift method, and the redundancy number can be easily expanded compared to the conventional one. Can be done.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

  FIG. 1A is a block diagram showing a configuration of a part (read system) of an SRAM having a dynamic column shift type redundant circuit according to an embodiment of the semiconductor memory device of the present invention. The SRAM includes a memory cell array 10, a row decoder 13, a column decoder (not shown), an I / O circuit (DOUT) unit 14 including an output buffer (Out Buffer), a column shift circuit, a shift control circuit, and the like. In the memory cell array 10, a plurality of memory cells are arranged in a matrix, a plurality of word lines (WL) are arranged in the row direction, and a plurality of bit lines (BL) (complementary pairs) are arranged in the column direction. It is installed.

  FIG. 1B shows the memory cell array 10 in FIG. 1A, a part of the column shift circuit, and the shift control circuit. The memory cell array 10 includes a plurality of normal blocks 11 in which normal memory cells are arranged in a predetermined number of columns, and at least one redundant block in which redundant memory cells are arranged in the same number of columns as the normal blocks. Has 12.

  The column shift circuit 15 dynamically switches the connection relationship between the common data line 24 for normal blocks and the common data line 27 for redundant blocks used in the memory cell array 10 and the I / O circuit unit 14.

  The shift control circuit 16 compares the defective column address stored in advance with the input address, and controls the column shift operation of the column shift circuit 15 to replace the defective column with the redundant column if they match. At this time, starting from the block where the defective column exists in the memory cell array 10, the connection relationship between the block to be used and the I / O circuit unit 14 is shifted to one side in the block arrangement direction, so that the defective column is dynamically changed. Replace with redundant column.

  FIG. 2 shows a configuration example by extracting a part of the plurality of normal blocks 11 and the redundant block 12 in FIG. In the normal block 11, each column is connected to a global sense amplifier (GS / A) 22 via a column selector multiplex circuit (MUX) 21, and each global sense amplifier (GS / A) 22 is a block. It is connected to a common data line 24 for a normal block through a selection circuit (BMUX) 23.

  In the redundant block 12, the columns are divided into N, and different column addresses are assigned to the respective divided column bundles. Each column is connected to a global sense amplifier (GS / A) 26 for redundant blocks via a multiplex circuit 25, and the output side of the global sense amplifier (GS / A) 26 is a common data line for redundant blocks. Connected to 27.

  A specific example of the SRAM will be described below with reference to FIGS. The cell array 10 includes a plurality of normal I / O regions (I / O 0, I / O 1, I / O 2,...) In which normal memory cells are arranged, and at least one in which redundant memory cells are arranged. It consists of a spare I / O area.

  In a normal I / O area (I / O 0, I / O 1, I / O 2,…), each I / O area has four blocks (No. <0>, <1>, <2>, <3>) 11, and the columns of each block 11 include a column selector multiplex circuit (MUX) 21, a global sense amplifier (G_S / A) 22, a write buffer (not shown), a block selection circuit ( BMUX) 23 to the common data line 24. The column shift circuit 15 switches the connection relationship between the common data line 24 in each I / O region and the data line DOUTi (i = 0, 1, 2,...) Of the I / O circuit unit 14.

  On the other hand, in the spare I / O area, redundant cells having a smaller number of columns than in the normal I / O area are arranged. In this example, the number of blocks in the normal I / O area is, for example, 1/4. Become. The column of one block 12 in this spare I / O area is connected to a common data line via a column selector multiplex circuit (MUX) 25, a global sense amplifier (G_S / A) 26, and a write buffer (not shown). Connected to 27. One block 12 in the spare I / O area is composed of, for example, 8 columns as in the case of each block 11 in the normal I / O area, and these 8 columns are divided into N (N is, for example, 2). In this case, different column addresses are assigned to the four-column bundle on the left side in the figure and the four-column bundle on the right side in the figure, and switching can be performed independently in units of the four-column bundle.

  However, defects that can be relieved by switching (replacement) to a spare I / O area are two defective columns corresponding to two “four-column bundles”. These two bad columns may be in the same I / O area or in different I / O areas, but the bad column addresses (Address) that determine the two “4-column bundles” need to be different from each other. There is. Then, as the defective address data stored in the fuse or the like, a defective column address that determines “I / O Number” and “4-column bundle” is used to designate a defective relief position, and the column shift circuit 15 shifts the common data line. Decide where to do.

  In the above-described SRAM operation, the input address is compared with the address of a defective cell set by a fuse or the like. If there is no defective cell, the address comparison does not match (hit) and no spare redundant cell is used. If there is a defective cell, it is remedied as described below.

  FIG. 3 shows an example of the dynamic column shift operation when there is one defect in the block <0> in the I / O 1 area shown in FIG. 3A shows the entire normal I / O area and spare I / O area, FIG. 3B shows the I / O 1 area including the defective cell, and FIG. A spare I / O area to be replaced with an I / O 1 area including a defective cell is shown.

  If there is a defective cell in the leftmost column of the block <0> in the I / O 1 area, and the input address matches the address of the defective cell, another I / O area is used without using the I / O area containing the defective cell. Control the column shift circuit to use (switch) the O area. In this case, the connection relationship between the block common data line in the I / O area and the I / O circuit section on the fixed direction side of the block array (in this example, the right side in the figure) from the defective I / O 1 area The column shift is controlled so that the I / O 1 area is disabled, the block <0> in the I / O 2 area is replaced with the block <0> in the I / O 1 area, and the I / O 1 area is disabled. Replace the 4 columns in the left half of the spare <0> area with the block <0> in the I / O 2 area.

  FIG. 4 is a block diagram of the I / O 2 area block <0> in the I / O 1 area block <0> shown in FIG. An example of the dynamic column shift operation when there is a second defect in is shown. Also in this case, FIG. 4A shows the entire normal I / O area and spare I / O area, FIG. 4B shows the I / O 2 area including the defective cell, and FIG. b) shows a spare I / O area to be replaced with an I / O 2 area including a defective cell.

  Relief for the first defect is performed as described above with reference to FIG. As a second defect, if there is a defective cell in the rightmost column of the block <1> in the I / O 2 area, if the input address matches the address of the defective cell, the I / O area containing the defective cell is Control the column shift circuit to use (switch) other I / O areas without using them. In this case, the connection relationship between the block common data line in the I / O area on the fixed direction side of the block array (in this example, the right side in the figure) and the I / O circuit section from the defective I / O 2 area The column shift is controlled so that the I / O 2 area is dynamically switched, the I / O 2 area is disabled, and the unused I / O spare <0> area (right half in the figure) is 4 columns in the I / O 2 area. Replace with block <1>.

  FIG. 5 shows an example of the logic configuration of the shift control circuit 16 that controls the column shift circuit 15 shown in FIG. Defective address data (defective column address “Address” that determines “4 column bundle” to be simultaneously switched with “I / O Number”) and input address (Input-Add) are input to the shift control circuit. The “I / O Number” and “Address” are stored in advance in fuses (fuse1-I / O, fuse2-I / O, fuse1-Add, fuse2-Add) at the initial stage of use of the device. In this case, the fuse set of fuse1-I / O, fuse1-Add stores the first defect information (the column address that determines the “4-column bundle” to be simultaneously switched), and fuse2-I / O, In the fuse set of fuse2-Add, second defect information (a column address that determines “4-column bundle” to be simultaneously switched) is stored.

  The shift control circuit is provided in the peripheral circuit portion of the memory core, and is logically configured by a 2-input AND circuit, an OR circuit, a register circuit (Reg11, Reg21,...) And the like. When the number of defective remedies is N, N fuse sets are prepared, and an AND circuit having N inputs is used.

  In this example, the “Address” stored in the fuse (fuse1-Add, fuse2-Add) for designating the defective column is compared with Input-Add. 15 controls where the common data line is shifted. That is, the defective cell and the redundant cell are dynamically switched by shifting the connection relationship with the I / O circuit unit one block at a time in the block arrangement direction starting from the block in which the defective column exists. .

  As described above, according to the SRAM of this embodiment, the connection relationship between the memory cell array 10 and the I / O circuit unit 14 can be dynamically shifted in I / O units (global sense amplifier units). It has possible dynamic column shift type redundancy circuit. Then, the redundant column of the redundant block in the memory cell array is divided into N with respect to the conventional redundancy circuit of the dynamic column shift method, and N column repairable addresses are assigned to the divided column bundles by assigning different column addresses to each other. It can be specified.

  For example, if the number of redundant columns in a redundant block is 8 and these 8 columns are divided into two, four defective columns having different column addresses can be repaired independently by simultaneous replacement of a 4-column bundle. Is possible. On the other hand, when eight redundant columns are divided into four, four defective columns having different column addresses can be repaired independently by simultaneous replacement of two column bundles. In addition, when eight redundant columns are divided into eight, it is possible to independently repair eight defective columns having different column addresses by replacing one column. When the redundant column is not divided (conventional example), only one defective column can be relieved by simultaneous replacement of the 8-column bundle.

  As the number of defective columns that can be remedied independently increases, the number of logics of the address comparator, fuse, and redundant control circuit increases in the peripheral circuit section of the memory core, which increases the circuit scale. It also happens in

  The feature related to the area penalty in the present embodiment is that the shift circuit may be the same regardless of the number of defective cells that can be repaired independently for the memory core portion. There is no increase.

  When considering the trade-off between the repair rate and the area penalty for the above three repair methods for dividing the redundant column, the realistic choice is “simultaneous replacement of two column bundles” or “four column bundles”. It is considered as “simultaneous replacement” Regarding the number of defective columns that can be repaired independently, there is a restriction on the repairable address, and even if the number of defective columns that can be repaired independently is increased, the repair rate is not proportionally improved.

1 is a block diagram showing a part of an SRAM having a dynamic column shift redundant circuit according to an embodiment of a semiconductor memory device of the present invention; FIG. 2 is a configuration diagram showing a part of a plurality of normal blocks and redundant blocks in FIG. 1. The figure which shows an example of the dynamic column shift operation | movement when there exists one defect in the block <0> of I / O 1 in the SRAM of FIG. Dynamic column shift in the SRAM of Figure 1 when I / O 1 block <0> has a first defect and I / O 2 block <1> has a second defect The figure which shows an example of operation | movement. FIG. 2 is a circuit diagram showing an example of a logic configuration of a shift control circuit that controls the column shift circuit shown in FIG. 1. The figure which shows schematically the structure of a part of SRAM which has the conventional dynamic column shift system redundant circuit. The figure which shows the operation example of the conventional dynamic column shift system redundant circuit in detail.

Explanation of symbols

10 ... Memory cell array, 11 ... Normal block, 12, 14, 17 ... Multiplex circuit, 14,18 ... Global sense amplifier, 15 ... Common data line for normal block, 12 ... Redundant block, 19 ... Common data for redundant block Lines: 13 ... row decoder, 14 ... I / O circuit part, 15 ... column shift circuit, 16 ... shift control circuit.

Claims (3)

A semiconductor memory device having a dynamic column shift type redundant circuit capable of dynamically performing column shift in each input / output circuit unit of an input / output circuit unit composed of a plurality of input / output circuits,
A memory cell array having a normal block in which normal memory cells are arranged and a redundant block in which redundant memory cells are arranged, the columns of the redundant block are divided into N, and different column addresses are assigned to the respective divided column bundles; ,
A column shift circuit capable of switching a connection relationship between a block used in the memory cell array and an input / output circuit unit;
A pre-stored bad column address is compared with the input address, and if they match, a shift control circuit that dynamically controls the column shift operation of the column shift circuit to replace the defective column with a redundant column,
A semiconductor memory device, wherein N repairable addresses are designated. The normal memory cells are arranged in units of a normal block having a plurality of columns, and the block data line of the normal block is connected to the common data for the normal block via the multiplex circuit for the normal block. Connected to the wire,
The redundant memory cell has at least one redundant block having a plurality of columns equal to the number of columns of the normal block;
2. The semiconductor memory device according to claim 1, wherein the common data line for the normal block and the block data line for the redundant block are connected to the input / output circuit section through the multiplex circuit.   The shift control circuit dynamically shifts the connection relationship between the block to be used and the input / output circuit unit to one side in the block arrangement direction starting from a block in which a defective column exists in the memory cell array. 3. The semiconductor memory device according to claim 2, wherein the defective column is replaced with a redundant column.

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