JP2009090019A - Game machine security chip and game machine verification machine - Google Patents

Abstract

The present invention provides sufficient secrecy and, when necessary, ensures sufficient security so that information can be read from outside and the state of a bus can be confirmed.
A security chip for gaming machine according to the present invention includes a collation machine level judgment means for judging a setting level of a collation machine when a collation machine capable of setting at least two or more levels is connected. And when it is determined that the level set in the verification machine is a certain level, the user program of only a specific type of security chip permitted by the verification machine is read and the data on the bus in the security chip is output. When it is determined that the level set in the collator is higher than the level, the user program in all types of security chips is read and the data on the bus in the security chip is output. Enable.
[Selection] Figure 4

Description

  The present invention relates to a gaming machine security chip used in a gaming machine, and a gaming machine verification machine that makes it possible to read necessary information from such a security chip.

  Game machines such as pachinko machines and pachislot machines are required to undergo a predetermined inspection by an inspection organization in addition to being regulated by various laws. Such a gaming machine is equipped with a security chip including a security check circuit for preventing illegal modification of the operation.

  The security chip is generally manufactured by a security chip manufacturer and provided to each gaming machine manufacturer. When a gaming machine manufacturer develops software for a gaming machine, the security chip manufactured by the security chip manufacturer is mounted on an actual board, and the development proceeds while testing the operation. For this reason, when the final control program code and other data to be sold are created, a chip equivalent to that for mass production required for inspection by an inspection organization, that is, a chip to which a security code is assigned is required.

  The organization that provides the security chip code, when requested by the gaming machine manufacturer, performs a predetermined calculation such as a hash calculation based on data such as a program written by the gaming machine manufacturer, and the data written by the gaming machine manufacturer A security code that is uniquely determined by is generated and written in a predetermined area in the security chip. The security chip in which the security code is written is inspected by an inspection organization after being mounted on an actual gaming machine. The same machine as the gaming machine that has passed this inspection can be sold, and at the time of mass production, a gaming machine equipped with a security chip in which the same ROM content as this machine is copied is delivered to each gaming hall or the like.

  The security chip to which the security code is written executes a security check when the gaming machine is powered on. In other words, it is determined whether or not the code generated by the same calculation method as the organization that assigns the security code based on the data such as the program written in the memory of the security chip matches the security code written in advance. To do. If a part of the program or data is modified, the code generated at that time will not match the security code written in advance, so the gaming machine determines that the program or data has been modified, and At this point, the operation of the central processing unit (CPU) is stopped. By such a mechanism of the security chip, alteration of the game machine program and the like is prevented.

  Mass-produced security chips will be installed in gaming machines and distributed widely in the gaming machine market. If anyone can easily read the content recorded in the memory of such a security chip, the Service-to-Self manufactures a forged chip based on the read program, or the content of a highly confidential program It is assumed that the contents of the program to be protected as intellectual property are imitated by analyzing the above.

  On the other hand, if the contents recorded in the memory of the security chip cannot be read at all after the gaming machine enters the market, normal operation and abnormal operation cannot be determined outside the security chip. Inconvenience also arises from the viewpoint of management.

  The present invention has been made under such circumstances, and has sufficient secrecy for important information such as programs recorded inside, and has secured sufficient security when necessary. Therefore, it is an object of the present invention to provide a gaming machine security chip and a collator that can read these information from outside and check the state of the bus.

  In order to solve the above problems, a central processing unit for controlling the operation of the gaming machine and a user memory in which a user program and a security code of the gaming machine are written are included, and based on the security code when the gaming machine is activated A security chip for a gaming machine that executes a security check, and when a verification machine capable of setting at least two or more levels is connected, a verification machine level determination means that determines a setting level of the verification machine And when the level set in the verification machine is determined to be the first level, the user program is read out only on a specific security chip permitted by the verification machine and on the bus in the security chip. Data output is permitted, and a second level higher than the first level is set in the collator. Le and when it is determined, characterized in that to enable the output of data on the bus without the reading and the security chip of the user program in the security chip regardless of the type.

  For the security chip, when at least the third and fourth levels are prepared between the first level and the second level, and the level set in the collator is determined to be the third level. Only the specific security chip permitted to the verification machine is allowed to read the user program, and the output of data on the bus in the security chip is prohibited, and the level set in the verification machine is the fourth level. When it is determined that the user program is not read, it is possible to output data on the bus in the security chip only when it is a specific security chip permitted by the collator. You can also.

  The identification of whether or not the specific security chip is permitted by the verification machine depends on whether or not the identification information given to the verification machine matches the identification information written in the program management area of the user memory. The security chip for gaming machines according to claim 1 or 2, which is to be performed.

  Further, the gaming machine security chip may have a function of stopping the operation of the gaming machine security chip based on a signal from the matching machine when the setting level of the matching machine is a predetermined level. .

  In order to solve the above problems, a central processing unit for controlling the operation of the gaming machine and a user memory in which a user program and a security code of the gaming machine are written are included, and based on the security code when the gaming machine is activated A gaming machine verification machine that permits reading of data stored in the user memory and output of data on the bus from a security chip for gaming machines that executes security checks, and can be set at at least two or more levels. And a level setting means that, when connected to the gaming machine security chip, has its setting level determined by the level determining means of the gaming machine security chip, the setting level being the first level When reading a user program only for a specific security chip and before When data on the bus in the security chip can be output and the setting level is a second level higher than the first level, reading of user programs in all types of security chips and in the security chip It is possible to output data on the bus.

  With respect to the gaming machine collating machine, at least the third and fourth levels can be set between the first level and the second level by the level setting means, and the setting level is the third level. When it is possible to read out the user program only for a specific security chip permitted by the collator, it is impossible to output data on the bus in the security chip, and the setting level is the fourth level. The user program cannot be read, but only when a specific security chip is used, data on the bus in the security chip can be output.

  Whether the specific type of security chip is identified depends on whether the identification information given to the verification machine matches the identification information written in the program management area of the user memory of the gaming machine security chip. The game machine collation machine according to claim 5 or 6, which is performed.

  The gaming machine collating machine can be provided with a function of stopping the operation of the security chip of the gaming machine when the set level is a predetermined level.

  As described above, by setting a level in advance between the security chip for gaming machines and the matching machine for gaming machines, for example, by setting a high level for administrative agencies or inspection agencies, Data can be read from the security chip and the bus status can be checked, and by setting a low level for the gaming machine manufacturer, data can be read only from the company's security chip and the bus status can be checked. It becomes possible to make it possible. This provides sufficient confidentiality for important information such as programs recorded inside, and when necessary, it is possible to read these information from outside and check the bus status after ensuring sufficient security. It becomes possible, and the above-mentioned inconvenience can be solved.

  An embodiment of a gaming machine security chip according to the present invention will be described below with reference to the drawings.

  In the present embodiment, for example, different levels are set for the verification machine provided from the security chip manufacturer to the inspection organization and the verification machine provided to the gaming machine manufacturer, and stored in the ROM in the security chip based on those levels. In addition to controlling whether or not to read out user programs, etc., and whether or not to output from the bus to the external terminal, the verification machine provided to the gaming machine manufacturer is included in the security chip of the gaming machine manufactured by each gaming machine manufacturer. However, the ROM data in the security chip of the gaming machine manufactured by another company cannot be read out.

  In order to realize this, the security chip side can determine the level set for each connected collator. Specifically, the highest level is given to the verification machine owned by the inspection organization, and the verification machine having such a level obtains data such as user programs from the security chips of gaming machines of all manufacturers. The data on the internal bus can be taken out from reading and external terminals. On the other hand, a lower level is assigned to the verification machine provided to the gaming machine manufacturer, and if it is determined to be a verification machine of this level, only the security chip of the gaming machine developed by that manufacturer is used. In addition, data such as user programs can be read and data on the internal bus can be output from external terminals, and user programs cannot be read from security chips of game machines developed by other manufacturers.

  FIG. 1 shows a connection between a security chip 3 and a verification machine 4 in order to read a user program stored in a ROM in a security chip 3 mounted on a gaming machine control board 2 in the gaming machine 1 The state in which the collator 4 and the personal computer 5 are connected is shown. In the case of FIG. 1, the user program stored in the ROM of the security chip 3 is read out in the same manner as the ROM writer and displayed on the screen of the personal computer 5.

  FIG. 2 shows a state in which the collator 4 and the logic state analyzer 6 are connected to the security chip 3 in order to observe the bus state (bus output) in the security chip 3 from an external logic state analyzer or the like. . In the case of FIG. 2, a signal permitting output from the bus to the external terminal is sent from the verification device 4 to the security chip 3 as described later, whereby the bus signal is output to the outside. .

  FIG. 3 shows a state in which the security chip 3 is removed from the gaming machine 1 and mounted in the collator 7 and a personal computer 5 is connected to the collator 7 in order to read out the user program stored in the ROM of the security chip 3. Is shown. Usually, as shown in FIG. 3, the type of collation machine 7 that removes the security chip 3 from the gaming machine 1 and collates via the socket is provided only to the inspection organization and not to the gaming machine manufacturer. Thus, the collation machine 7 of the type in which the security chip 3 is removed from the gaming machine 1 can be compared and collated with the certified chip, and the highest level is set. 3 can perform the collating operation as shown in FIG. 1 or 2 with the security chip 3 attached to the gaming machine 1.

  In addition, there is a function of stopping the operation of the security chip as a function provided in the verification machine provided to the inspection organization, which is not provided in the verification machine provided to the gaming machine manufacturer. This is because a regular security chip is certainly present in the gaming machine, but the control means incorporating the program for actually controlling the gaming machine is illegally attached elsewhere, and the gaming machine is controlled by the control means. It is a function for discovering fraud such as controlling so that it is advantageous to the fraudster. You can determine whether the security chip is legitimate if you just connect the verification machine to the operating game machine, but the program that controls the operating game machine is stored in the security chip. It is impossible to determine whether the program is an unauthorized program stored in a part illegally attached by an unauthorized person.

  However, by providing a function for forcibly stopping a program running on a regular security chip, it is possible to easily identify an unauthorized program running. In other words, a special level collator is instructed to stop the program, and this command actually stops the program. For example, by confirming that the liquid crystal screen actually stops, the regular program operates. Can be easily confirmed.

  FIG. 4 is a block diagram of a circuit of the security chip 3 shown in FIGS. In the figure, a central processing unit (CPU) 10 controls the overall operation of the gaming machine. The user memory is composed of a user ROM 12 and a user RAM 14. The user ROM 12 stores a user program developed by a gaming machine manufacturer that develops and manufactures pachinko and the like, and necessary data. The user RAM 14 stores a game operation. Necessary work data is temporarily stored.

  Reference numeral 16 denotes a map switching circuit, which has three modes prepared in the security chip 3 from the mode control circuit 24 through the output control signal generation circuit 26, that is, “security mode”, “PROM mode”, “ When any signal of “user mode” is input, the memory map is switched to a memory map prepared in advance according to each mode. Here, the “security mode” is a mode in which, in addition to performing a security check of the user ROM 12 by the security check circuit 52, setting of a circuit to be used in the user mode is performed. The “user mode” is a mode for executing the user program written in the user ROM 12. When the mode is shifted to this mode, the user program is executed from the reset address of the user ROM. The “PROM mode” is a mode in which a user program is read from and written to the user ROM.

  The boot ROM 18 is a memory that stores a program that starts up at startup, and the boot RAM 20 is a RAM that is used at startup. The clock circuit 30 receives the clock signal of the substrate and supplies the clock signal to the entire chip. The output control signal generation circuit 26 outputs a control signal corresponding to any one of “security mode”, “PROM mode”, and “user mode”, and buffers 32, 34, 36, 38, 40 via the bus 50. And controls whether each buffer can be input or output. The security check in the security mode is executed by the security check circuit 52.

  Of the buffers 32, 34, 36, 38, and 40, the buffer 32 controls the output of the control output control signal, the buffer 34 controls the input and output of addresses, and the buffer 36 inputs the data. The buffer 38 controls the input of parallel data, and the buffer 40 controls the output of a chip select signal from the address decoding circuit 44. If bus output is permitted with a logic state analyzer or the like connected to the security chip, these outputs can be read by the logic state analyzer. Whether or not to output from the buffers 32, 34, and 36 is controlled by signals from each mode and the collator. When the bus output is prohibited in the user mode, the buffers 32, 34, and 36 are not output at the access timing to the internal devices (user ROM 12, user RAM 14 and other application circuits (not shown)), and are set as external devices. This is output only when the memory or I / O map is accessed. When the bus output is permitted, all bus states are output.

  The security chip of FIG. 4 is further provided with a special request circuit 54 and a verification block 56. The verification block 56 performs serial communication with the verification communication circuit 66 (see FIG. 6) in the verification machine when the verification machine 4 of FIGS. 1 and 2 and the verification machine 7 of FIG. 3 are connected. The level set in the verification machine is detected, and if a low level verification machine is connected, the manufacturer to which the verification machine is provided is specified. The special request circuit 54 recognizes this when the collator makes a ROM read, bus output, and CPU stop request, and sends it to the mode control circuit 24.

  FIG. 5 is a block diagram showing the details of the verification block 56, the special request circuit 54, and the mode control circuit 24 in the security chip 3 shown in FIG. The verification block 56 includes a verification communication circuit, an authentication control circuit, and a level storage circuit. Of these, the verification communication circuit is a circuit that communicates with the verification machine. As a result of the communication, the authentication control circuit outputs a special request signal according to the level of the level storage circuit (which will be described later). The special request circuit 54 includes a special request analysis circuit and a request output circuit. The special request analysis circuit analyzes the special request signal from the verification block 56, and the request output circuit outputs each request based on the result. Output to the mode control circuit 24.

  The mode control circuit 24 includes a request reception circuit, a mode storage circuit, a ROM read request information storage circuit, a bus output control information storage circuit, a CPU stop request information storage circuit, and a control output circuit. In response to each request received from the special request circuit 54, the request receiving circuit outputs each control signal based on the mode stored in the mode storage circuit.

  FIG. 6 is a block diagram of a control device of the collator 7 that can connect to the security chip 3 from the outside and exchange predetermined signals with the security chip 3. The operation of the CPU 60 is controlled by a program stored in the ROM in the storage circuit 62 (including ROM and RAM). At that time, the RAM of the storage circuit 62 is used as a work area as necessary. The ROM of the storage circuit 62 stores a manufacturer code that can specify the gaming machine manufacturer to which the verification machine is provided (see FIG. 7).

  The clock circuit 64 supplies a necessary clock signal to the entire verification machine. The verification communication circuit 66 communicates with the verification block 56 (see FIGS. 4 and 5) of the security chip by connecting the verification machine to the security chip. Similarly to the verification circuit 56 of the security chip 3, the verification communication circuit 66 includes a level storage circuit (not shown). This communication is serial communication as described above. The display control circuit 70 turns on the LEDs representing “OK” and “NG” based on the result of the collation operation, and displays an operation explanation and the collation result on the LCD.

  The external I / F control circuit 72 outputs a collation result from the collator to the printer, and controls communication with a personal computer or an online monitoring device. The collation control circuit 74 starts the collation operation when there is an input to that effect from the collation start switch. Further, when there is an input to the verification control circuit 74 from the CPU stop SW, a control signal for stopping the operation of the CPU of the gaming machine is generated as will be described later.

  The chip signal input / output control circuit (for inspection chip) 68 and the chip signal input / output control circuit (for certified chip) 78 are circuits used when the security chip is removed from the board of the gaming machine and placed on the verification machine for inspection. It is. Therefore, in the case of a verification machine that is normally provided to a gaming machine manufacturer, it can be supplied without providing this part of the circuit, or even if this part is provided, it can be used by anyone other than those who have the prescribed authority. There may be provided means for prohibiting the above.

  The chip signal input / output control circuit (for inspection chip) 68 is a circuit that controls input / output of signals from the inspection target chip when the security chip for mass production is removed from the board of the gaming machine and inspected. . A chip signal input / output control circuit (for a copy chip) 78 is a circuit used when a test is performed with a copy security chip attached, and controls input / output of signals from the copy chip. Here, the inspection using the certified chip means that the certified chip and the chip to be inspected are respectively attached to the collator, and that there is no difference in the signal from each chip or the contents of the user ROM. This is an inspection method for discriminating that the chip is genuine.

  FIG. 7 is a memory map of the user ROM 12 in the security chip shown in FIG. As can be seen from the diagram on the left side of FIG. 7, the interior of the user ROM 12 is roughly divided into a “program code area”, a “program data area”, and a “program management area”. In the “program code area” and “program data area”, programs and data for controlling the actual operation of the gaming machine are written.

  For example, a 128-byte storage area is prepared in the program management area, and information necessary for managing the program is stored therein. Specifically, as shown on the right side of FIG. 7, the “header”, “maker code”, “product code”, “program code end address”, “various settings”, “unusable area” described above. , “Read RAM area” and “security code”.

  When a game machine manufacturer executes development of game machine software, a program for controlling the game machine of the company is written in the “program code area” and “program data area” of the user ROM. As for the program management area, necessary information is written in an area other than the security code. When the development of new gaming machine software is completed and the necessary code is written by the gaming machine manufacturer, the organization that provides the security code generates the security code based on the information written in the user ROM. Is written in the security code area of the program management area. Based on the chip in which the security code is written in this way, the gaming machine manufacturer takes a type test of a predetermined engine. Then, based on the chips that have passed this test, data is copied to the mass production chips and mounted on the actual gaming machine.

  FIG. 8 shows levels that can be set in the level storage circuit included in the verification communication circuit 66 of the verification machine (in this embodiment, five levels of levels 0, 1, 2, 3, and 4), The operations that can be performed at each level are shown as a table. When the level set in the collator is level 0, the reading of the user program from the ROM and the output of the bus in the security chip 3 are the same as the manufacturer code (see FIG. 7) stored in the security chip built-in ROM. This is possible only when the manufacturer code (see FIG. 6) stored in the ROM of the collator 7 matches. At level 1, the user program cannot be read from the ROM, but the bus can be output. At level 2, the user program can be read from the ROM, but the bus cannot be output. At level 3, the user program can be read from the ROM and the bus can be output.

  At level 4, the user program can be read from the ROM and the bus can be output, and the operation of the security chip can be stopped by an instruction from the collator. By actually stopping the program by such a function, for example, by confirming that the liquid crystal screen is actually stopped, it is possible to easily confirm that the regular program is operating.

  Next, the operation of the security chip when it is possible to read the user program stored in the ROM of the security chip of the gaming machine and output the data on the bus will be described with reference to the flowchart of FIG. . In order to read out ROM and output bus data by the collator, the collator is connected to the gaming machine in advance, and the security chip recognizes the level set in the collator and performs level authentication. If the level is “0”, the mutual manufacturer codes (corresponding to “identification information” in the claims) are compared as described above, and it is determined whether or not the two manufacturer codes match. However, only when they match, the subsequent read operation is possible, and the ROM read request signal and the bus output request signal are given to the gaming machine from the collator.

  When a system reset is entered in the mode control street 24 of FIG. 4 with a regular collator connected (XSRST = Low) (S1), it is checked whether or not the PRG terminal is High (S2). Here, when the PRG terminal is not High, the PROM mode is entered (S3). However, in the chip where ROM reading is prohibited this time even when the PROM mode is entered, the program in the ROM cannot be read, and only the program write (one time) and verify commands are accepted. Each is executed when there is. On the other hand, when the PRG terminal is High in S2, the mode shifts to the security mode (S4).

  When the mode is shifted to the security mode, it is monitored whether there is a ROM read and other requests after S5. When the ROM read and other requests are accepted, the level verification of the collator described above and the mutual manufacturer code confirmation are performed, and the same authentication and confirmation is also a determination condition when a subsequent request is accepted. The ROM read request in S5 is a request issued from the collator 4 shown in FIG. 1 and FIG. 2 or the collator 7 shown in FIG. 3. When there is a ROM read request, a ROM read setting flag is set, The flag is read later, and the program in the ROM can be read (S6). On the other hand, if there is no ROM read request in S5, the presence or absence of a bus output request is confirmed in S7. If there is a bus output request in S7, a flag for setting the bus output permission is set, and when the user program is executed, the output control signal generation circuit 26 outputs the output control signal of each buffer (ADDR output control signal shown in FIG. 4). Or a DATA output control signal), the bus output can be opened (S8).

  Subsequently, a security check is performed (S9). That is, the security check circuit 52 of FIG. 4 performs a security check of the user ROM 12. If the result of this security check is NG, the CPU is stopped in S10 (S10), and if the result of the security check is OK, the mode is shifted to the user mode (S11), and the game is executed based on the user program (S11). S12). If the bus output permission setting flag is set, the output is made outside the bus at this point. Even if the flag is not set, a bus or control signal is output for external access. Thereafter, the CPU continuously monitors whether there is a CPU stop request (S13). If there is a CPU stop request, the CPU is stopped (S10).

  As described above, if the ROM read permission is set in S6, the user program stored in the ROM can be read from the collator. Specifically, the collation block 56 shown in FIG. 4 requests the special request circuit 54 to make a bus output request or a ROM read request when there is a special request from a collator outside the chip. If the bus output permission is set in S8, the output control signal generation circuit 26 in FIG. 4 outputs an output permission signal to each buffer when a bus output is requested. The output of each bus is released, and the bus output during execution of the user program can be monitored by a logic state analyzer or the like outside the chip.

  Further, the CPU stop request in S13 is a request from the collator. If the legitimate security chip is operating normally, the gaming machine should stop at that time (S10), but the gaming machine operates despite sending such a request from the verification machine. If the operation is not stopped, it is considered that an unauthorized program different from the regular chip is hidden and mounted and an unauthorized program is operating, and such an unauthorized operation can be easily detected. Note that such a CPU stop request may be attached only to a special level collator as described above.

It is the figure which showed the state which connected the security chip and the collation machine, and also connected the collation machine and the personal computer. It is the figure which showed the state which connected the collator and the logic state analyzer to the security chip. It is the figure which showed the state which removed the security chip from the game machine, mounted | worn with the collator, and also connected the personal computer to this collator. It is a block diagram of the security chip for game machines which concerns on one Embodiment of this invention. FIG. 5 is a block diagram showing in detail the extracted portions of the verification block 56, special request circuit 54, and mode control circuit 24 in the security chip 3 shown in FIG. 1 is a block diagram of a control device for a gaming machine collator according to an embodiment of the present invention. FIG. 5 is a memory map of a user ROM 12 in the security chip shown in FIG. It is the figure which showed the level which can be set to the above-mentioned level storage circuit contained in the collation communication circuit 66 of a collator, and the operation | movement which can be performed at each level as a table | surface. It is the flowchart which showed the operation | movement of a security chip when enabling the reading of the user program memorize | stored in ROM of the security chip of the gaming machine by the collator, and the output of the data on a bus | bath.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Game machine 2 Game machine control board 3 Security chip 4 Verification machine 7 Verification machine 10 CPU
12 User ROM
14 User RAM
16 Map switching circuit 18 Boot ROM
20 Boot RAM
24 mode control circuit 26 output control signal generation circuit 32, 34, 36, 38, 40 buffer 50 bus 52 security check circuit 54 special request circuit 56 collation block 60 CPU
62 Memory circuit 66 Verification communication circuit 68 Chip signal input control circuit (for inspection chip) 68
70 Display Control Circuit 74 Collation Control Circuit 78 Chip Signal Input Control Circuit (for Basic Chip)

Claims (8)

A central processing unit that controls the operation of the gaming machine, and a user memory in which a user program and a security code of the gaming machine are written, and a security for the gaming machine that executes a security check based on the security code when the gaming machine is activated A chip,
When a collator capable of setting at least two or more levels is connected, it includes collator level determination means for determining a setting level of the collator.
When it is determined that the level set in the verification machine is the first level, reading of the user program and data on the bus in the security chip are read only when the level is a specific security chip permitted for the verification machine. When output is permitted and it is determined that the level set in the collator is a second level higher than the first level, reading of the user program in the security chip and in the security chip regardless of the type A security chip for gaming machines, characterized by permitting the output of data on the bus.   At least the third and fourth levels are prepared between the first level and the second level, and when the level set in the collator is determined to be the third level, the collator When only the permitted specific security chip is allowed to read the user program, and the output of data on the bus in the security chip is prohibited, and the level set in the collator is determined to be the fourth level The method according to claim 1, which prohibits reading of a user program and enables output of data on a bus in the security chip only when it is a specific security chip permitted by the collator. Security chip for gaming machines.   The identification of whether or not the specific security chip is permitted by the verification machine depends on whether or not the identification information given to the verification machine matches the identification information written in the program management area of the user memory. The security chip for gaming machines according to claim 1 or 2, which is to be performed.   The function according to any one of claims 1 to 3, further comprising a function of stopping the operation of the security chip of the gaming machine based on a signal from the verification machine when the setting level of the verification machine is a predetermined level. The security chip for gaming machines described. A central processing unit that controls the operation of the gaming machine, and a user memory in which a user program and a security code of the gaming machine are written, and a security for the gaming machine that executes a security check based on the security code when the gaming machine is activated A gaming machine verification machine that permits reading of data stored in the user memory and output of data on a bus from a chip,
Level setting means capable of setting at least two or more levels and determining the setting level by the level determining means of the gaming machine security chip when connected to the gaming machine security chip. Prepared,
When the setting level is the first level, it is possible to read out the user program of only a specific security chip and output the data on the bus in the security chip, and the second setting level is higher than the first level. The game machine collating machine can read out user programs in all types of security chips and output data on a bus in the security chip at the level of.   At least the third and fourth levels can be set between the first level and the second level by the level setting means. When the set level is the third level, the collator is permitted. The user program can be read only by the specified security chip, but the data on the bus in the security chip cannot be output. When the setting level is the fourth level, the user program cannot be read. However, it is possible to output data on the bus in the security chip only when the security chip is a specific security chip.   Whether the specific type of security chip is identified depends on whether the identification information given to the verification machine matches the identification information written in the program management area of the user memory of the gaming machine security chip. The game machine collation machine according to claim 5 or 6, which is performed.   The game machine collation machine according to any one of claims 5 to 7, comprising a function of stopping the operation of the security chip of the game machine when the set level is a predetermined level.

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