JP2009070462A - Memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory for suppressing the increase of a current consumption (power consumption). <P>SOLUTION: This memory (diode ROM) is equipped with: a plurality of word lines 7; a plurality of bit lines 8 to be arranged so as to intersect with the plurality of word lines 7; memory cells 9 arranged on the positions where the word lines 7 and the bit lines 8 intersect with each other; and transistors 42 connected to the bit lines 8. A current driving ability of the transistor 42 is constituted so as to vary according to the positions where the bit lines 8 are arranged. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory, and more particularly to a memory including a memory cell including a diode.

  Conventionally, as an example of a memory, a cross-point type mask ROM (hereinafter referred to as a diode ROM) in which a plurality of memory cells each including a diode are arranged in a matrix is known (see, for example, Patent Document 1).

  In the conventional diode ROM disclosed in Patent Document 1, a plurality of word lines and a plurality of bit lines arranged so as to cross the plurality of word lines and adjacent to each other with a predetermined interval are provided. , A plurality of memory cells including a diode arranged at a position where the word line and the bit line cross each other, and a sense amplifier (data discrimination circuit) for discriminating data read from the selected memory cell connected to the bit line ). In this diode ROM, the sense amplifier detects the current flowing from the sense amplifier to the word line via the bit line and the diode, thereby determining the data of the memory cell. Note that the cathodes of the diodes included in each of the memory cells connected to each word line are constituted by a common impurity region.

JP 2007-5580 A

  However, in the conventional cross-point type diode ROM disclosed in Patent Document 1, the distance between the impurity regions through which the current flowing from each bit line to the end of the word line passes varies from bit line to bit line. When the distance of the impurity region between the word line and the end of the word line is short, the cell current is large, and when the distance is long, the cell current is small. For this reason, when the distance of the impurity region between the bit line and the end of the word line is short, a large current flows through the bit line, so that the current consumption (power consumption) increases as a whole. is there.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory capable of suppressing an increase in current consumption (power consumption). It is.

  In order to achieve the above object, a memory according to the present invention is arranged at a position where a plurality of word lines, a plurality of bit lines arranged so as to intersect the plurality of word lines, and the word lines and the bit lines intersect. And a selection circuit connected to the bit line, and the current drive capability of the selection circuit is configured to be different depending on the position where the bit line is arranged.

  In the present invention, as described above, by configuring the current driving capability of the selection circuit to be different depending on the position where the bit line is arranged, for example, a diode included in each memory cell connected to each word line In the case where the cathodes of these are configured by a common impurity region, if the distance of the impurity region between the bit line and the end of the word line is short, the current drive capability of the selection circuit is lowered, and the bit line and When the distance of the impurity region between the end of the word line is long and the distance of the impurity region between the bit line and the end of the word line is short by increasing the current drive capability of the selection circuit However, it is possible to suppress a large current from flowing through the wiring connecting the bit line and the data determination circuit. Thereby, it is possible to suppress an increase in current consumption (power consumption).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a cross-point type diode ROM according to a first embodiment of the present invention. FIG. 2 is a plan layout diagram showing the configuration of the cross-point type diode ROM according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 100-100 in FIG.

  As shown in FIG. 1, the mask ROM according to the first embodiment includes an address input circuit 1, a row decoder 2, a column decoder 3, a sense amplifier 4, an output circuit 5, and a memory cell array region 6. Yes. The sense amplifier 4 is an example of the “data discrimination circuit” in the present invention. The address input circuit 1 is configured to output address data to the row decoder 2 and the column decoder 3 when a predetermined address is input from the outside. A word line 7 is connected to the row decoder 2. The row decoder 2 receives the address data from the address input circuit 1 and selects the word line 7 corresponding to the input address data, and sets the potential of the word line 7 to the L level (GND = 0V). ). As a result, the potentials of the word lines 7 other than the selected word line 7 become H level (Vcc).

  The column decoder 3 is connected to a plurality of bit lines 8 arranged so as to be orthogonal to the word lines 7. The column decoder 3 receives the address data from the address input circuit 1 to select the bit line 8 corresponding to the input address data, and the selected bit line 8 and the sense amplifier 4 are connected to the p. The connection is made through the type transistor 3a. The sense amplifier 4 detects a current flowing through the bit line 8 selected by the column decoder 3 and outputs an H level signal when a current of a predetermined current or more flows through the selected bit line 8. When a current less than a predetermined current flows through the selected bit line 8, an L level signal is output. The output circuit 5 is configured to output a signal to the outside when the output of the sense amplifier 4 is input.

  In the memory cell array region 6, a plurality of memory cells 9 are arranged in a matrix. The plurality of memory cells 9 are respectively arranged at the intersections of the plurality of word lines 7 and bit lines 8 arranged so as to be orthogonal to each other. Thereby, a cross-point type mask ROM is configured. In the memory cell array region 6, a memory cell 9 including a diode 10 whose anode is connected to the bit line 8 and a memory cell 9 including a diode 10 whose anode is not connected to the bit line 8 are provided. .

  Further, in the memory cell array region 6, as shown in FIG. 3, an n-type impurity region 22 is formed on the upper surface of the p-type silicon substrate 21 so as to extend in a predetermined direction. The impurity region 22 is an example of the “impurity region” in the present invention. A plurality of impurity regions 22 are formed at a predetermined interval along a direction orthogonal to the extending direction.

  In one impurity region 22, a plurality of p-type impurity regions 23 are formed at predetermined intervals along the direction in which the impurity regions 22 extend. The single impurity region 23 and the impurity region 22 form the diode 10 of the memory cell 9. Thereby, the impurity region 22 functions as a common cathode of the plurality of diodes 10, and the impurity region 23 functions as an anode of the diode 10. In the impurity region 22, one n-type contact region 24 is formed for every eight impurity regions 23. This contact region 24 is provided in order to reduce the contact resistance of the plug 27 of the first layer described later to the impurity region 22 of the silicon substrate 21.

  A first interlayer insulating film 25 is provided so as to cover the upper surface of the silicon substrate 21. A contact hole 26 is provided in a region corresponding to the impurity region 23 and the contact region 24 of the first interlayer insulating film 25. The contact hole 26 is filled with a first-layer plug 27 made of W (tungsten). As a result, the first-layer plugs 27 are connected to the impurity regions 23 and the contact regions 24, respectively.

  A first pad layer 28 made of Al is provided on the first interlayer insulating film 25 so as to be connected to the first plug 27. The pad layer 28 is formed to be substantially square when viewed in plan (see FIG. 2). Further, a second interlayer insulating film 29 is provided on the first interlayer insulating film 25 so as to cover the first pad layer 28. A contact hole 30 is formed in a region corresponding to the first pad layer 28 of the second interlayer insulating film 29. In the contact hole 30, a second layer plug 31 made of W is embedded. On the second interlayer insulating film 29, a plurality of bit lines 8 made of Al are formed at predetermined intervals. As shown in FIG. 2, the bit line 8 is formed so as to extend in a direction orthogonal to the direction in which the impurity region 22 extends, and in the region corresponding to the diode 10 of each memory cell 9 (see FIG. 1). It is arranged so as to cross the region 22.

  Further, the data of the memory cell 9 is switched depending on whether or not the contact hole 30 is formed between the first pad layer 28 and the bit line 8 corresponding to the diode 10 of the memory cell 9. It is configured. That is, by forming the contact hole 30 corresponding to the diode 10 of the memory cell 9, the plug 31 embedded in the contact hole 30, the first pad layer 28, and the first plug 27 are used. When the bit line 8 and the impurity region 23 constituting the diode 10 of the memory cell 9 are connected, the data of the memory cell 9 is set to “1”. On the other hand, when the contact hole 30 is not formed corresponding to the diode 10 of the memory cell 9 and the bit line 8 corresponding to the diode 10 of the memory cell 9 is not connected, the memory cell 9 Is set to “0”.

  On the region corresponding to the second plug 31 of the second interlayer insulating film 29, a second pad layer 32 made of Al is formed. The second pad layer 32 is formed to be substantially square when viewed in plan (see FIG. 2). The second-layer plug 31 and the second-layer pad layer 32 are connected. Further, a third interlayer insulating film 33 is provided on the second interlayer insulating film 29 so as to cover the bit line 8 and the second pad layer 32. A contact hole 34 is provided in a region corresponding to the second pad layer 32 of the third interlayer insulating film 33, and a third layer plug 35 made of W is formed in the contact hole 34. Is embedded. As a result, the third-layer plug 35 is connected to the second-layer pad layer 32.

  On the third interlayer insulating film 33, a word line 7 made of Al is formed so as to extend along the direction in which the impurity region 22 extends. A plurality of word lines 7 are provided at predetermined intervals along a direction orthogonal to the extending direction, and are arranged above each impurity region 22. The word line 7 is connected to the plug 35 in the third layer. Here, in the first embodiment, the word line 7 and the impurity region 22 include the third-layer plug 35, the second-layer pad layer 32, the second-layer plug 31, the first-layer pad layers 28 and 1. The memory cells are connected every eight memory cells (predetermined intervals) via the plugs 27 of the layer. The plug 35, the pad layer 32, the plug 31, the pad layer 28, and the plug 27 are examples of the “first metal wiring” in the present invention. When the word line 7 corresponding to the address data input to the row decoder 2 (see FIG. 1) is selected, the potential of the selected word line 7 is lowered to the L level (GND) and selected. The potential of the word line 7 that is not present is configured to be at the H level (Vcc).

  Further, the distance from the cathode of the diode 10 below the bit line 8 arranged at the end of the eight bit lines 8 connected to the eight memory cells 9 to the word line 7 is eight bits. It is configured to be shorter than the distance of the impurity region 22 from the cathode of the diode 10 below the bit line 8 arranged at the center of the line 8 to the word line 7. The longer the distance of the impurity region 22 from the cathode of the diode 10 to the word line 7, the greater the electrical resistance from the cathode to the word line 7.

  As shown in FIG. 2, a transistor 42 connected to the bit line 8 through a metal wiring 41 is connected to one end of each of the plurality of bit lines 8. The transistor 42 is an example of the “selection circuit” in the present invention. Further, the bit line 8 and the metal wiring 41 are electrically connected through the contact portion 43. Further, the metal wiring 41 and one of the source / drain regions of the transistor 42 are electrically connected through a contact portion 44a. The other of the source / drain regions of the transistor 42 is connected to the sense amplifier 4 through the contact portion 44b. Here, in the first embodiment, the gate width W1 of the transistor 42 is arranged at the end portion more than the gate width W1 of the transistor 42 connected to the bit line 8 arranged at the center portion of the eight bit lines 8. The gate width W1 of the transistor 42 connected to the bit line 8 is configured to be smaller. As a result, since the gate width W1 is small, the current drive capability of the transistor 42 connected to the bit line 8 arranged at the center of the eight bit lines 8 is connected to the bit line 8 arranged at the end. The current driving capability of the transistor 42 is lower.

  Next, the operation of the mask ROM according to the first embodiment will be described with reference to FIGS.

  First, a predetermined address is input to the address input circuit 1. As a result, address data corresponding to the input address is output from the address input circuit 1 to the row decoder 2 and the column decoder 3, respectively. Then, by decoding the address data by the row decoder 2, a predetermined word line 7 corresponding to the address data is selected. The potential of the selected word line 7 is lowered to L level (GND), and the potential of the unselected word line 7 is set to H level (Vcc).

  On the other hand, in the column decoder 3 to which address data is input from the address input circuit 1, a predetermined bit line 8 corresponding to the input address data is selected, and the selected bit line 8 is connected to the sense amplifier 4. Is done. Then, a potential close to Vcc is supplied from the sense amplifier 4 to the selected bit line 8. When the anode of the diode 10 of the selected memory cell 9 located at the intersection of the selected word line 7 and the selected bit line 8 is connected to the bit line 8, the sense amplifier 4 sends a bit. A current flows to the word line 7 via the line 8 and the diode 10. At this time, the sense amplifier 4 detects that a predetermined current or more flows through the bit line 8 and outputs an H level signal. The output circuit 5 receives the output signal of the sense amplifier 4 and outputs an H level signal to the outside.

  On the other hand, if the anode of the diode 10 of the selected memory cell 9 located at the intersection of the selected word line 7 and the selected bit line 8 is not connected to the bit line 8, No current flows to line 7. In this case, the sense amplifier 4 detects that no current flows and outputs an L level signal. The output circuit 5 receives the output signal of the sense amplifier 4 and outputs an L level signal to the outside.

  In the first embodiment, as described above, the current drive capability of the transistor 42 connected to the eight bit lines 8 connected to the eight memory cells 9 is set to be the transistor at the end of the eight bit lines 8. By reducing the current drive capability of 42 and increasing the current drive capability of the transistor 42 at the center of the eight bit lines 8, the distance of the impurity region 22 between the word line 7 and the cathode of the diode 10 is reduced. Even when the resistance is short and the resistance is small, it is possible to suppress a large current from flowing through the wiring connecting the bit line 8 and the sense amplifier 4 by reducing the current driving capability of the transistor 42. Thereby, it is possible to suppress an increase in current consumption (power consumption).

  In the first embodiment, as described above, the gate width W1 of the transistor 42 is set to be larger than the gate width W1 of the transistor 42 connected to the bit line 8 arranged in the center of the eight bit lines 8. By configuring the transistor 42 connected to the bit line 8 disposed at the end to have a smaller gate width W1, the smaller the gate width W1, the greater the electrical resistance. The current driving capability of the transistor 42 connected to the bit line 8 arranged at the end is made lower than the current driving capability of the transistor 42 connected to the bit line 8 arranged in the central portion of the plurality of bit lines 8. be able to.

(Second Embodiment)
FIG. 4 is a plan layout diagram showing the configuration of a cross-point type diode ROM according to the second embodiment of the present invention.

  In the cross-point type diode ROM according to the second embodiment, as shown in FIG. 4, the transistor 42a is connected to one end of each of the bit lines 8 via the metal wiring 41 as in the first embodiment. Is connected. Unlike the first embodiment, the gate width W2 of the transistor 42a is the same in each transistor 42a. Further, the metal wiring 41 and the transistor 42a are connected via a contact portion 43.

  Here, in the second embodiment, the number of contact portions 44 a that connect one of the source / drain of the transistor 42 a and the metal wiring 41 is the number of the bit lines 8 arranged at the center of the eight bit lines 8. One of the source / drain of the transistor 42a connected to the bit line 8 arranged at the end, rather than the number of contact portions 44a connecting one of the source / drain of the transistor 42a connected to the metal wire 41 and The number of contact portions 44a connecting the metal wiring 41 is configured to be smaller.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  In the second embodiment, as described above, the number of contact portions 44a connecting one of the source / drain of the transistor 42a and the metal wiring 41 is set to the bit line 8 arranged in the central portion of the eight bit lines 8. One of the source / drain of the transistor 42a connected to the bit line 8 arranged at the end, rather than the number of contact portions 44a connecting one of the source / drain of the transistor 42a connected to the metal wire 41 and The number of contact portions 44a for connecting the metal wiring 41 is reduced. As a result, the larger the number of contact portions 44a, the smaller the electrical resistance. Therefore, the current drive capability of the transistor 42a connected to the bit line 8 arranged at the center of the plurality of bit lines 8 can be easily obtained. However, the current driving capability of the transistor 42a connected to the bit line 8 disposed at the end can be lowered.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first and second embodiments, the present invention is applied to the cross-point type diode ROM. However, the present invention is not limited to this, and a memory cell including a diode other than the cross-point type diode ROM is provided. It can be widely applied to memories.

  In the first and second embodiments, the current driving capability of the transistor connected to the bit line is changed by changing the gate width of the transistor connected to the bit line and the number of contact portions, respectively. However, the present invention is not limited to this, and the current driving capability of the transistor connected to the bit line may be changed by changing the impurity concentration of the source / drain region of the transistor connected to the bit line for each transistor. . Further, the current drive capability of the transistor connected to the bit line may be changed by changing the size of the region into which the impurity is implanted in the source / drain region of the transistor connected to the bit line. Further, the gate length of the transistor connected to the bit line may be changed, or a resistor may be provided between the transistor connected to the bit line and the bit line.

  In the first and second embodiments, the example in which the plug and the pad layer for connecting the word line and the wiring layer are arranged for every eight bit lines has been shown, but the present invention is not limited to this. A plug and a pad layer for connecting the word line and the wiring layer may be arranged for every bit line other than eight.

1 is a circuit diagram showing a configuration of a cross-point type diode ROM according to a first embodiment of the present invention. 1 is a plan layout diagram illustrating a configuration of a cross-point type diode ROM according to a first embodiment of the present invention; FIG. 3 is a cross-sectional view taken along line 100-100 in FIG. 2. It is the plane layout figure which showed the structure of the crosspoint type | mold diode ROM by 2nd Embodiment of this invention.

Explanation of symbols

7 Word line 8 Bit line 9 Memory cell 22 Impurity region 27 Plug (first metal wiring)
28 Pad layer (first metal wiring)
31 Plug (first metal wiring)
32 Pad layer (first metal wiring)
35 Plug (first metal wiring)
41 Metal wiring (second metal wiring)
42, 42a Transistor (selection circuit)
44a Contact part

Claims (5)

Multiple word lines,
A plurality of bit lines arranged to intersect the plurality of word lines;
A memory cell disposed at a position where the word line and the bit line intersect;
A selection circuit connected to the bit line,
The memory is configured such that a current driving capability of the selection circuit is different depending on a position where the bit line is disposed.   The current driving capability of the selection circuit is connected to the bit line arranged at the end portion rather than the current driving capability of the selection circuit connected to the bit line arranged in the central portion of the plurality of bit lines. The memory according to claim 1, wherein the current driving capability of the selection circuit is configured to be smaller. An impurity region disposed in a direction in which the word line extends;
A first metal wiring that electrically connects the word line and the impurity region at predetermined intervals;
The bit line has a plurality of bit lines arranged at a predetermined interval between the first metal wirings,
The current driving capability of the selection circuit is more than the current driving capability of the selection circuit connected to the bit line disposed in the center among the plurality of bit lines disposed between the first metal wirings. The memory according to claim 2, wherein a current driving capability of the selection circuit connected to the bit line arranged in the memory is smaller. The selection circuit includes a transistor,
The gate width of the transistor connected to the bit line arranged at the end is larger than the gate width of the transistor connected to the bit line arranged at the center of the plurality of bit lines. The memory according to claim 2, wherein the memory is configured to have a smaller width. The selection circuit includes a transistor,
A second metal wiring connecting one of the source / drain regions of the transistor and the bit line;
The number of contact portions that electrically connect one of the source / drain regions of the transistor and the second metal wiring is the number of contact portions of the transistor connected to the bit line disposed at the center of the plurality of bit lines. One of the source / drain regions of the transistor connected to the bit line disposed at the end and the number of contact portions that electrically connect one of the source / drain regions and the second metal wiring 4. The memory according to claim 2, wherein the number of contact portions that electrically connect the second metal wiring is reduced. 5.

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