JP2009065246A - Load control device - Google Patents

Abstract

When driving a load, there is a need for a technique that can suppress fluctuations in a load to be controlled even when a power supply voltage fluctuates.
A load control device omits a constant voltage source and includes a twelfth resistor R12 and a Zener diode ZD1 as duty ratio adjusting means. Conventionally, the first transistor Q1, the second transistor Q2, the third transistor Q3, the third resistor R3, the sixth resistor R6, the ninth resistor R9, the eleventh resistor connected to the output of the constant voltage source. The terminal of the resistor R11 is connected to the positive terminal of the battery BT. In addition, one terminal of the twelfth resistor R12 is connected to the positive terminal of the battery BT, the other terminal is connected to the cathode of the Zener diode ZD1, and the anode of the Zener diode ZD1 is the non-inversion of the second comparator CP2. Connected to input terminal.
[Selection] Figure 4

Description

  The present invention relates to a load control device, and more particularly to a load control device that controls a load based on a duty ratio.

  2. Description of the Related Art Conventionally, a load control device that controls a load such as a motor or a lamp by a technique called pulse width modulation (hereinafter simply referred to as “PWM modulation”) is known. A load control device that performs PWM modulation control controls the output to a desired level by changing the duty ratio in a constant cycle with respect to a fixed input.

As such a load control device, a technique for PWM modulation control of a vehicle load such as an in-vehicle lamp corresponding to two input patterns of a fixed input and a pulse input from the in-vehicle ECU is disclosed (for example, Patent Document 1). reference). In this technique, a desired control output value is obtained by comparing the generated triangular wave with a comparator.
JP 2001-148294 A

  Incidentally, the load control device described in Patent Document 1 is applied to driving a load such as a lamp mounted on an automobile, for example. In this application example, when an abnormality occurs in the automobile power generation device due to a failure or the like, the power supply voltage of the battery generally in the range of 12V to 14.5V may rise to a value of 16V or more. At this time, since the duty ratio does not change in the load control device of Patent Document 1, there is a problem that the effective power increases and the illuminance of the lamp increases more than necessary.

  When the effective power of the lamp increases, for example, when the lamp has a short lifetime or is irradiated by a lamp having an illuminance that is more than necessary, the irradiated person feels very dazzling. In automobiles, there is a need for a technology that can cause an accident and solve such problems.

  The present invention has been made in view of such a situation, and an object of the present invention is to suppress fluctuations in the load to be controlled even when the power supply voltage fluctuates when driving the load. It is to provide a technology that can be used.

One embodiment of the present invention relates to a load control device. The apparatus includes a triangular wave generating unit that generates a triangular wave voltage based on a voltage supplied when a load unit to be controlled is driven, without being supplied through a constant voltage source; and A duty ratio determining means for determining a duty ratio by comparing a triangular wave generated by the triangular wave generating means with a predetermined reference potential; and a duty ratio adjustment for decreasing the duty ratio when the power supply voltage exceeds a predetermined value. Means.
Further, the triangular wave generating means is configured to divide a power supply voltage by a capacity, a charge / discharge reference current generating means for generating a reference current for charging and discharging in the capacity, a voltage of a capacity charged by the reference current, and a resistor. A first comparator that compares the first partial pressure that has been generated.
The charge / discharge reference current generation means may include a plurality of current mirror circuits.
Further, the duty ratio determining means compares a voltage of the capacitor input to one terminal of the first comparator with a second divided voltage obtained by dividing the power supply voltage by a resistor. The comparator may be provided.
The duty ratio adjusting means may include a Zener diode and a resistor connected to a reference potential of the comparator.
The duty ratio determined by the duty determining means may be set by a resistance value of a resistor provided in the load control device.

  According to the present invention, when a load is driven, even when the power supply voltage fluctuates unintentionally, it is possible to suppress fluctuations in the load to be controlled.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the drawings. In the present embodiment, a load control device that drives a predetermined load by PWM modulation control will be described. In this load control device, a constant voltage circuit is not provided, and a triangular wave for PWM modulation control is generated by the voltage of the same voltage source as the voltage applied to the load and the drive means of the load. Further, when the power source of the voltage source increases from a predetermined voltage, the duty ratio is decreased in accordance with the increase so that the effective power of the load does not fluctuate greatly.

  First, a load control apparatus having a constant voltage source will be described, and then a load control apparatus that suppresses fluctuations in the effective voltage of the load by omitting the constant voltage source will be described.

  FIG. 1 shows a circuit diagram of a load control device 50 having a constant voltage source 52. The load control device 50 includes a power input terminal TP, an output terminal TO, a ground terminal TG, and a control terminal TC as connection terminals.

  The power input terminal TP is connected to the high potential side of the battery BT (hereinafter referred to as “power supply voltage VI” or “voltage VI”). The output terminal TO is connected to one end of the load W, and the other end of the load W is connected to the high potential side (power supply voltage VI) of the battery BT.

  Further, the ground terminal TG is connected to the low potential side of the battery BT, and is internally grounded to the ground (ground potential) GND. Note that the low potential side of the battery BT is grounded to the ground GND. A control signal of the ECU 60 is connected to the control terminal TC.

  Also, PNP-type first to third transistors Q1 to Q3 are connected in parallel to the output Vc of the constant voltage source 52. At this time, the emitter terminals of the first to third transistors Q1 to Q3 are connected to the output Vc.

  The base terminals of the first to third transistors Q1 to Q3 are connected to the collector terminal of the first transistor Q1. With this configuration, the first to third transistors Q1 to Q3 constitute a first current mirror circuit CR1.

  The collector terminal of the first transistor Q1 is connected to one terminal of the first resistor R1, and the other terminal of the first resistor R1 is grounded to the ground GND.

  The collector terminal of the second transistor Q2 is connected to the collector terminal of the NPN-type fourth transistor Q4, and the emitter terminal of the fourth transistor Q4 is grounded to the ground GND.

  The collector terminal of the second transistor Q2 is connected to one terminal of the second resistor R2, and the other terminal of the second resistor R2 is connected to the base terminal of the fourth transistor Q4.

  Further, the collector terminal of the second transistor Q2 is connected to the collector terminal of the NPN-type fifth transistor Q5, and the emitter terminal of the fifth transistor Q5 is grounded to the ground GND.

  The collector terminal of the third transistor Q3 is connected to the collector terminals of the NPN-type sixth and seventh transistors Q6 and Q7. The emitter terminals of the sixth and seventh transistors Q6 and Q7 are grounded to the ground GND, and the base terminals are connected to the collector terminal of the second transistor Q2 (the collector terminal of the fourth transistor Q4). Yes.

  With such a connection configuration, the fourth, sixth, and seventh transistors Q4, Q6, and Q7 constitute a second current mirror circuit CR2.

  In addition, one terminal of the third resistor R3 is connected to the output Vc of the constant voltage source 52, and one terminal of the fourth resistor R4 is connected to the other terminal of the third resistor R3. Furthermore, the other terminal of the fourth resistor R4 is connected to the ground GND. That is, the third resistor R3 and the fourth resistor R4 are connected in series from the output Vc of the constant voltage source 52 to the ground GND.

  The collector terminal of the third transistor Q3 is connected to the non-inverting input terminal (+) of the first comparator CP1. The inverting input terminal (−) of the first comparator CP1 is connected to a connection path between the other terminal of the third resistor R3 and one terminal of the fourth resistor R4. In addition, one terminal of a capacitor (capacitance) C1 is connected to the connection path between the collector terminal of the third transistor Q3 and the non-inverting input terminal of the first comparator CP1, and the other terminal of the capacitor C1 is connected. The terminal is grounded to the ground GND.

  One terminal of the fifth resistor R5 is connected to a connection path between one terminal of the fourth resistor R4 and the other terminal of the third resistor R3, and the other terminal of the fifth resistor R5. Is connected to the collector terminal of an NPN-type eighth transistor Q8. The emitter terminal of the eighth transistor Q8 is grounded to the ground GND.

  The base terminal of the eighth transistor Q8 is connected to one terminal of the sixth resistor R6, and the other terminal of the sixth resistor R6 is connected to one terminal of the seventh resistor R7. . The other terminal of the seventh resistor R7 is connected to the base terminal of the ninth transistor Q9. The collector terminal of the ninth transistor Q9 is connected to the output Vc of the constant voltage source 52 through the eighth resistor R8. The emitter terminal of the ninth transistor Q9 is grounded to the ground GND.

  Further, the base terminal of the fifth transistor Q5 is connected to the connection path between the other terminal of the eighth resistor R8 and the collector terminal of the ninth transistor Q9.

  The output terminal of the first comparator CP1 is connected to a connection path between the other terminal of the sixth resistor R6 and one terminal of the seventh resistor R7.

  The output Vc of the constant voltage source 52 is connected to one terminal of the ninth resistor R9, the other terminal is connected to one terminal of the tenth resistor R10, and further to the tenth resistor R10. The other terminal is grounded to the ground GND.

  Then, a non-inverting input terminal of the second comparator CP2 is connected to a connection path between the other terminal of the ninth resistor R9 and one terminal of the tenth resistor R10, so that the second comparator CP2 is inverted. The input terminal is connected to the non-inverting input of the first comparator CP1 (the collector terminal of the third transistor Q3).

  Furthermore, one terminal of the eleventh resistor R11 is connected to the output Vc of the constant voltage source 52, and the other terminal of the eleventh resistor R11 is connected to the ECU 60 via the control terminal TC.

  The terminal on the control terminal TC side of the eleventh resistor R11 and the output terminal of the second comparator CP2 are connected to the input terminals of the OR logic circuit (OR gate) LD1, respectively. The output terminal of the OR logic circuit LD1 is connected to the driving means DR. That is, the control signal is input to the driving unit DR by OR logic. The drive means DR is applied with the power supply voltage VI of the battery BT, amplifies the output signal from the OR logic circuit LD1, and outputs it to the gate terminal of the n-channel MOSFET 14. The drain terminal of the MOSFET 14 is connected to the load W through the output terminal TO. The source terminal of the MOSFET 14 is grounded to the ground GND.

  The operation of the load control device 50 having the above configuration will be described.

  The first to ninth transistors Q1 to Q9, the first to eighth resistors R1 to R8, the capacitor C1, and the first comparator CP1 constitute a so-called triangular wave generation circuit.

The first current mirror circuit CR1 generates a constant current that serves as a reference for charging and discharging the capacitor C1. The current I3 flowing from the third transistor Q3 becomes a current for charging the capacitor C1. Here, as shown in the following equation (1), the current I1 flowing from the first transistor Q1 and the current I2 flowing from the second transistor Q2 are equal to the current I3.

ここで、Ｖｃは定電圧源５２からの出力電圧、Ｖｂｅ１は、第１のトランジスタＱ１のベースエミッタ間電圧である。 The current I1 is set by the first resistor R1 and is expressed by the following equation (2).

Here, Vc is an output voltage from the constant voltage source 52, and Vbe1 is a base-emitter voltage of the first transistor Q1.

Then, the current I4 for discharging the capacitor C1 is generated by the second current mirror circuit CR2 (Q4, Q6, Q7) while satisfying the following expression (3).

  A fifth transistor Q5 functioning as a switch is connected to a base terminal of the fourth transistor Q4 via a second resistor R2. Therefore, when the fifth transistor Q5 is turned on, the base terminals of the sixth transistor Q6 and the seventh transistor Q7 are grounded to the ground GND, so that the sixth transistor Q6 and the seventh transistor Q7 are turned off. The current I4 stops flowing. Here, the saturation voltages of the sixth transistor Q6 and the seventh transistor Q7 are ignored because they are small and have little influence.

The reference potential VT1 applied to the inverting input terminal of the first comparator CP1 is created by the third to fifth resistors R3 to R5 and the eighth transistor Q8. In a state where the eighth transistor Q8 is turned off, the reference potential VT1 becomes a triangular wave upper limit potential Vb, which is expressed by the following equation (4).

When the eighth transistor Q8 is turned on, the reference potential VT1 ignores the saturation voltage of the eighth transistor Q8, and the combined resistance of the fourth resistor R4 and the fifth resistor R5 and the third resistor R3. It becomes resistance division and becomes the lower limit potential Va of the triangular wave, which is expressed by the following equation (5).

  Therefore, if the potential Vc1 of the non-inverting input terminal of the first comparator CP1 is smaller than the reference potential VT1 at a certain moment, the output of the first comparator CP1 becomes low, and the eighth transistor Q8 and The ninth transistor Q9 is turned off.

  Since the reference potential VT1 becomes the upper limit potential Vb when the eighth transistor Q8 is off, the ninth transistor Q9 is turned off, so that charge flows from the eighth resistor R8 to the base of the fifth transistor Q5, and the fifth transistor Q5 is turned on. Then, since the fourth transistor Q4, the sixth transistor Q6, and the seventh transistor Q7 are turned off, the current I2 does not flow. As a result, due to the current I3 flowing through the third transistor Q3, the capacitor C1 is charged and the upstream potential, that is, the potential of the non-inverting input terminal of the first comparator CP1 increases. When the potential Vc1 slightly exceeds the upper limit potential Vb, the output of the first comparator CP1 becomes high, and as a result, the eighth transistor Q8 and the ninth transistor Q9 are turned on.

  This time, when the eighth transistor Q8 is turned on, the reference potential VT1 is lowered to the lower limit potential Va, and when the ninth transistor Q9 is turned on, the charge of the base terminal of the fifth transistor Q5 is extracted. The transistor Q5 of 5 is turned off. As a result, the fourth transistor Q4, the sixth transistor Q6, and the seventh transistor Q7 are turned on, and the current I4 flows.

Since the current I2 is twice the current I4 as described above, the capacitance C1 is discharged with the current value of the current I3 when subtracted. Then, when the potential Vc1 of the non-inverting input terminal of the first comparator CP1 decreases and falls slightly below the lower limit voltage Va, the output of the first comparator CP1 is inverted to low. In this way, a triangular wave is obtained. At this time, the period T of the triangular wave (hereinafter also referred to as “PWM period T”) is expressed by the following equation (6).

The ninth resistor R9, the tenth resistor R10, and the second comparator CP2 constitute a circuit that generates a PWM pulse (hereinafter, pulse generation circuit PW). The reference potential Vk of the second comparator CP2 is divided by the ninth resistor R9 and the tenth resistor R10, and is expressed by the following equation (7).

  Since the inverting input terminal of the second comparator CP2 is connected to the non-inverting input terminal of the first comparator CP1, the voltage Vc1 of the non-inverting input terminal of the first comparator CP1 is lower than the reference voltage Vk. And the output of the second comparator CP2 goes high.

  The output terminal of the second comparator CP2 is input to the driving means DR via the OR logic circuit LD1. In the driving means DR, the input is inverted and output to the gate terminal of the MOSFET 14. When the control input from the ECU 60 is high, the gate voltage of the MOSFET 14 is fixed low and the MOSFET 14 is turned off, so that the load current IL of the load W becomes zero.

  When the control input goes low, the OR logic circuit LD1 enables the pulse of the second comparator CP2. When the output of the second comparator CP2 is low, the output of the driving means DR is high, and as a result, the MOSFET 14 is turned on and the load current IL flows through the load W.

FIG. 2 is a diagram showing operation timings in the load control device 50 shown in FIG. Here, the duty ratio D is a ratio of the on-time Ton to the PWM cycle T, and is expressed by the following equation (8) using the upper limit potential Vb, the lower limit potential Va, and the reference potential Vk.

つまり、抵抗値のみで決まり、定電圧源５２の出力Ｖｃが変化してもデューティ比は変化しない。 When the expressions (4), (5), and (7) are substituted into the expression (8), the duty ratio D is expressed by the following expression (9).

That is, it is determined only by the resistance value, and the duty ratio does not change even if the output Vc of the constant voltage source 52 changes.

  Incidentally, the output Vc from the constant voltage source 52 is set based on the potential of the battery BT, and the output Vc does not change even when the battery BT changes. As described above, assuming that the load control device 50 is mounted on an automobile, in the case of a battery BT with an output performance of 12 V, the output generally varies to about 14.5 V due to charging by the power generation device. It is assumed that However, when an abnormality occurs in the power generation device, the output of the battery BT may increase to 16V or more.

  FIG. 3 shows a change in effective power of the halogen bulb with respect to a change in power supply voltage when a halogen bulb rated at 60 W is driven as the load W. Here, each constant (resistance value) is set so that the duty ratio D is 20%. At this time, the effective power may increase and the illuminance may increase more than necessary.

  Therefore, a configuration that can suppress an increase in the effective power of the load W even when the output of the battery BT increases will be described below.

  FIG. 4 is a configuration diagram of the load control device 10 according to the present embodiment. 1 differs from the load control device 50 shown in FIG. 1 in that the constant voltage source 52 is omitted and that a twelfth resistor R12 and a Zener diode ZD1 are added as duty ratio adjusting means. Specifically, since the constant voltage source 52 is omitted, the first transistor Q1, the second transistor Q2, and the third transistor Q3 connected to the output Vc of the constant voltage source 52 by the load control device 50. The terminals of the third resistor R3, the sixth resistor R6, the ninth resistor R9, and the eleventh resistor R11 are connected to the positive terminal of the battery BT.

  As for the added twelfth resistor R12 and Zener diode ZD1, one terminal of the twelfth resistor R12 is connected to the positive terminal of the battery BT, the other terminal is connected to the cathode of the Zener diode ZD1, and The anode of the Zener diode ZD1 is connected to the connection path between the other terminal of the ninth resistor R9 and one terminal of the tenth resistor R10, that is, the non-inverting input terminal of the second comparator CP2.

  Since the configuration of the load control apparatus 50 in FIG. 1 is the same as that of the load control apparatus 50 in FIG. 1 except for the above-described changes in the load control apparatus 10 in FIG. 4, the description thereof will be omitted.

  Next, the operation of the load control device 10 will be described. In this load control device 10, when the voltage VI of the battery BT exceeds an arbitrary voltage VL, an increase in effective power at the load W is suppressed.

First, the Zener voltage (breakdown voltage) VZ of the Zener diode ZD1 is set to a value represented by the following equation (10).

Next, the period T of the triangular wave is expressed by the following equation (11) by replacing Vc in equation (6) with VI.

つまり、周期Ｔは、容量Ｃ１の値と、抵抗値のみで決まり、バッテリＢＴの電圧ＶＩに依存しないことが分かる。 Here, if the base-emitter voltage Vbe1 of the first transistor Q1 is about 0.6V, it can be approximated as VI−Vbe1≈VI, and therefore the period T is expressed by equation (12).

That is, it can be seen that the period T is determined only by the value of the capacitor C1 and the resistance value, and does not depend on the voltage VI of the battery BT.

Next, the duty ratio D will be examined. When the voltage VI is equal to or lower than the voltage VL, no current flows through the Zener diode ZD1 and the twelfth resistor R12. Therefore, it is expressed by the above-described equation (9). When the voltage Vc in the equations (4), (5), and (7) is replaced with the voltage VL, the duty ratio D is expressed by the following equation (13).

  That is, the duty ratio D is determined only by the resistance value, and the duty ratio D does not change with respect to the change in the voltage VI of the battery BT.

On the other hand, when the voltage VI exceeds the voltage VL, the Zener diode ZD1 is turned on. Therefore, assuming that the current flowing through the ninth resistor R9 is I9 and the current flowing through the twelfth resistor R12 is I12, the following equation (14) A simultaneous equation will hold.

When the equation (14) is solved, the reference voltage Vk is expressed by the following equation (15).

Thereby, the duty ratio D is expressed by the following equation (16).

Then, if the value of the twelfth resistor R12 is determined so as to satisfy the following equation (17) by taking out the constant applied to the voltage VI of the numerator in the equation (16), the increase in the voltage VI is effectively achieved. The duty ratio D decreases.

  With this setting, when the voltage VI further increases, the reference potential Vk exceeds the upper limit potential Vb, and the MOSFET 14 is turned off.

  FIG. 5 shows an example of a change in the effective power of the halogen bulb with respect to a change in power supply voltage when a halogen bulb rated at 60 W is driven as the load W by the load control device 10 in the same manner as in FIG.

  Here, R2 = 40 kΩ, R3 = 80 kΩ, R4 = 8.9 kΩ, R9 = 52 kΩ, R10 = 68 kΩ, R12 = 60 kΩ, VL = 12V, and VZ = 5.2V.

  As shown in the figure, when the voltage VL exceeds 12V, the duty ratio D decreases, and it can be seen that the effective power is maintained at substantially the same value as when the voltage VI is 12V. The effective power when the voltage VI = 14V is 18.5W. On the other hand, in the case of the load control device 50 under the same conditions, the effective power is 22.7W. Therefore, the effective power of the load control device 10 excluding the constant voltage source 52 shown in FIG. 4 is about 19% lower than the effective power of the load control device 50 having the constant voltage source 52 of FIG. Yes.

  As described above, according to the present embodiment, the effective power at the load W can be kept substantially constant even when the power supply voltage VI of the battery BT becomes high. Therefore, when the load W is, for example, a car lamp, the illuminance can be kept substantially constant. As a result, it is possible to avoid a phenomenon in which the lamp becomes brighter than necessary and the driver of the surrounding car is dazzled, and an improvement in safety can be expected. In addition, the life of the load W can be extended.

  In addition, when the power supply voltage (power supply voltage VI) of the battery BT rises abnormally, the current stops flowing, so that it is possible to prevent the load W from being broken due to an overcurrent flowing through the load W. For example, if the load W is a lamp, the risk of running out of the ball is reduced.

  Furthermore, since the power consumption (effective power) is reduced when the power supply voltage of the battery BT is high, the amount of work required for power generation is reduced in the case of an automobile, so that reduction in fuel consumption is realized.

  Further, since the constant voltage source 52 having a large volume and weight is omitted, the overall configuration of the load control device 10 is very simple, and a reduction in size and cost can be realized.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it is understood by those skilled in the art that various modifications can be made to the combination of the respective components, and such modifications are within the scope of the present invention. Such a modification is shown below.

  FIG. 6 is a configuration diagram of a load control device 110 according to a modification. The load control device 110 includes an output element on the high side. That is, a p-channel FET is attached as the MOSFET 14.

  FIG. 7 is a configuration diagram of a load control device 210 according to another modification. In the load control device 210, the non-inverting input terminal and the inverting input terminal of the second comparator CP2 are switched, and the Zener diode ZD1 and the twelfth resistor R12 are provided on the ground GND side.

At this time, the potential VZ for obtaining the voltage VL is expressed by the following equation (18).

The reference potential Vk when the voltage VI exceeds the voltage VL is expressed by equation (19).

The duty ratio D is expressed by the following equation (20).

The setting of the twelfth resistor R12 is expressed by the following equation (21).

  Moreover, although the above-described embodiment relates to a device that is dimmed and driven by PWM modulation control, it is applied to a device that is driven at normal brightness, and as shown in FIG. Power supply voltage to duty ratio characteristics can be provided so that power consumption does not increase more than necessary. Here, R2 = 40 kΩ, R3 = 80 kΩ, R9 = 100 kΩ, R10 = 13 kΩ, R12 = 2 kΩ, and VZ = 10V.

  Further, a part or all of the load control devices 10, 110, and 210 may be integrated into an integrated circuit (IC). Furthermore, a hysteresis may be provided in the second comparator CP2.

  Furthermore, although the battery BT whose power supply voltage VI is 12V is illustrated, the battery BT such as 24V or 36V may be used.

It is a circuit diagram of the load control apparatus which has a constant voltage source based on this embodiment. It is the figure which showed the operation | movement timing in the load control apparatus shown in FIG. 1 based on this embodiment. FIG. 6 shows a change in the effective power of the halogen bulb with respect to a change in power supply voltage when a halogen bulb rated at 60 W is driven as a load W in the load control device shown in FIG. 1 according to the present embodiment. It is a circuit diagram of the load control device which provided the Zener diode except the constant voltage source concerning this embodiment. FIG. 6 shows a change in the effective power of the halogen bulb with respect to a change in power supply voltage when a halogen bulb rated at 60 W is driven as the load W in the load control apparatus shown in FIG. 4 according to the present embodiment. It is a circuit diagram of a load control device concerning a modification of this embodiment. It is a circuit diagram of a load control device concerning a modification of this embodiment. It is the figure which showed the characteristic of the power supply voltage versus duty ratio of the load control apparatus based on the modification of this embodiment.

Explanation of symbols

10 Load control device 14 MOSFET
50 Load control device 52 Constant voltage source 60 ECU
BT battery C1 capacity CP1 first comparator CP2 second comparator CR1 first current mirror circuit CR2 second current mirror circuit DR driving means GND ground LD1 OR logic circuit Q1 first transistor Q2 second transistor Q3 3rd transistor Q4 4th transistor Q5 5th transistor Q6 6th transistor Q7 7th transistor Q8 8th transistor Q9 9th transistor R1 1st resistance R2 2nd resistance R3 3rd resistance R4 4th resistor R5 5th resistor R6 6th resistor R7 7th resistor R8 8th resistor R9 9th resistor R10 10th resistor R11 11th resistor R12 12th resistor R13 13th resistor TC Control terminal TG Ground terminal TP Power input terminal W Load ZD Zener diode

Claims (6)

A triangular wave generating means for generating a triangular wave voltage based on a voltage supplied when the load means to be controlled is driven without passing through a constant voltage source; and
A duty ratio determining means for determining a duty ratio by comparing the triangular wave generated by the triangular wave generating means with a predetermined reference potential;
Duty ratio adjusting means for reducing the duty ratio when the power supply voltage exceeds a predetermined value;
A load control device comprising: The triangular wave generating means includes
Capacity,
Charge / discharge reference current generating means for generating a charge and discharge reference current in the capacity;
2. The load according to claim 1, further comprising: a first comparator that compares a voltage of the capacitor charged by the reference current and a first divided voltage obtained by dividing a power supply voltage by a resistor. Control device.   The load control device according to claim 2, wherein the charge / discharge reference current generation unit includes a plurality of current mirror circuits. The duty ratio determining means compares a voltage of the capacitor input to one terminal of the first comparator with a second divided voltage obtained by dividing the power supply voltage by a resistor. The load control device according to any one of claims 1 to 3, further comprising:   The load control device according to claim 4, wherein the duty ratio adjusting unit includes a Zener diode and a resistor connected to a reference potential of the comparator.   The load control device according to any one of claims 1 to 5, wherein the duty ratio determined by the duty determination means is set by a resistance value of a resistor provided in the load control device.

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