JP2009059155A - Usb host controller device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a USB host controller device suitable for integrated equipment. <P>SOLUTION: A USB host controller device 1 includes: a data address selector address conversion part 21 which adds an address offset value for a descriptor region to an address to convert it into the descriptor region address of a memory 40 in the case of access to a descriptor region, and adds an address offset value for a data region to the address to convert it into the data region address of the memory 40 in the case of access to a data region; a descriptor cache memory 24 which stores the data of the descriptor region address acquired from the memory 40 on the basis of the descriptor region address when access to the descriptor region is generated; and a data buffer memory 28 which stores the data of the data region address acquired from the memory 40 on the basis of the data region address when access to the data region is generated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a USB host controller device having a USB host controller control circuit for controlling access to a memory and a CPU from a USB host controller having a master bus and a slave bus.

  In general, a USB host controller device that controls communication between a computer and a device connected by USB conforms to OHCI (Open Host Controller Interface), EHCI (Enhanced Host Controller Interface), and the like. Here, a universal serial bus (USB) host controller device has a bus separated into a master (Master) and a slave (Slave) such as AHB (Advanced High-performance Bus).

  An information device 200 having such a conventional USB host controller has the configuration shown in FIG. The information device 200 includes a USB host controller 10, a DRAM (Dynamic Random Access Memory) interface arbitration circuit 30, a DRAM 40, a CPU (Central Processing Unit) 50, another IO (Input / Output) 60, and an AHB arbitration circuit (Arbiter) 70. Prepare. The USB host controller 10 is connected to the AHB master bus 12 and the AHB slave bus 13 via the AHB interface 10A. The USB host controller 10 is connected to the AHB arbitration circuit 70 via the AHB master bus 12 and the AHB slave bus 13. Further, the AHB arbitration circuit 70 is connected to the CPU 50 and the DRAM interface arbitration circuit 30 via the CPU bus 51. The DRAM interface arbitration circuit 30 adjusts access to the DRAM 40 from the USB host controller 10 and other IOs 60. The USB host controller 10 accesses the DRAM 40 via the DRAM interface arbitration circuit 30 or the like.

  While the USB host controller 10 is operating, the CPU bus 51 is occupied, and during this time, the CPU 50 cannot use the CPU bus 51. As described above, the operation of the USB host controller 10 has a great influence on the operation of the CPU 50.

  Here, in a relatively high-spec information device such as a personal computer, the operation speed of the DRAM 40 and the bus is high, so that the operation of the CPU 50 is not significantly affected. However, so-called embedded devices such as mobile phones and HDD recorders greatly affect the operation of the CPU 50. Furthermore, in such an embedded device, power consumption and circuit cost are limited, so that the operating speed of the DRAM 40 and the bus cannot be increased as in a personal computer or the like. In addition, the processing capability of the CPU 50 cannot be equipped with a high specification like a personal computer or the like. Therefore, particularly in an embedded device, the problem of occupying the CPU bus 51 during operation of the USB host controller 10 becomes significant. As described above, the operation of the USB host controller 10 has a problem that it places a heavy burden on the embedded device.

  In particular, the USB host controller 10 compliant with OHCI or EHCI needs to access the descriptor 40 to the DRAM 40 for each frame. Accordingly, the use efficiency of the DRAM 40 of other modules is reduced by periodically accessing the DRAM 40 other than the data transfer.

  Further, the USB host controller 10 uses a 32-bit linear address and is also required to align data. Therefore, when the USB host controller 10 is to be incorporated in an existing system, the address of the existing system must be matched with the USB host controller 10. This often required significant design changes in existing systems.

  As a solution to these problems, there is a method of controlling to access the system memory only from the slave bus (see, for example, Patent Document 1). In the method described in Patent Document 1, electronic devices that operate as USB hosts are connected to each other via a memory bus, and include an embedded processor and a system memory. The bus controller integrated circuit does not dominate the system memory and simply functions as a slave. The embedded processor writes data to the host controller integrated circuit in the form of transfer-based transactions.

There is also a method of accessing the system memory via the DMA controller (see, for example, Patent Document 2). In the method described in Patent Document 2, the host controller transmits a start address and a block length to the DMA controller to retrieve data from the related system memory, and the DMA controller transmits the start address and the block address transmitted from the host controller. When the block length is received, the DMA controller retrieves the instruction data from the system memory.
Special table 2007-501472 gazette Special table 2007-502476 gazette

  However, the methods described in Patent Document 1 and Patent Document 2 described above have the following problems.

  In the method described in Patent Document 1, all information necessary for transfer must be stored in the internal RAM. Therefore, when the capacity of the internal RAM is small, there is a problem that the CPU must transfer the data to the internal RAM every time data having a large data size is transmitted. In order to avoid this, a RAM having a very large data size must be provided inside. For this reason, the CPU must perform control to permit access of the USB host controller in a timely manner. As a result, there is a problem that control with a large burden is required, and software must be rewritten to conform to OHCI and EHCI.

  In the method described in Patent Document 2, the CPU needs to arbitrate the access right to the DRAM accessed by the USB host controller. Even when arbitration is not necessary, the address space is shared between the CPU and the USB host controller. Further, since the SDRAM controller is included inside, it is difficult to share with other IOs. In the case of an embedded device, other modules may be given priority over IO such as USB. In addition, there are cases where the DRAM access frequency is high and the access method is limited. Therefore, there is a case where the latency is large when accessing the DRAM, and there is a possibility that a delay occurs in the data transfer.

  As described above, the USB host controllers described in Patent Document 1 and Patent Document 2 described above are not suitable for embedded devices.

  Therefore, an object of the present invention is to provide a USB host controller device suitable for an embedded device.

  In order to solve the above problems, the first feature of the present invention is that the USB host controller (10) having the master bus (12) and the slave bus (13) accesses the memory (40) and the CPU (50). The present invention relates to a USB host controller device (1) having a USB host controller control circuit (20) for controlling the above. That is, when the USB host controller control circuit (20) of the USB host controller device (1) according to the first feature of the present invention is accessed to the master bus (12), it determines whether the access address is a descriptor area or a data area. In the case of access to the descriptor area, the address offset value for descriptor area is added to the address and converted into the descriptor area address of the memory (40). On the other hand, in the case of access to the data area, the address for data area is used. When an access to the data address selector address conversion unit (21) that adds the offset value and converts it to the data area address of the memory (40) and the descriptor area occurs, the memory (40 ) Descriptor area address obtained from A descriptor cache memory (24) for storing data, and a data buffer memory (28) for storing data at the data area address acquired from the memory (40) based on the data area address when an access to the data area occurs And comprising.

  Here, when the slave bus (13) is accessed, a CPU bus conversion unit (29) may be further provided that converts the accessed address into an address of the CPU (50).

  Here, the data buffer memory (28) is preferably a pre-readable memory.

  Furthermore, you may further provide the descriptor memory (25) which memorize | stores beforehand the data of the one part address of the descriptor area | region address of a memory (40). In this case, when the data of the descriptor area address is not in the descriptor memory (25), the data of the descriptor area address acquired from the memory (40) is stored in the descriptor cache memory (24).

  Further, a bulk IO register (27) for storing in advance data at a part of the data area address of the memory (40) may be further provided. In this case, when the data at the data area address is not in the bulk IO register (27), the data at the data area address acquired from the memory (40) is stored in the data buffer memory (28).

  According to the present invention, by providing the data address selector address conversion unit, it is possible to prevent the address used in the USB host controller and the address used in the CPU and DRAM from competing, and when incorporating the USB device into the device, An address used in the CPU and DRAM does not depend on an address used in the USB host controller, and a convenient USB host controller device can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

(Embodiment)
A USB host controller device 1 according to an embodiment of the present invention will be described with reference to FIG. The USB host controller device 1 according to the embodiment of the present invention is used in an information device 100 which is a so-called embedded device such as a mobile phone.

  1, an information device 100 according to an embodiment of the present invention includes a USB host controller device 1, a DRAM (Dynamic Random Access Memory) interface arbitration circuit 30, a DRAM (memory) 40, a CPU 50, and another IO 60. . The USB host controller device 1 receives an access from the USB device via the USB bus 11, and outputs it to the DRAM interface arbitration circuit 30, the CPU 50, and other IOs according to the access. The DRAM interface arbitration circuit 30 arbitrates communication between the USB host controller device 1, the CPU 50 and other IOs 60, and the DRAM 40.

  The USB host controller device 1 includes a USB host controller 10 and a USB host controller control circuit 20. The USB device is connected to the DRAM 40 via the USB bus 11 and the USB host controller device 1. The USB host controller device 1 includes a USB host controller 10 connected to the AHB master bus 12 and the AHB slave bus 13 via the AHB interface 10A, and a USB host controller that controls access from the USB host controller 10 to the DRAM 40 and the CPU 50. And a control circuit 20.

  The USB host controller 10 is compliant with OHCI (Open Host Controller Interface) or EHCI (Enhanced Host Controller Interface). The USB host controller 10 inputs the access input via the USB bus 11 to the USB host controller control circuit 20 via the AHB master bus 12 or the AHB slave bus 13.

  The USB host controller control circuit 20 converts an address input from the USB host controller 10 via the AHB master bus 12 into a logical address of the DRAM 40, and communicates with the DRAM 40 via the memory of the USB host controller 20. Control access. Further, the USB host controller control circuit 20 converts an address inputted through the AHB slave bus 13 into a logical address for the CPU 50, and controls access to the CPU 50 through the CPU bus 51.

  The CPU 50 accesses the internal register of the USB host controller 10 via the AHB slave bus 13 and performs setting and control of the USB host controller 10. Further, the CPU 50 is connected to another IO 60 and a module (not shown) connected via the CPU bus 51. The CPU 50 also controls other IOs 60 and modules.

  The USB host controller control circuit 20 includes a data address selector address conversion unit 21, a descriptor memory controller 22, a data memory controller 23, a descriptor cache memory 24, a descriptor memory 25, a bulk IO register 27, a data buffer memory 28, and a CPU bus conversion. A portion 29 is provided.

  When the AHB master bus 12 is accessed, the data address selector address conversion unit 21 determines whether the access address is a descriptor area or a data area. In the case of access to the descriptor area, the data address selector address conversion unit 21 adds the descriptor area address offset value to the address, converts it to the descriptor area address of the DRAM 40, and inputs it to the descriptor memory controller 22. On the other hand, in the case of access to the data area, the data address selector address conversion unit 21 adds the data area address offset value to the address, converts it to the data area address of the DRAM 40, and inputs it to the data memory controller 23.

  The descriptor memory controller 22 accesses the descriptor cache memory 24 or the descriptor memory 25 based on the accessed descriptor area address of the DRAM 40 and requests data.

  The descriptor cache memory 24 is a memory in which the data of the descriptor area address acquired from the DRAM 40 is stored based on the descriptor area address. The descriptor cache memory 24 is generally a DRAM.

  The descriptor memory 25 is a memory in which data of a part of the descriptor area address of the DRAM 40 is stored in advance. The descriptor memory 25 is generally an SRAM (Static Random Access Memory). Here, the descriptor (Descriptor) is ED (Endpoint Descriptor), TD (Transport Descriptor), Hcca (Host Controller Communication Area), Periodic Frame List, iTD (Isochronous Transport Descriptor), qTD (Queue Transport Descriptor), siTD (Split). Transaction Transport Descriptor), Queue Head, and FSTN (Periodic Span Traversal Node).

  The data stored in the descriptor memory 25 may be arbitrarily set according to the function and specifications of the information device 100. For example, when transferring data over a large number of frames using OHCI, it is preferable to store ED in the DRAM 40 and store TD in the descriptor memory 25.

  In general, for the ED, the DRAM 40 is accessed every frame, but the value is not changed. Therefore, in the embodiment of the present invention, by storing the cached data in the descriptor cache memory 24, the data can be acquired from the descriptor cache memory 24 without accessing the DRAM 40 each time. Thereby, access between the USB host controller device 1 and the DRAM 40 can be reduced.

  On the other hand, the value of TD is rewritten by the USB host controller 10 for each transfer. When the descriptor memory 25 is an SRAM, the writing process to the descriptor memory 25 is performed at a high speed and the access to the DRAM 40 does not occur, so that the process can be speeded up.

  As described above, it is preferable that the processing system is divided according to the descriptor or data access type, and that the descriptor cache memory 24 and the descriptor memory 25 are provided for data transfer and descriptor access. Thereby, frequent access to the DRAM 40 can be reduced.

  When access to the descriptor area address occurs, the descriptor memory controller 22 determines whether or not the data of the descriptor area address is in the descriptor memory 25. If it is in the descriptor memory 25, the descriptor memory controller 22 reads the data of the descriptor area address from the descriptor memory 25 and responds to the access. On the other hand, when there is no data in the descriptor area address in the descriptor memory 25, the data of the descriptor area address is requested to the DRAM 40. When the descriptor area address data acquired from the DRAM 40 via the DRAM interface arbitration circuit 30 is stored in the descriptor cache memory 24, the descriptor memory controller 22 reads the data of the descriptor area address from the descriptor cache memory 24 and accesses it. Respond to.

  The data memory controller 23 requests data by accessing the bulk IO register 27 or the data buffer memory 28 based on the data area address of the accessed DRAM 40.

  The bulk IO register 27 is a register in which data at a part of the data area address of the DRAM 40 is stored in advance.

  The bulk IO register 27 may be a relatively small amount. This is because the data of the embedded device is generally almost continuously arranged, so that the data buffer memory 28 has a prefetching (prefetch) function, so that high-speed processing is possible.

  As data to be stored in the bulk IO register 27, commands and status data in the case of using BOT (Bulk-Only Transport) in the mass storage class or the like are suitable.

  The data buffer memory 28 is a memory in which data at the data area address acquired from the DRAM 40 is stored based on the data area address. The data buffer memory 28 is preferably a memory that can be prefetched (prefetched).

  By providing the data buffer memory 28 with a prefetch function, it is possible to store data arranged continuously in the data buffer memory 28 in advance using the prefetch function. Thus, the USB host controller device 1 according to the embodiment of the present invention can efficiently transfer data. Even when latency occurs between the DRAM 40 and the data buffer memory 28, the latency can be hidden by the prefetch function of the data buffer memory 28.

  When access to the data area address occurs, the data memory controller 23 determines whether or not the data at the data area address is in the bulk IO register 27. If the data is in the bulk IO register 27, the data memory controller 23 reads the data at the data area address from the bulk IO register 27 and responds to the access. On the other hand, when the data at the data area address is not in the bulk IO register 27, the data at the data area address is requested to the DRAM 40. When the data area address data acquired from the DRAM 40 is stored in the data buffer memory 28, the data memory controller 22 reads the data of the descriptor area address from the descriptor cache memory 24 and responds to the access.

  When the AHB slave bus 13 is accessed, the CPU bus conversion unit 29 converts the accessed address into the address of the CPU 50.

  In the CPU bus conversion unit 29, conversion is performed by adding or subtracting a constant to or from a bus address for the CPU, or conversion is performed by mapping, and the address of the AHB slave bus 13 on the USB host controller 10 side is accessed from the CPU 50 side. In this case, the address is converted so as not to compete with other devices or to be in the IO space.

  Next, with reference to FIG. 2, an address converted by the data address selector address converter 21 according to the embodiment of the present invention will be described.

  FIG. 2A is a mapping diagram of addresses input to the data address selector address conversion unit 21. The address area shown in FIG. 2A has a host controller register area used by the USB host controller 10, a descriptor area such as TD, ED, and Hcca, and a data area.

  FIG. 2B is a logical address mapping diagram of the DRAM 40. FIG. 2B corresponds to a mapping diagram of addresses output by the data address selector address conversion unit 21. FIG. 2B includes a host controller register area, another IO 60 register area, a descriptor area, and a data area. 2B, the register area, the descriptor area, and the data area in FIG. 2A are associated with each other.

  When the input address is the host controller register area, the data address selector address conversion unit 21 adds the address offset value for the host controller register area, and the address of the host controller register area shown in FIG. Convert to

  The data address selector address converter 21 converts the address of the AHB master bus 12 into an address to which the DRAM 40 is mapped. In this embodiment, the addresses of the CPU bus conversion unit 29 and the data address selector address conversion unit 21 are mapped on the same address, but may be mapped to different addresses.

  When the input address is the descriptor area, the data address selector address conversion unit 21 adds the descriptor area address offset value and converts it to the address of the descriptor area shown in FIG. A part of the address area of the descriptor area in FIG. 2B is stored in the descriptor memory 25. In the example shown in FIG. 2B, it is described that a set of one address is stored in the descriptor memory 25, but a plurality of sets of addresses may be stored in the descriptor memory 25. Good.

  If the input address is a data area, the data address selector address conversion unit 21 adds the data area address offset and converts it to the address of the data area shown in FIG. A part of the address area of the data area in FIG. 2B is stored in the bulk IO register 27. In the example shown in FIG. 2B, it is described that a set of one address is stored in the bulk IO register 27, but a plurality of sets of addresses are stored in the bulk IO register 27. May be.

  With reference to FIG. 3, a process when an access occurs in the USB host controller device 1 according to the embodiment of the present invention will be described.

  First, when an access occurs in the AHB master bus 12 in step S1, it is determined in step S2 whether the accessed address is a data area or a descriptor area. At this time, the determination is made based on the address mapping shown in FIG.

  If it is determined in step S2 that the area is a data area, the process proceeds to step S3. In step S3, the data area address offset value is added to the accessed address, and the address in the DRAM 40 is output.

  Next, in step S4, it is determined whether or not the address output in step S3 is the address of the bulk IO register area in FIG. If it is the address of the bulk IO register area, in step S7, the bulk IO register 27 is accessed to obtain the data at that address.

  On the other hand, if it is determined in step S4 that the address output in step S3 is not the address of the bulk IO register area in FIG. 2B, the process proceeds to step S5. In step S5, the data at the address is requested to the data buffer memory 28. In step S6, the DRAM 40 is accessed, the data at the address is stored in the data buffer memory 28, and the data at the address is acquired.

  On the other hand, if it is determined in step S2 that the area is a descriptor area, the process proceeds to step S8. In step S8, the descriptor area address offset value is added to the accessed address, and the address in the DRAM 40 is output.

  Next, in step S9, it is determined whether or not the address output in step S8 is the address of the descriptor memory area in FIG. If it is the address of the descriptor memory area, in step S10, the descriptor memory 25 is accessed to obtain the data at that address.

  On the other hand, if it is determined in step S9 that the address output in step S8 is not the address of the bulk IO register area in FIG. 2B, the process proceeds to step S11. In step S11, the data of the address is requested to the descriptor cache memory 24. In step S12, the DRAM 40 is accessed, the data at the address is stored in the descriptor cache memory 24, and the data at the address is acquired.

  According to the USB host controller device 1 according to the embodiment of the present invention, the address input from the AHB master bus 12 and the AHB slave bus 13 connected to the USB host controller 10 is a data address selector address conversion unit. At 21, the logical address of the DRAM 40 is converted. Thereby, the address used by the CPU 50 and the DRAM 40 and the address used by the USB host controller 10 do not conflict. Therefore, the consistency between the addresses of these existing devices and the address when connecting the USB host controller without changing the design of the existing devices such as the DRAM interface arbitration circuit 30, DRAM 40, CPU 50, and other IO 60. Can keep.

  Further, in the USB host controller device 1, the addresses of various descriptor areas and the addresses of the data areas are separated. Accordingly, the address selector for data 21 can easily separate the address of the descriptor from the address of the data.

  Further, since the data buffer memory 28 equipped with the pre-read function is provided, the data in the DRAM 40 can be read into the data buffer memory 28 in advance. As a result, even when the access latency of the DRAM 40 is large, the latency can be hidden. Here, especially in embedded devices, since transfer data is often arranged continuously, the effect of shortening the response time by the prefetch function of the data buffer memory 28 is great. On the other hand, the descriptor data is not always the same as the transfer data with a small transfer capacity and continuous addresses. Therefore, the descriptor cache memory 24 performs small capacity caching. In this manner, since the processing system for the descriptor and the transfer data is separated, access to the DRAM 50 can be realized according to the characteristics of the descriptor and the transfer data. If the same processing is performed on the descriptor and the transfer data, for example, prefetching of the descriptor data causes a problem such as a significant deterioration in processing performance. However, according to the embodiment of the present invention, such a problem occurs. do not do.

  According to the USB host controller device 1 according to the embodiment of the present invention, the descriptor memory 25 and the bulk IO register 27 further have a memory area mapped to the address of the DRAM 40. As a result, high-speed processing can be performed without accessing the DRAM.

  Here, the data of the DRAM 40 can be acquired by reducing each memory capacity to the necessary minimum and reading the data from the DRAM 40 to the descriptor cache memory 24 or the data buffer memory 28. Therefore, the data sizes of the descriptor cache memory 24, the descriptor memory 25, the bulk IO register 27, and the data buffer memory 28 may be arbitrarily determined. Data that is not stored in each memory may be stored in the DRAM 40. The capacity of each memory may be determined according to the function of the information device 100, required performance, and the like.

FIG. 1 is a diagram illustrating a USB host controller device and an information device including the USB host controller device according to an embodiment of the present invention. FIG. 2 is a diagram for explaining address conversion by the data address selector address converter in the embodiment of the present invention. FIG. 3 is a flowchart for explaining processing of the USB host controller device when the AHB master bus is accessed in the embodiment of the present invention. FIG. 4 is a diagram for explaining a conventional USB host controller device and an information device including the USB host controller device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 USB host controller apparatus 10 USB host controller 11 USB bus 12 AHB master bus 13 AHB slave bus 20 USB host controller control circuit 21 Data address selector address conversion part 22 Descriptor memory controller 23 Data memory controller 24 Descriptor cache memory 25 Descriptor memory 27 Bulk IO register 28 Data buffer memory 29 CPU bus converter 30 DRAM interface arbitration circuit 40 DRAM
50 CPU
51 CPU bus 60 Other IO
70 AHB arbitration circuit 100, 200 Information equipment

Claims (5)

A USB host controller device having a USB host controller control circuit for controlling access to a memory and a CPU from a USB host controller having a master bus and a slave bus,
The USB host controller control circuit
When the master bus is accessed, it is determined whether the access address is a descriptor area or a data area. When accessing the descriptor area, the address offset value for the descriptor area is added to the address, and the descriptor of the memory is On the other hand, in the case of access to the data area, a data address selector address conversion unit for adding a data area address offset value to the address and converting it to the data area address in the case of accessing the data area,
When an access to the descriptor area occurs, a descriptor cache memory that stores data of the descriptor area address acquired from the memory based on the descriptor area address;
When access to the data area occurs, based on the data area address, a data buffer memory that stores data of the data area address acquired from the memory;
A USB host controller device comprising:   The USB host controller device according to claim 1, further comprising a CPU bus conversion unit that converts the accessed address into an address of the CPU when the slave bus is accessed.   The USB host controller device according to claim 1, wherein the data buffer memory is a pre-readable memory. A descriptor memory for storing in advance data of a part of the descriptor area address of the memory;
4. The data of the descriptor area address acquired from the memory is stored in the descriptor cache memory when the data of the descriptor area address is not in the descriptor memory. 5. The USB host controller device described in 1. A bulk IO register that pre-stores data at a part of the data area address of the memory;
5. The data area address data acquired from the memory is stored in the data buffer memory when the data area address data is not in the bulk IO register. The USB host controller device according to the item.

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