JP2009048753A - Semiconductor memory device and data storage method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that data having multi-dimensional space cannot be treated by low power consumption in a conventional semiconductor memory device. <P>SOLUTION: The device is a semiconductor memory device storing data having multi-dimensional space based on coordinate information of data, the device has a cell array 17 in which memory cells storing data are arranged in a lattice pattern, a word line selector 16 selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction, write-amplifier/sense-amplifier 18 writing/reading data to/from the memory cells arranged in a column direction, an amplifier selector 19 inputting/outputting the data to/from the selected one of the write-amplifiers/sense-amplifiers, and address conversion circuit 15 generating a row address CAX to be supplied to the word line selector 16 based on the coordinate information of the data, and generating a column address CAY to be supplied to the amplifier selector 19 by converting the coordinate information of the data into one-dimensional information. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The semiconductor memory device and the data storage method according to the present invention particularly relate to a semiconductor memory device having a cell array in which memory cells are arranged in a lattice shape, and a data storage method for the semiconductor memory device.

  In recent years, with the advancement of information processing, it has been required to increase the data processing speed. In information processing, data having a multidimensional space, such as matrix calculation or image processing, may be handled. For example, in image processing, display devices are becoming higher definition, and it is required to display more pixels at a higher speed. Therefore, by using a storage device having storage cells arranged in a lattice pattern, reproducing a multidimensional space on the storage device, and associating an address on the data space with an address on the storage device, data processing It has been proposed to increase the speed. Examples of such data processing methods are disclosed in Patent Documents 1 to 4.

  A block diagram of the semiconductor memory device disclosed in Patent Document 1 is shown in FIG. In this example, image data is stored in an information storage unit having storage cells arranged two-dimensionally. Then, using the temporary matrix number generation unit 102, the column correspondence conversion unit 103, and the row correspondence conversion unit 104, the row number and the column number for specifying the memory cell are switched. As a result, in Patent Document 1, a high-speed matrix replacement process for image data is realized.

  A block diagram of the semiconductor memory device disclosed in Patent Document 2 is shown in FIG. In this example, after a two-dimensional image is once written in the memory cell array 210, the combination of the row address and the column address is changed by the selection circuits M1 and M2, thereby performing image rotation conversion processing or line symmetry conversion processing. As a result, in Patent Document 2, it is possible to increase the speed of image rotation conversion processing or line symmetry conversion processing.

  A block diagram of the semiconductor memory device disclosed in Patent Document 3 is shown in FIG. In this example, the semiconductor memory device has a plurality of subarrays 306-0 to 306-7, and stores data in different rows of rectangular data in different subarrays. Then, data writing and reading are performed in parallel, thereby realizing high-speed processing.

A block diagram of the semiconductor memory device disclosed in Patent Document 4 is shown in FIG. In this example, an address conversion unit 402 that converts a logical address of a pixel constituting an image into a physical address indicating a cell position on the memory is provided. Further, the address conversion unit 402 generates a physical address so that pixel data is efficiently arranged on the memory. As a result, Patent Document 4 enables efficient use of the memory.
Japanese Patent Laid-Open No. 5-120121 Japanese Patent Laid-Open No. 9-259035 Japanese Patent Laid-Open No. 10-112179 JP-A-5-257458

  However, in the techniques disclosed in Patent Documents 1 to 4, image data is divided and stored in cells connected to different word lines. When a DRAM (Dynamic Random Access Memory) is used as a storage device, the memory selects a cell in the row direction depending on which word line is selected, and selects a cell in the column direction depending on which sense amplifier is selected. A selection is made. Therefore, in these conventional techniques, it is necessary to drive a plurality of word lines in the image data writing or reading operation. For this reason, the techniques disclosed in Patent Documents 1 to 4 have a problem that power consumption increases according to the number of word lines to be driven. In a semiconductor device mounted on a portable device or the like, reduction of power consumption is strongly demanded, and increase of power consumption becomes a big problem.

  One embodiment of the present invention is a semiconductor memory device that stores data having a multidimensional space based on coordinate information of the data, the cell array in which the memory cells that store the data are arranged in a grid, and the row direction A word line selector that selects and drives one of a plurality of word lines that activates the memory cells arranged in the memory, and writes and reads data to and from the memory cells arranged in the column direction A plurality of write amplifiers and sense amplifiers; an amplifier selector that selects one of the plurality of write amplifiers and sense amplifiers and inputs / outputs the data to / from the selected write amplifiers and sense amplifiers; and the data One row address to be given to the word line selector is generated based on the coordinate information, and the coordinate information of the data is made one-dimensional. An address conversion circuit for generating a column address to be given to the amplifier selector, a semiconductor memory device having a.

  Another aspect of the present invention is a semiconductor memory device having a cell array in which memory cells for storing data are arranged in a grid, and storing data having a multidimensional space in the cell array based on the coordinate information of the data A data storage method according to claim 1, wherein a row address where the data is stored is determined based on one coordinate information of the coordinate information of the data, and the data is stored based on the one-dimensional coordinate information. It is a data storage method in a semiconductor memory device for determining an address.

  According to the semiconductor memory device and the data storage method of the present invention, all the data in the space is stored in a plurality of cells designated by one word line by making the data in the multidimensional space one-dimensional. be able to. Thus, it is possible to arbitrarily access data in one space by driving one word line. That is, it is not necessary to drive a plurality of word lines when accessing data in one space. Therefore, according to the semiconductor memory device and the data storage method of the present invention, it is possible to reduce the power consumption necessary for driving the word line during data access.

  According to the semiconductor memory device and the data storage method of the present invention, it is possible to reduce power consumption during data access.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, an example in which image information is handled as data having a multidimensional space will be described. The data to be handled has coordinate information indicating the position in the space. For example, in the case of image data having a two-dimensional space, each data has an X address and a Y address. FIG. 1 is a block diagram of a semiconductor memory device 1 according to the embodiment. As shown in FIG. 1, the semiconductor memory device 1 includes a clock generation circuit 10, a command decoder 11, a logic circuit 12, a mode register 13, an address control circuit 14, an address conversion circuit 15, a word line selector 16, a cell array 17, a write amplifier. A sense amplifier 18, an amplifier selector 19, a latch circuit 20, and an input / output buffer 21 are included.

  The clock generation circuit 10 generates a clock signal used inside the semiconductor memory device 1 based on the clock signal CLK, the inverted clock signal CLKb, and the clock enable signal CKE. The command decoder 11 decodes commands specified by signals such as a chip select signal CS, a RAS (Row Address Strobe) signal, a CAS (Column Address Strobe) signal, and a write enable signal WE.

  The logic circuit 12 generates control signals to the address control circuit 14, the word line selector 16, the amplifier selector 19, and the latch circuit 20 according to the command decoded by the command decoder 11 and the operation mode specified by the mode register. . The mode register 13 designates an operation mode such as a burst mode or a normal operation mode based on an X address and a Y address input from the outside.

  The address control circuit 14 has an address buffer, a refresh counter, and a burst counter. The address buffer temporarily holds an X address and a Y address input from the outside. The refresh counter is used in the DRAM, and sets the refresh cycle of the DRAM and generates a refresh address. The burst counter generates an address designating a storage cell on the cell array 17 in a burst operation for the memory. The address control circuit 14 outputs the addresses generated by the address buffer, the refresh counter, and the burst counter as the word line address WL and the bit line address BL. The word line address WL specifies the position in the row direction of the memory cells arranged in a lattice pattern on the cell array 17. The bit line address BL designates the position in the column direction of the memory cells arranged in a lattice pattern on the cell array 17. The address control circuit 14 selects and outputs one of the addresses output from the address buffer, the refresh counter, and the burst counter based on the control signal output from the logic circuit 12. Note that the word line address WL and the bit line address BL indicate one address using a plurality of bits.

  When the input data has a space designated by the X address and the Y address, the address conversion circuit 15 generates one cell array row address CAX to be given to the word line selector 16 based on the coordinate information of the data, The coordinate information is made one-dimensional and a cell array column address CAY to be supplied to the amplifier selector 19 is generated. In the present embodiment, the memory cell of the cell array 17 is activated using the cell array row address CAX and the cell array column address CAY instead of the word line address and the bit line address. For example, when the address control circuit 14 outputs the word line address WL based on the X address and outputs the bit line address BL based on the Y address, the address conversion circuit 15 may select any of the word line address WL and the bit line address BL. One cell array row address CAX is generated using the bits, and a cell array column address CAY is generated by combining the bits of the word line address WL and the bit line address BL that are not used for the cell array row address CAX. Details of the address conversion circuit 15 will be described later.

  The cell array 17 has a plurality of memory cells arranged in a lattice pattern. In the present embodiment, the cell array 17 is formed so that the number of memory cells arranged in one row direction is a number that can sufficiently store all the pixels in the image space. The word line selector 16 selects any one of the plurality of word lines based on the cell array row address CAX. The word line is connected to a plurality of memory cells arranged in the same row among the memory cells arranged in a grid pattern. Therefore, when the word line selector 16 selects any one word line, the memory cell connected to the selected word line is activated. The write amplifier / sense amplifier 18 has a combination of a plurality of write amplifiers and sense amplifiers. A plurality of pairs of write amplifiers and sense amplifiers are connected to the bit line pairs, respectively. The bit line pair is a pair of two bit lines, and this bit line pair is treated as one column. A plurality of memory cells arranged in the same column among the memory cells arranged in a lattice shape are connected to the bit line pair. The amplifier selector 19 selects one of a plurality of sets of write amplifiers and sense amplifiers based on the cell array column address CAY. The semiconductor memory device 1 has a plurality of combinations of the cell array 17, the word line selector 16, and the write amplifier / sense amplifier 18. A plurality of these sets are called banks. In FIG. 1, BANK 0 to 3 are shown. In the following, the operation for BANK0 is described unless otherwise specified.

  The latch circuit 20 has a plurality of latch circuits. The latch circuit 20 takes in data input from the outside in synchronization with the clock signal output from the clock generation circuit 10 and outputs the data to the write amplifier selected by the amplifier selector 19. Also. The latch circuit 20 takes in the data output from the sense amplifier selected by the amplifier selector 19 in synchronization with the clock signal output from the clock generation circuit 10, and outputs the data to the input / output buffer. The input / output buffer 21 outputs data DQ input from the outside to the latch circuit 20 and outputs data DQ output from the latch circuit 20 to the outside. Semiconductor memory device 1 performs data input / output in parallel using a plurality of data input / output terminals.

  Here, details of the address conversion circuit 15 will be described. A block diagram of the address conversion circuit 15 in the present embodiment is shown in FIG. As shown in FIG. 2, the address conversion circuit 15 includes image map circuits 15a to 15d and an image map selector 15e. In the image map circuits 15a to 15d, an address conversion method is defined in advance for each size of an image to be handled. For example, the image map circuit 15a handles an image having a size of 80 pixels in the vertical direction (Y-axis direction) and 80 pixels in the horizontal direction (X-axis direction). The image map circuits 15 a to 15 d generate one cell array row address CAX and a plurality of cell array column addresses CAY based on the word line address WL and the bit line address BL output from the address control circuit 14. The image map circuits 15a to 15d may convert an address conversion rule using a conversion table, or may perform an address conversion by calculation. Bus wiring on the input side of the image map circuit according to the size of an image to be handled The combination of the connection of the bus wiring on the output side may be changed. The address conversion will be described later.

  The image map selector 15e enables one of the image map circuits 15a to 15d based on an image size selection signal input from the outside, and disables the remaining image map circuits. That is, the address conversion circuit 15 performs address conversion based on the rules set in the image map circuit selected by the image size selection signal.

Next, address conversion will be described in detail. An example of the address conversion rule is shown in FIGS. In the following example, in order to generalize the conversion rule, the word line address WL output from the cell array row address CAX and the address control circuit 14 is configured with a bit width of h bits, and the cell array column address CAY and the address control circuit 14 are Assume that the output bit line address BL is configured with a bit width of v bits, the X-axis direction address X of the handled image is configured with m bits, and the Y-axis direction address of the processed image is configured with n bits. In other words, the number of word lines in the cell array 17 is 2 ^h book number of bit line pairs is 2 ^v present.

  The example shown in FIG. 3 is an example of a conversion rule from the word line address WL and the bit line address BL output from the address control circuit 14 to the cell array row address CAX. In this example, the X address of the image is associated with the h-bit word line address WL. For example, the least significant bit X1 of the X address is associated with the least significant bit WL1 of the word line address WL. The X address is defined using m bits of the word line address WL. Here, the bits from the (m + 1) th bit to the hth bit (most significant bit) of the word line address have a common value as the coordinate address of the pixel in the image space to be handled.

  The address conversion circuit 15 generates a cell array row address CAX based on the address information output from the address control circuit 14. In this example, the address conversion circuit 15 is a bit line address that is not used as a value representing the image space in the bit line address BL (for example, bits from the (n + 1) th bit to the vth bit (most significant bit) of the Y address. Is used to generate a cell array row address CAX. For example, the most significant bit from the (n + 1) th bit of the Y address is made to correspond in order from the least significant bit of the cell array row address CAX. Further, the bit value of the cell array row address CAX without the corresponding Y address bit value can be arbitrarily set.

  The example shown in FIG. 4 is an example of a conversion rule from the word line address WL and the bit line address BL output from the address control circuit 14 to the cell array column address CAY. In this example, the v-bit bit line address BL is associated with the Y address of the image. For example, the least significant bit Y1 of the Y address is associated with the least significant bit BL1 of the bit line address BL. The Y address is defined using n bits of the bit line address BL. Here, bits from the (n + 1) th bit to the vth bit (most significant bit) of the bit line address have a common value as the coordinate address of the pixel in the image space to be handled.

  The address conversion circuit 15 generates the cell array column address CAY based on the address information output from the address control circuit. In this example, the address conversion circuit 15 uses a word line address and a bit line address (for example, from the least significant bit to the m-th bit of the X address) used as values representing the image space among the word line address WL and the bit line address BL. The cell array column address CAY is generated using the bit value of n and the bit value of the nth bit from the least significant bit of the Y address. For example, the value of the mth bit from the least significant bit of the X address is used as the value of the mth bit from the least significant bit of the cell array column address CAY, and the value of the Y address as the value of the most significant bit from the m + 1 bit of the cell array row address CAX. The value of the nth bit from the least significant bit is used.

  That is, the address conversion circuit 15 generates one cell array row address CAX using the bits of the X address and the Y address having a common value as the spatial coordinates of the image to be handled. Further, the address conversion circuit 15 generates a cell array column address CAY using bits of the X address and the Y address having different values as the spatial coordinates of the image to be handled. As a result, an image having a predetermined area can be stored in a memory cell specified by one cell array row address CAX. The cell array row address CAX may be generated using only one of the X address and the Y address, or may be generated by combining the X address and the Y address. The correspondence relationship between the bit of the cell array column address CAY and the bit of the X address and the Y address can be arbitrarily set according to the situation.

  Next, FIG. 5 shows a data storage address when an image having 8 pixels in the X-axis direction and 16 pixels in the Y-axis direction is stored in the cell array 17 based on the conversion rule. An image in which the number of pixels in the X-axis direction is 8 pixels and the number of pixels in the Y-axis direction is 16 pixels may represent the addresses of all pixels in the image space using a 3-bit X address and a 4-bit Y address. it can. In this example, the upper 3 bits of the Y address are used as the cell array row address CAX, the lower 3 bits of the X address are used as the lower 3 bits of the cell array column address CAY, and the Y address is added to the upper 4 bits of the cell array column address CAY. The lower 4 bits are used.

  As shown in FIG. 5, an image whose value represented by the upper 3 bits of the Y address is “0” is stored in a memory cell connected to one word line whose address value is designated by “0”. The On the other hand, FIG. 6 shows data storage positions when images of the same size are stored in the cell array 17 when the address conversion circuit 15 is not used. In this case, as shown in FIG. 6, the image is stored using 8 word lines and 16 bit line pairs.

  Subsequently, a data read operation in the semiconductor memory device according to the present embodiment will be described. Here, as an example, each of the operations when reading out five types of images having the same 8 pixel × 8 pixel image space will be described. Examples of images to be read are shown in FIGS. 7, 9, 11, 13, and 15, and timing charts for reading these images are shown in FIGS. 8, 10, 12, 14, and 16. In the following description (including the description of the following embodiments), as an example of the operation, the cell array row address CAX is controlled by using a part of the Y address, and the cell array column address CAY is used in the cell array row address CAX. It is assumed that the remaining X address and Y address are not used. As described above, when the cell array row address CAX and the cell array column address CAY are generated by the combination of the X address and the Y address, respectively, the X address and the Y address corresponding to the cell array row address CAX and the cell array column address CAY can be input in a timely manner. And can be changed as appropriate according to the specifications.

  In a general DRAM memory, a word line address of a memory cell is designated by a RAS signal. Subsequently, after the time defined by tRCD has elapsed from the RAS signal, the CAS signal is input to specify the bit line address. After the CAS signal is input, the data to be read is output when the time defined by the latency elapses. Further, when reading data of a memory cell designated by a word line different from the designated word line, precharge is performed after all read data from the designated word line address is output. Then, a word line address and a bit line address are newly designated by the RAS signal and the CAS signal after elapse of the time specified by tRP. Note that tRCD, latency, and tRP are times defined by the semiconductor memory device. The semiconductor memory device operates on the basis of the clock signal CLK, and a period of one cycle of the clock signal CLK is hereinafter referred to as tCK.

  First, the image shown in FIG. 7 is an image in which the letter A is written using 14 pixels. FIG. 8 shows a timing chart when 14 pieces of data representing the character A are read. As shown in FIG. 8, the semiconductor memory device 1 receives the operation start command ACT when the RAS signal is input at the first clock CL1. At this time, the Y address used as the cell array row address CAX is also input at the same time. Subsequently, the semiconductor memory device 1 receives the CAS signal at the third clock CL3 and receives the read command RED. At this time, an X address used as a part of the cell array column address CAY is input. Then, the data Q0 is output after the time specified by the latency elapses. Data Q0 is data located at the coordinates of Y = 1 and X = 3 specified by the Y address input in synchronization with the first clock CL1 and the X address input in synchronization with the third clock CL3. It is.

  In the semiconductor memory device 1, the X address and the Y address are continuously input in synchronization with the clock after the third clock CL3, and 14 selected by the cell array column address CAY generated using the input address. Read each data. In this example, 19 clocks are required from the input of the RAS signal to the semiconductor memory device 1 until the reading of all data is completed. In the semiconductor memory device 1, pixel information in the image space is stored in a memory cell activated by one word line. Therefore, the RAS signal and CAS signal are not input until all data is read out. Further, after all data is read, a precharge operation is performed, and preparations for reading image data in different image spaces are made.

  The image shown in FIG. 9 is a straight image drawn by eight pixels having coordinates in a column designated by Y address “2” in the image space. FIG. 10 shows a timing chart in the case of reading out eight pieces of data indicating this straight line image. As shown in FIG. 10, the semiconductor memory device 1 receives the operation start command ACT when the RAS signal is input at the first clock CL1. At this time, the Y address used as the cell array row address CAX is also input at the same time. Subsequently, the semiconductor memory device 1 receives the CAS signal at the third clock CL3 and receives the read command RED. At this time, an X address used as a part of the cell array column address CAY is input. Then, the data Q0 is output after the time specified by the latency elapses. Data Q0 is data located at the coordinates of Y = 2 and X = 0 specified by the Y address input in synchronization with the first clock CL1 and the X address input in synchronization with the third clock CL3. It is.

  In the semiconductor memory device 1, the X address and the Y address are continuously input in synchronization with the clock after the third clock CL3, and eight data are read out. In this example, 13 clocks are required from the input of the RAS signal to the semiconductor memory device 1 until the reading of all data is completed. In the semiconductor memory device 1, pixel information in the image space is stored in a memory cell activated by one word line. Therefore, the RAS signal and CAS signal are not input until all data is read out. Further, after all data is read, a precharge operation is performed, and preparations for reading image data in different image spaces are made.

  The image shown in FIG. 11 has eight pixels drawn obliquely in the image space. FIG. 12 shows a timing chart in the case of reading out eight pieces of data indicating a straight line image drawn obliquely. As shown in FIG. 12, the semiconductor memory device 1 receives the operation start command ACT when the RAS signal is input at the first clock CL1. At this time, the Y address used as the cell array row address CAX is also input at the same time. Subsequently, the semiconductor memory device 1 receives the CAS signal at the third clock CL3 and receives the read command RED. At this time, an X address used as a part of the cell array column address CAY is input. Then, the data Q0 is output after the time specified by the latency elapses. Data Q0 is data located at the coordinates of Y = 0 and X = 0 specified by the Y address input in synchronization with the first clock CL1 and the X address input in synchronization with the third clock CL3. It is.

  In the semiconductor memory device 1, the X address and the Y address are continuously input in synchronization with the clock after the third clock CL3, and eight data are read out. In this example, 13 clocks are required from the input of the RAS signal to the semiconductor memory device 1 until the reading of all data is completed. In the semiconductor memory device 1, pixel information in the image space is stored in a memory cell activated by one word line. Therefore, the RAS signal and CAS signal are not input until all data is read out. Further, after all data is read, a precharge operation is performed, and preparations for reading image data in different image spaces are made.

  In the image shown in FIG. 13, a straight line having eight pixels in the Y-axis direction is drawn. The straight line has X addresses designated by X = 0, 3, 5, and 7, respectively. FIG. 14 shows a timing chart in the case of reading 32 pieces of data indicating the plurality of straight lines. In this example, it is assumed that the semiconductor memory device 1 performs a burst operation. In the burst operation, the Y address input when the RAS signal is input is used as a head address, and the subsequent Y address is generated by an internal burst counter. In addition, the semiconductor memory device 1 in this example realizes a data output speed that is twice that of a case where the inverted clock signal operates based on a single-phase clock signal. Such a data output method is referred to as a double data rate.

  As shown in FIG. 14, the semiconductor memory device 1 receives the operation start command ACT when the RAS signal is input at the first clock CL1. At this time, the Y address used as the cell array row address CAX is also input at the same time. Subsequently, the semiconductor memory device 1 receives the CAS signal at the third clock CL3 and receives the read command RED. At this time, an X address used as a part of the cell array column address CAY is input. Then, the data Q0 is output after the time specified by the latency elapses. Data Q0 is data located at the coordinates of Y = 0 and X = 0 specified by the Y address input in synchronization with the first clock CL1 and the X address input in synchronization with the third clock CL3. It is.

  In the semiconductor memory device 1, eight data are read continuously without inputting individual X address and Y address by burst operation. When a plurality of burst operations are continuously performed, a read start address is appropriately input by a CAS signal. In this example, 21 clocks are required from the input of the RAS signal to the semiconductor memory device 1 until the reading of all data is completed. In the semiconductor memory device 1, pixel information in the image space is stored in a memory cell activated by one word line. Therefore, the RAS signal is not input until all data is read out. Further, after all data is read, a precharge operation is performed, and preparations for reading image data in different image spaces are made.

  The images shown in FIG. 15 are images each having an area of 8 pixels in the Y-axis direction and 6 pixels in the X-axis direction. FIG. 16 shows a timing chart in the case of reading 48 data in this area. Also in this case, it is possible to read out pixels by a burst operation as in the example shown in FIG. Also in this example, data is output at a double data rate.

  As shown in FIG. 16, the semiconductor memory device 1 receives the RAS signal at the first clock CL1 and receives the operation start command ACT. At this time, the Y address used as the cell array row address CAX is also input at the same time. Subsequently, the semiconductor memory device 1 receives the CAS signal at the third clock CL3 and receives the read command RED. At this time, an X address used as a part of the cell array column address CAY is input. Then, the data Q0 is output after the time specified by the latency elapses. Data Q0 is data located at the coordinates of Y = 0 and X = 0 specified by the Y address input in synchronization with the first clock CL1 and the X address input in synchronization with the third clock CL3. It is.

  In the semiconductor memory device 1, eight data are read continuously without inputting individual X address and Y address by burst operation. When a plurality of burst operations are continuously performed, a read start address is appropriately input by a CAS signal. In this example, 29 clocks are required from the input of the RAS signal to the semiconductor memory device 1 until the reading of all data is completed. In the semiconductor memory device 1, pixel information in the image space is stored in a memory cell activated by one word line. Therefore, the RAS signal is not input until all data is read out. Further, after all data is read, a precharge operation is performed, and preparations for reading image data in different image spaces are made.

  From the above description, in the semiconductor memory device 1 according to the present embodiment, the address conversion circuit 15 generates a cell array column address in which the address of image data having a two-dimensional space is made one-dimensional. The address conversion circuit 15 generates one cell array row address for one image space. Thereby, data of one image space can be stored in the memory cell connected to one word line. That is, the semiconductor memory device 1 can access image data having a two-dimensional space stored in the cell array 17 only by activating one word line. As a result, the semiconductor memory device 1 can reduce the number of word lines to be activated, so that it is possible to reduce power consumption required for data access.

  Further, when an X address and a Y address in the image space correspond to a word line address and a bit line address, respectively, and access is made to data of different X addresses, a precharge operation is required for each access to different X addresses. In a general DRAM, data having a two-dimensional space is stored using a plurality of word lines. Therefore, when accessing data having different X addresses, a plurality of precharge operations are required. On the other hand, the semiconductor memory device 1 according to the present embodiment can arbitrarily access even data of different X addresses by performing only one precharge operation. For this reason, the semiconductor memory device 1 can also reduce power consumption for the precharge operation.

  Furthermore, when accessing data having different X addresses in a general DRAM, it is necessary to perform RAS signal input, CAS signal input, and precharge operations a plurality of times. On the other hand, the semiconductor memory device 1 according to the present embodiment can arbitrarily access data of different X addresses only by performing RAS signal input, CAS signal input, and precharge operation only once. It is. That is, the semiconductor memory device 1 can reduce the time required for the input of the RAS signal, the input of the CAS signal, and the precharge operation independent of the number of data to be accessed as compared with a general DRAM. FIG. 17 shows a comparative example of the operation time between the general DRAM and the semiconductor memory device 1 according to the first embodiment.

  In FIG. 17, the time defined by tRCD is a, the time defined by latency is b, the period tCK of the clock signal is c, and the time defined by tRP is d. For example, when accessing data having an image size of (2 × 2), the processing time is 2 (a + b + 2c + d) in a general DRAM. On the other hand, in the semiconductor memory device 1, the processing time is a + b + 4c + d. Here, since the term related to c depending on the number of data read is the same between a general DRAM and the semiconductor memory device 1, the time except for the time related to the term related to c is compared. The processing time ratio between the general DRAM and the semiconductor memory device 1 is such that when the processing time of the general DRAM is 100%, the semiconductor memory device 1 can complete the operation in the processing time of 50%. . The difference in the processing time ratio further increases as the number of pixels in the X direction of the read image increases. That is, the semiconductor memory device 1 according to the present embodiment can perform data processing at a higher speed than a general DRAM. In addition, the effect of speeding up the semiconductor memory device 1 increases as the image size handled increases.

  The semiconductor memory device 1 according to the present embodiment includes a plurality of image map circuits 15a to 15d corresponding to the image size of the image handled by the address conversion circuit 15. The image map circuits 15a to 15d can perform address conversion in accordance with a preset conversion rule without performing any arithmetic processing. That is, the semiconductor memory device 1 does not increase power consumption due to the arithmetic processing even if the address conversion is executed. Thereby, the semiconductor memory device 1 can suppress an increase in power consumption due to address conversion.

  In the semiconductor memory device 1 according to the present embodiment, since the address conversion circuit converts the address based on a predetermined conversion rule, the correspondence between the address before conversion and the address after conversion is related to the data address. It will be decided. That is, the data stored in the semiconductor memory device 1 is in a state of holding the coordinate information designated by the external device. As a result, the external device can access the data stored in the semiconductor memory device 1 without particularly converting the coordinate information of the data.

Embodiment 2
In the first embodiment, an example in which image data having a two-dimensional space is handled has been described. In the second embodiment, an example in which image data having a three-dimensional space is handled will be described. Here, X-axis (X address), Y-axis (Y address), and Z-axis (Z address) are used as coordinate information indicating a three-dimensional space. In the second embodiment, the address conversion circuit 15 generates a cell array column address CAY that combines the X address, the Y address, and the Z address. Note that the Z address is handled as a bank address BA that designates, for example, a bank of the cell array in the semiconductor memory device 1. Specifically, when a Z address is input to the semiconductor memory device 1, the address control circuit 14 outputs a bank address BA corresponding to the Z address.

  An example of address conversion rules in the second embodiment is shown in FIGS. The example shown in FIG. 18 is an example of a conversion rule from the word line address WL output by the address control circuit 14 to the cell array row address CAX. In this example, the X address of the image is associated with the h-bit word line address WL. For example, the least significant bit X1 of the X address is associated with the least significant bit WL1 of the word line address WL. The X address is defined using m bits of the word line address WL. Here, the bits from the (m + 1) th bit to the hth bit (most significant bit) of the word line address have a common value as the coordinate address of the pixel in the image space to be handled.

  The address conversion circuit 15 generates the cell array row address CAX based on the address information output from the address control circuit 14. In this example, the address conversion circuit 15 is a word line address (for example, bits from the (m + 1) th bit to the hth bit (most significant bit) of the X address that are not used as values representing the image space in the word line address WL. Is used to generate a cell array row address CAX. For example, the most significant bit from the (m + 1) th bit of the X address is made to correspond in order from the least significant bit of the cell array row address CAX. Further, the bit value of the cell array row address CAX without the corresponding X address bit value can be arbitrarily set.

  The example shown in FIG. 19 is an example of a conversion rule from the word line address WL, the bit line address BL, and the bank address BA output from the address control circuit 14 to the cell array column address CAY. In this example, the v-bit bit line address BL is associated with the Y address of the image. For example, the least significant bit Y1 of the Y address is associated with the least significant bit BL1 of the bit line address BL. The Y address is defined using n bits of the bit line address BL. Here, the bits from the (n + 1) th bit to the vth bit (most significant bit) of the bit line address have a common value as the coordinate address of the image in the image space to be handled.

  The address conversion circuit 15 generates a cell array column address CAY based on the address information output from the address control circuit 14. In this example, the address conversion circuit 15 uses a word line address, a bit line address, and a bank address BA (for example, an X address) used as a value representing an image space among the word line address WL, the bit line address BL, and the bank address BA. The cell array column address CAY using the bit value from the least significant bit to the mth bit, the bit value of the nth bit from the least significant bit of the Y address, and the bit value of the oth bit from the least significant bit of the bank address BA) Is generated. For example, the value of the oth bit from the least significant bit of the Z address is used as the value of the oth bit from the least significant bit of the cell array column address CAY, and the value of the Y address is used as the value of the o + 1th bit to the o + nth bit of the cell array column address CAY. The value of the nth bit from the least significant bit is used, and the value of the mth bit from the least significant bit of the X address is used as the value of the most significant bit from the o + n + 1 bit of the cell array column address CAY.

  That is, the address conversion circuit 15 generates one cell array row address CAX using the bits of the X address, Y address, and Z address having common values as the spatial coordinates of the image to be handled. Further, the address conversion circuit 15 generates a cell array column address CAY using bits of X address, Y address, and Z address having different values as the spatial coordinates of the image to be handled. As a result, an image having a three-dimensional space can be stored in a memory cell specified by one cell array row address CAX. The cell array row address CAX may be generated using only one of the X address, Y address, and Z address, or may be generated by combining the X address, Y address, and Z address. The correspondence relationship between the bit of the cell array column address CAY and the bit of the X address, the Y address, and the Z address can be arbitrarily set according to the situation.

  Subsequently, a data read operation in the semiconductor memory device according to the present embodiment will be described. First, FIG. 20 shows data storage positions on the cell array in this embodiment. As shown in FIG. 20, in this embodiment, one three-dimensional image data (for example, image data having an image space of 4 pixels × 4 pixels × 4 pixels) is stored in a memory cell connected to one word line. Is done. In the following description, the operation when reading out the image data will be described as an example. An example of an image to be read is shown in FIG. 21, and a timing chart for reading an image is shown in FIG.

  Data to be read out is five pixels indicated by Q0 to Q4 in FIG. Then, as shown in FIG. 22, the semiconductor memory device 1 receives the RAS signal and receives the operation start command ACT at the first clock CL1. At this time, an X address used as the cell array row address CAX is also input at the same time. Subsequently, the semiconductor memory device 1 receives the CAS signal at the third clock CL3 and receives the read command RED. At this time, a Y address and a Z address used as part of the cell array column address CAY are input. Then, the data Q0 is output after the time specified by the latency elapses. The data Q0 has X = 0, Y = 0, Z = designated by the X address inputted in synchronization with the first clock CL1 and the Y address and Z address inputted in synchronization with the third clock CL3. Data located at the coordinate of 0.

  In the semiconductor memory device 1, the X address and the Y address are continuously input in synchronization with the clock after the third clock CL3, and five pieces of data are read out. In this example, 10 clocks are required from the input of the RAS signal to the semiconductor memory device 1 until the reading of all data is completed. In the semiconductor memory device 1, pixel information in the image space is stored in a memory cell activated by one word line. Therefore, the RAS signal and CAS signal are not input until all data is read out. Further, after all data is read, a precharge operation is performed, and preparations for reading image data in different image spaces are made.

  From the above description, the semiconductor memory device 1 can handle not only two-dimensional data but also three-dimensional data by making the address conversion rule performed by the address conversion circuit 15 correspond to the three-dimensional.

Embodiment 3
In the first and second embodiments, there is one bank to be accessed. However, when the semiconductor memory device 1 has a plurality of banks, it is possible to access a plurality of banks in parallel by bank interleave control. is there. Bank interleave control is control performed in a semiconductor memory device having a plurality of banks. In bank interleave control, the word lines of each bank can be activated individually. Data can be read in parallel from the memory cells connected to the activated word line in each bank. By using this bank interleave control, for example, when the value of one pixel is represented by 4 bits, the value of each bit can be divided and stored in a plurality of banks.

Embodiment 4
In the fourth embodiment, the Z address is used not as a spatial coordinate but as a terminal address indicating the number of a data input / output terminal (hereinafter referred to as I / O terminal). In a semiconductor memory device, the number of I / O terminals is generally determined in advance and cannot be changed after manufacturing. In such a case, when data having a bit width larger than the actual number of I / O terminals is handled, it is necessary to use a different semiconductor memory device or to redesign the semiconductor memory device.

  Therefore, in the fourth embodiment, the Z address is associated with the I / O terminal number. For example, in a semiconductor memory device having 16 I / O terminals, when data having a bit width of 64 bits is handled, 0th to 15th I / O terminals are assigned to Z address = 0, and Z address = 1. 16th to 31st I / O terminals are assigned to Z address = 2, 32nd to 47th I / O terminals are assigned to Z address = 2, and 48th to 63rd I / O terminals are assigned to Z address = 3. Further, the data having a bit width of 64 bits is divided into data having a bit width of 16 bits. Then, a Z address is added as a data address in accordance with the order of input / output data.

  FIG. 23 shows a timing chart of the data output operation of the semiconductor memory device 1 when the Z address is used in this way. In this example, it is assumed that the Z address is generated internally based on the burst operation. As shown in FIG. 23, when a RAS signal and a CAS signal are input, data Q0 is output. Data Q0 corresponds to data output via the 0th to 15th I / O terminals. Subsequently, data Q1 to Q3 are output. Data Q1 corresponds to data output via the 16th to 31st I / O terminals, data Q2 corresponds to data output via the 32nd to 47th I / O terminals, Data Q3 corresponds to data output through the 48th to 63rd I / O terminals.

  From the above description, according to the semiconductor memory device 1 according to the present embodiment, the address conversion circuit generates the cell array column address by combining the X address, the Y address, and the Z address. Therefore, even when the Z address is used as additional information corresponding to the number of an I / O terminal through which data is input / output, data can be stored in a memory cell connected to one word line. It is. That is, the semiconductor memory device 1 can handle data of various bit widths regardless of the number of I / O terminals by using the Z address as additional information. In addition, since the Z address is generated inside the semiconductor memory device 1, even in such a case, the external device can manage the data only with the X address and the Y address.

Embodiment 5
In the fifth embodiment, when the value of one pixel is represented using a plurality of bits, the Z address is used as a data address associated with the position of the bit representing the value of the pixel. For example, when the output data is expressed by 4 bits, the least significant bit of the output data is assigned to Z address = 0, the second lower bit of the output data is assigned to Z address = 1, and the output data is assigned to Z address = 2. The third lower bit is assigned, and the most significant bit of the output data is assigned to Z address = 3.

  In the fifth embodiment, the Z address is an address generated inside the semiconductor memory device 1 based on the burst operation. The address conversion circuit 15 generates a cell array column address CAY by combining the X address, the Y address, and the Z address.

  FIG. 24 shows a timing chart showing the operation of the semiconductor memory device 1 according to the fifth embodiment. As shown in FIG. 24, in the fifth embodiment, when an address of data to be read is designated by an X address and a Y address, four data Q0 to Q3 are output subsequently. At this time, the data Q0 to Q3 are continuously output by the burst operation. Data Q0 to Q3 correspond to each bit of 4-bit data.

  From the above description, the semiconductor memory device 1 according to the fifth embodiment associates each bit of data expressed by a plurality of bits with a Z address, thereby making the data constituted by the plurality of bits one word line. Store in the connected storage cell. At this time, since the Z address is generated inside the semiconductor memory device 1, the external device can manage the data only by the X address and the Y address.

  In the above embodiment, the semiconductor memory device 1 outputs data by serial operation for sequentially outputting data. However, the semiconductor memory device 1 can also output data by a parallel operation of outputting data in parallel using a plurality of I / O terminals. FIG. 25 shows a timing chart showing the operation of the semiconductor memory device 1 performing the parallel operation. As shown in FIG. 25, in the parallel operation, after the CAS signal is input, four data are simultaneously output in synchronization with one clock.

Embodiment 6
In the sixth embodiment, when one image space is divided into a plurality of small spaces, a Z address is used as a small space address representing the small space. In the semiconductor memory device 1, the cell array row address CAX and the cell array column address CAY are composed of a plurality of bits. Therefore, the number of word line and bit line pairs is a power of 2. On the other hand, the number of pixels in the X-axis direction and the number of pixels in the Y-axis direction in one image space are not necessarily represented by powers of 2. For this reason, the utilization efficiency of the memory cells of the cell array 17 may deteriorate.

  Therefore, in the sixth embodiment, one image space is treated as a set of small spaces (for example, small images) in which the number of pixels is defined by a power of 2. For example, in the case of an image of 1024 pixels in the X-axis direction and 768 pixels in the Y-axis direction, the image is divided into small images having 1024 pixels in the X-axis direction and 256 pixels in the Y-axis direction. Treat as a set of two small images. A Z address is assigned to each small image. FIG. 26 shows an image when such division is performed.

  In addition, a timing chart showing the operation of the semiconductor memory device 1 in this case is shown in FIG. As shown in FIG. 27, by specifying a pixel to be read using an X address, a Y address, and a Z address, data can be accessed in this embodiment as in the second embodiment. It is also possible for the address conversion circuit 15 to divide the image and generate a Z address assigned to the divided small space.

  From the above description, even if the semiconductor memory device 1 according to the sixth embodiment is an image whose image size is not defined by a power of 2, this image is changed to a small image whose size is represented by a power of 2. To divide. Thereby, the utilization efficiency of the memory cells arranged in the cell array 17 can be increased. Further, when the image size conversion in the sixth embodiment is performed by the address conversion circuit 15, it is not necessary to perform any conversion in the external device.

Embodiment 7
Although the semiconductor memory device 1 of the present invention has the effect of reducing power consumption as described above, data read and write operations can be performed by combining with a data processing device such as a CPU that performs data read and write by a full page operation. This is particularly effective for speeding up. The full page operation is to access a plurality of memory cells connected to one word line after inputting a set of addresses (for example, a combination of X address and Y address). The data transmission / reception method described in the seventh embodiment further enhances the speed-up effect by changing the data transmission / reception method of the CPU according to the data storage method of the semiconductor memory device 1 of the present invention.

  FIG. 28 shows an example of an image handled in the present embodiment. As shown in FIG. 28, this image has pixel data of data Q0 to QV in the upper half of the 8 × 8 pixel image. When handling such an image, in an operation performed in a general SDRAM, an address of X = 0 and Y = 0 is designated and a memory cell connected to a word line designated by X = 0 is designated. The data Q0 to Q3 to be stored is transmitted or received, and then the address X = 1, Y = 0 is designated and stored in the memory cell connected to the word line designated by X = 1. Q7 data is transmitted and received. Thereafter, this operation is sequentially repeated up to an address of X = 7.

  On the other hand, in the full page operation shown in the present embodiment, for example, by adjusting the address conversion method, after specifying an address of X = 0 and Y = 0, Q0 is not performed without specifying the address again. Data of ~ QV can be read or written continuously. FIG. 29 shows a timing chart of the reading operation in this embodiment. As shown in FIG. 29, in the data transmission / reception method shown in the seventh embodiment, the 0th Y address is designated together with the operation start command ACT by the clock CL1. Subsequently, the 0th X address is designated together with the read command RED at the clock CL3. Then, in response to the input of the read command RED of the clock CL3, the data Q0 to QV are continuously read with the clocks CL6 to CL20. The target image is reproduced by appropriately arranging the read data Q0 to QV in the CPU.

  On the other hand, FIG. 30 shows a timing chart of the write operation in this embodiment. As shown in FIG. 30, in the data transmission / reception method shown in the seventh embodiment, the 0th Y address is designated together with the operation start command ACT by the clock CL1. Subsequently, the zeroth X address is designated together with the read command WRT at the clock CL3, and the data Q0 serving as the head data is input. Then, data Q0 to QV are continuously input with clocks CL3 to CL17. As described above, in the present embodiment, by arranging write data in a continuous format on the CPU side, the target image data is written for each X address without re-inputting the address.

  As another form of the semiconductor memory device 1, an operation when a pseudo SRAM (RAM having an SRAM interface and using a DRAM cell) is used will be described. In the pseudo SRAM, the specification specifies that the X address and the Y address are transmitted together with a read or write command. Therefore, the data read operation and write operation are the operations of the timing charts shown in FIGS. FIG. 31 shows a timing chart of the read operation in the pseudo SRAM. As shown in FIG. 31, in the pseudo SRAM, the X address and the Y address are input together with the read command RED, and then the data is read. FIG. 32 shows a timing chart of the write operation in the pseudo SRAM. As shown in FIG. 32, in the pseudo SRAM, the X address, the Y address, and the data Q0 that is the head data are input together with the write command WRT, and then the data is continuously input.

  In the semiconductor memory device 1 according to the present invention, in order to store multidimensional image data in a memory cell connected to one word line, address information is held using an address conversion method as in this embodiment. However, it is possible to write by full page operation. In this way, one image data can be read or written in one full page operation without re-inputting the address. As a result, the semiconductor memory device 1 of the present invention can reduce the time required for re-input of addresses and commands and the precharge operation, thereby realizing high-speed access to the memory.

Embodiment 8
In Embodiment 8, an example in which a reset operation is once performed on a memory cell in a cell array at the time of data writing and then data writing is performed will be described. FIG. 33 shows a detailed block diagram of the word line selector 16, the memory cell array 17, and the sense amplifier / write amplifier 18 in the eighth embodiment. In FIG. 33, the logic circuit 12 is shown as a block for generating a clear signal CLR to be described later.

  As shown in FIG. 33, the word line selector 16 includes a reset control circuit 16a in addition to the function of the word line selector that selectively drives the word line X. The reset control circuit 16a gives a reset potential (for example, ground potential) to the bit line DT of the cell array based on the clear signal CLR output from the logic circuit 12, for example. The cell array 17 includes a bit line pair Y including the bit lines DT and DB, and a memory cell MC connected between one of the bit lines DT and DB and the word line X. The memory cell MC is a storage element that stores data. In FIG. 33, only four word lines X and four bit line pairs Y are shown for the sake of simplification, but actually, there are far more word lines X and bit line pairs. . The sense amplifier / write amplifier 18 includes a sense amplifier SA and a write amplifier WA, but these circuits can use the same circuit in common. FIG. 33 shows only the write amplifier WA related to the characteristic operation of the seventh embodiment.

  Here, a data write operation of the semiconductor memory device 1 in the eighth embodiment will be described. FIG. 34 shows a timing chart of the data write operation. In the example shown in FIG. 34, data “1” is written to the memory cell MC connected to the 0th word line X and the 0th bit line pair Y, and data “0” is written to the other memory cells MC. An example is given. As shown in FIG. 34, in the write operation, the Y address is input together with the operation start command ACT at the clock CL1, and the X address and input data are input together with the write command WRT at the clock CL3. Then, the clear signal CLR rises during the period of the clocks CL3 to CL4 with the input of the write command WRT, the X address and the input data at the clock CL3. In response to the rise of the clear signal CLR, the bit line DT changes from the precharge voltage (for example, VDD / 2) to the low level. On the other hand, the bit line DB is changed from the precharge voltage (for example, VDD / 2) to the high level contrary to the bit line DT by the amplification operation of the write amplifier. As a result, each bit line pair is in a data “0” state. That is, all the memory cells MC hold the data “0”. After the clock CL4, the clear signal CLR falls in order to write data to the memory cell MC.

  Subsequently, data is written from the clock CL4 to the memory cell MC. In the example shown in FIG. 34, the number of memory cells MC to which data “1” is written is one (only the memory cells connected to the 0th bit line pair Y). Therefore, the potential of the 0th bit line pair Y is inverted by the clock CL4, and the data “1” is written to the memory cell MC connected to the 0th bit line pair Y. At this time, in the seventh embodiment, the memory cell MC to which data “0” is written is not subjected to the write operation because the reset value of the memory cell and the value of the write data are the same.

  From the above description, in the semiconductor memory device 1 according to the eighth embodiment, the memory cell MC is reset once before data is written to the memory cell MC, and only for the memory cell MC having a data value different from the reset state. Data write operation is performed. That is, even if other data is already written in the memory cell MC, the data stored in the memory cell MC by the reset operation is reset. For this reason, in the semiconductor memory device 1 according to the eighth embodiment, regardless of the data stored in the memory cell MC, the write operation is performed only for the memory cell MC that stores a value different from the reset state in the write data thereafter. To do. As a result, the number of memory cells MC that perform a data write operation can be reduced, so that the time required for the data write operation can be reduced.

Embodiment 9
In the example shown in the ninth embodiment, the address conversion circuit 15 of the semiconductor memory device 1 in the first embodiment is a semiconductor device different from other blocks. FIG. 35 shows a block diagram of the semiconductor memory device 1 according to the ninth embodiment. As shown in FIG. 35, the semiconductor memory device 1 according to the ninth embodiment is provided as a semiconductor device in which the memory 1a having a block other than the address conversion circuit 15 and the address conversion circuit 15 are different. The address conversion circuit 15 is provided between the memory 1a and the CPU 30. The address conversion circuit 15 in the ninth embodiment receives the X address and the Y address from the CPU 30 and converts them into the cell array row address CAX and the cell array column address CAY as in the above embodiment, Output as X address and Y address. In the ninth embodiment, commands and data are directly input from the CPU 30 to the memory 1a.

  Further, when transmitting address data to a general SDRAM or the like, the CPU 30 transmits a Y address corresponding to the cell array row address CAX together with the operation start command ACT, and corresponds to the cell array column address CAY together with the read command RED or the write command WRT. Send the X address. The address conversion circuit 15 generates a cell array row address CAX and a cell array column address CAY to be input to the memory 1a using a part of the X address and the Y address. Therefore, in the ninth embodiment, the address data transmission method of the CPU 30 is changed to a different one from the other embodiments.

  FIG. 36 shows a timing chart of the read operation in the ninth embodiment. In the example shown in FIG. 36, the same operation as that shown in FIG. 29 is applied to the semiconductor memory device 1 of the ninth embodiment. As shown in FIG. 36, in the ninth embodiment, the CPU 30 transmits Y addresses from the fifth bit to the seventh bit used as the cell array row address CAX together with the operation start command ACT. Then, the address conversion circuit 15 outputs the cell array row address CAX to the memory 1a based on the received address data. Thereafter, the Y address from the first bit to the fourth bit and the X address from the first bit to the third bit, which are used as the cell array column address CAY together with the read command RED, are transmitted. Then, the address conversion circuit 15 outputs the cell array column address CAY to the memory 1a based on the received address data.

  FIG. 37 shows a timing chart of the write operation in the ninth embodiment. In the example shown in FIG. 37, the same operation as that shown in FIG. 30 is applied to the semiconductor memory device 1 of the ninth embodiment. As shown in FIG. 37, in the ninth embodiment, the CPU 30 transmits to the address conversion circuit 15 Y addresses from the fifth bit to the seventh bit used as the cell array row address CAX together with the operation start command ACT. Then, the address conversion circuit 15 outputs the cell array row address CAX to the memory 1a based on the received address data. Thereafter, the CPU 30 transmits the Y address from the first bit to the fourth bit and the X address from the first bit to the third bit used as the cell array column address CAY together with the read command RED to the address conversion circuit 15. Then, the address conversion circuit 15 outputs the cell array column address CAY to the memory 1a based on the received address data.

  In this manner, by changing the address output method of the CPU 30, even if the address conversion circuit 15 is provided as another semiconductor device, the same operation as in the above embodiment can be performed. Further, by using the address conversion circuit 15 as another semiconductor device, it is possible to reduce power consumption and increase the speed of memory access using a general memory as in the above embodiment.

Embodiment 10
In the ninth embodiment, the address data output by the CPU 30 must be selected and output each time. When the address is selectively output, there is a problem that the operation of the CPU 30 becomes complicated. Therefore, in the tenth embodiment, a latch circuit 31 is provided before the address conversion circuit 15 in the ninth embodiment. A block diagram of the semiconductor memory device 1 having the latch circuit 31 is shown in FIG.

  The latch circuit 31 receives address data and command data output from the CPU 30, temporarily stores the address data, and selectively outputs an address according to the received command. The latch circuit 31 outputs the received command data to the address conversion circuit 15 in synchronization with the selected address data. For example, the latch circuit 31 receives the X address and the Y address from the CPU 30, and when the CPU 30 outputs the operation start command ACT, the latch circuit 31 uses the fifth to seventh bits used as the cell array row address CAX in synchronization with the operation start command ACT. The Y address up to the bit is output. When the CPU 30 outputs the read command RED or the write command WRT, the Y address and the first bit from the first bit to the fourth bit used as the cell array column address CAY in synchronization with the read command RED or the write command WRT. X address from the first to the third bit is output.

  FIG. 39 shows a timing chart of the read operation in the tenth embodiment. In the example shown in FIG. 39, the same operation as that shown in FIG. 29 is applied to the semiconductor memory device 1 of the tenth embodiment. As shown in FIG. 39, in the tenth embodiment, the CPU 10 transmits the X address and the Y address together with the operation start command ACT. Then, the latch circuit 31 transmits the Y address from the fifth bit to the seventh bit used as the cell array row address CAX together with the operation start command ACT to the address conversion circuit 15. The address conversion circuit 15 outputs the cell array row address CAX to the memory 1a based on the received address data. Thereafter, the latch circuit 31 transmits the Y address from the first bit to the fourth bit and the X address from the first bit to the third bit used as the cell array column address CAY together with the read command RED to the address conversion circuit 15. . The address conversion circuit 15 outputs the cell array column address CAY to the memory 1a based on the received address data.

  FIG. 40 shows a timing chart of the write operation in the tenth embodiment. In the example shown in FIG. 40, the same operation as that shown in FIG. 30 is applied to the semiconductor memory device 1 of the tenth embodiment. As shown in FIG. 40, in the tenth embodiment, the Y address from the fifth bit to the seventh bit used as the cell array row address CAX by the latch circuit 31 in synchronization with the operation start command ACT is sent to the address conversion circuit 15. Send. Then, the address conversion circuit 15 outputs the cell array row address CAX to the memory 1a based on the received address data. Thereafter, the latch circuit 31 transmits the Y address from the first bit to the fourth bit and the X address from the first bit to the third bit used as the cell array column address CAY together with the write command WRT to the address conversion circuit 15. . The address conversion circuit 15 outputs the cell array column address CAY to the memory 1a based on the received address data.

  From the above description, by providing the latch circuit 31 according to the present embodiment, the CPU 30 can output without selecting an address to be output. As a result, the operation of the CPU 30 is simplified, and the design of a program that operates on the CPU 30 can be simplified.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the present invention can be applied to any memory device in which memory cells are arranged in a lattice pattern, and can be applied not only to a DRAM but also to a flash memory or the like. In the above description, the data read operation is mainly described. However, the same effect as the read operation can be obtained in the write operation. It is also possible to realize the address conversion method and input method input to the semiconductor memory device described in the above embodiment by program description. When the above operation is realized by a program, no hardware change is required.

1 is a block diagram of a semiconductor memory device according to a first embodiment; 1 is a block diagram of an address conversion circuit according to a first exemplary embodiment; FIG. 6 is a diagram illustrating a conversion rule for address conversion when the address conversion circuit according to the first embodiment generates a cell array row address; FIG. 6 is a diagram illustrating a conversion rule for address conversion when the address conversion circuit according to the first embodiment generates a cell array column address; 3 is a diagram showing data storage positions on a cell array in the semiconductor memory device according to the first embodiment; FIG. It is a figure which shows the data storage position on the cell array in a common semiconductor memory device. FIG. 3 is a diagram illustrating an image read by the semiconductor memory device according to the first embodiment. 3 is a timing chart illustrating an operation of the semiconductor memory device according to the first embodiment; FIG. 3 is a diagram illustrating an image read by the semiconductor memory device according to the first embodiment. 3 is a timing chart illustrating an operation of the semiconductor memory device according to the first embodiment; FIG. 3 is a diagram illustrating an image read by the semiconductor memory device according to the first embodiment. 3 is a timing chart illustrating an operation of the semiconductor memory device according to the first embodiment; FIG. 3 is a diagram illustrating an image read by the semiconductor memory device according to the first embodiment. 3 is a timing chart illustrating an operation of the semiconductor memory device according to the first embodiment; FIG. 3 is a diagram illustrating an image read by the semiconductor memory device according to the first embodiment. 3 is a timing chart illustrating an operation of the semiconductor memory device according to the first embodiment; 3 is a diagram showing a comparative example of data read times of the semiconductor memory device according to the first embodiment and a general DRAM; FIG. FIG. 10 is a diagram showing a conversion rule for address conversion when the address conversion circuit according to the second embodiment generates a cell array row address; FIG. 10 is a diagram illustrating a conversion rule for address conversion when the address conversion circuit according to the second embodiment generates a cell array column address; FIG. 6 is a diagram showing data storage positions on a cell array in the semiconductor memory device according to the second embodiment; FIG. 6 is a diagram illustrating an image read by the semiconductor memory device according to the second embodiment. 6 is a timing chart illustrating an operation of the semiconductor memory device according to the second embodiment; 6 is a timing chart illustrating an operation of the semiconductor memory device according to the fourth embodiment; 10 is a timing chart (during serial operation) showing the operation of the semiconductor memory device according to the fifth embodiment; 12 is a timing chart (during parallel operation) showing the operation of the semiconductor memory device according to the fifth embodiment; FIG. 20 is a diagram illustrating an image conversion method handled in the sixth embodiment. 10 is a timing chart showing the operation of the semiconductor memory device according to the sixth embodiment; FIG. 10 is a diagram showing an image read by the semiconductor memory device according to the seventh embodiment. 10 is a timing chart showing a read operation of the semiconductor memory device according to the seventh embodiment; 12 is a timing chart showing a write operation of the semiconductor memory device according to the seventh embodiment; 12 is a timing chart illustrating another example of the read operation of the semiconductor memory device according to the seventh embodiment; 12 is a timing chart showing another example of the write operation of the semiconductor memory device according to the seventh embodiment; FIG. 10 is a block diagram of a word line selector, a memory cell array, and a write amplifier / sense amplifier in a semiconductor memory device according to an eighth embodiment; 10 is a timing chart of a write operation in the semiconductor memory device according to the eighth embodiment. FIG. 10 is a block diagram of a semiconductor memory device according to a ninth embodiment. 10 is a timing chart showing a read operation of the semiconductor memory device according to the ninth embodiment; 10 is a timing chart showing a write operation of the semiconductor memory device according to the ninth embodiment; FIG. 10 is a block diagram of a semiconductor memory device according to a tenth embodiment. 21 is a timing chart showing a read operation of the semiconductor memory device according to the tenth embodiment; 22 is a timing chart showing a write operation of the semiconductor memory device according to the tenth embodiment; 1 is a block diagram of a semiconductor memory device disclosed in Patent Document 1. FIG. 10 is a block diagram of a semiconductor memory device disclosed in Patent Document 2. FIG. 10 is a block diagram of a semiconductor memory device disclosed in Patent Document 3. FIG. 10 is a block diagram of a semiconductor memory device disclosed in Patent Document 4. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 10 Clock generation circuit 11 Command decoder 12 Logic circuit 13 Mode register 14 Address control circuit 15 Address conversion circuit 15a-15d Image map circuit 15e Image map selector 16 Word line selector 17 Cell array 18 Write amplifier / sense amplifier 19 Amplifier selector 20 Latch circuit 21 Input / output buffer 30 CPU
31 latch circuit WL word line address BL bit line address BA bank address CAX cell array row address CAY cell array column address CKE clock enable signal CLK clock signal CLKb inverted clock signal CS chip select signal WE write enable signal DQ data

Claims (14)

A semiconductor memory device that stores data having a multidimensional space based on the coordinate information of the data,
A cell array in which memory cells for storing the data are arranged in a grid pattern;
A word line selector that selects and drives any one of a plurality of word lines that activate the memory cells arranged in a row direction;
A plurality of write amplifiers and sense amplifiers for writing and reading data to and from the memory cells arranged in the column direction;
An amplifier selector that selects one of the plurality of write amplifiers and sense amplifiers, and inputs and outputs the data to and from the selected write amplifier and sense amplifier;
An address conversion circuit for generating one row address to be given to the word line selector based on the coordinate information of the data, making the coordinate information of the data one-dimensional, and generating a column address to be given to the amplifier selector;
A semiconductor memory device.   The semiconductor memory device according to claim 1, wherein the address conversion circuit generates the row address using a bit value of a portion that is a common value among a plurality of the data among address values indicating the coordinate information.   3. The semiconductor memory device according to claim 1, wherein the address conversion circuit generates the column address by combining bit values of portions that are different in each of the plurality of data among the address values indicating the coordinate information. .   The address conversion circuit assigns a terminal address to an input / output terminal number associated with the data, and generates the column address by combining the terminal address and the coordinate information. The semiconductor memory device described in 1.   When the value of the data is set by a plurality of bits, the address conversion circuit assigns a data address to each bit of the plurality of bits, and generates the column address by combining the data address and the coordinate information The semiconductor memory device according to claim 1.   The address conversion circuit divides the size of the space into small spaces whose size is defined by the number of data represented by a power of 2, assigns a small space address to a number indicating the small space, and The semiconductor memory device according to claim 1, wherein the column address is generated by combining a space address and the coordinate information.   The address conversion circuit includes a plurality of image map circuits corresponding to the size of the data space, and one of the image map circuits is selected according to an image size selection signal that specifies the size of the data space. The semiconductor memory device according to claim 1, which is selected.   8. The semiconductor memory device according to claim 7, wherein the image map circuit performs address conversion based on a rule set in advance for each space size of the data.   The semiconductor memory device according to claim 1, wherein the semiconductor memory device performs a burst operation for continuously inputting / outputting a plurality of the data.   9. The semiconductor memory device according to claim 1, wherein the semiconductor memory device performs a full page operation in which a plurality of the memory cells connected to one word line are accessed by one address input. .   The semiconductor memory according to claim 1, wherein the semiconductor memory device has a reset control circuit that controls all memory cells to a reset state before writing the data to the memory cells. apparatus.   12. The semiconductor memory device according to claim 1, wherein the address conversion circuit and other functional blocks are formed on a different semiconductor substrate.   The semiconductor memory device temporarily stores the address data transmitted from the transmitting device before the address conversion circuit, and responds to a command signal designating the operation of the semiconductor memory device transmitted from the transmitting device. The semiconductor memory device according to claim 12, further comprising a latch circuit that transmits address data selected from the address data to the address conversion circuit. A data storage method in a semiconductor memory device, in which memory cells for storing data have a cell array arranged in a grid pattern, and data having a multidimensional space is stored in the cell array based on the coordinate information of the data. ,
Determining a row address in which the data is stored based on one coordinate information of the coordinate information of the data;
A data storage method in a semiconductor memory device, wherein a column address for storing the data is determined based on the coordinate information that has been made one-dimensional.

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