JP2009044402A - Delay pulse generation circuit - Google Patents

Abstract

An output pulse is generated by delaying an input pulse without using a clock pulse.
A first delay circuit that starts an operation in response to an external input pulse signal and changes an output signal after a first delay time T1 from the start of the operation, and in response to the output signal, A second delay circuit 104 that starts the operation after the first delay time T1 from the start of the operation and changes the output signal after the second delay time T2 from the start of the operation. In response, an output pulse signal is generated by delaying the input pulse signal.
[Selection] Figure 1

Description

  The present invention relates to a delay pulse generation circuit that outputs an input pulse signal with a delay.

  A delay pulse generation circuit that outputs an input pulse signal with a predetermined time delay is known. The delay pulse generation circuit generally generates a reset pulse from a pulse signal, resets the counter with the reset pulse, and then outputs an output pulse signal when the counter counts the number of clock pulses a predetermined number of times. (Patent Document 1 etc.).

Japanese Patent No. 321811

  By the way, in the case of the above configuration, only the clock pulse cycle unit can be selected as the delay time and the adjustment width of the time. Although the apparent accuracy can be increased by increasing the frequency of the clock pulse, there is a problem that the configuration of the delay pulse generation circuit becomes complicated in order to cope with the high frequency. Furthermore, as the frequency increases, power consumption increases and the problem of circuit heat generation also arises.

  In the case of the above configuration, if an abnormal reset pulse is applied due to disturbance or the like, the counter is erroneously reset, and there is a possibility that the delay time or the time interval may be shifted.

  In view of the above problems, an object of the present invention is to provide a delayed pulse generation circuit capable of solving at least one problem.

  One aspect of the present invention includes a first delay circuit that starts a delay process in response to an external input pulse signal and outputs a predetermined first output signal after a first delay time from the start of the delay process. In response to the first output signal, a delay process is started after a first delay time from the start of the delay process, and a predetermined second output signal is output after a second delay time from the start of the delay process. And a delay pulse generation circuit that generates an output pulse signal obtained by delaying the input pulse signal from the first output signal and the second output signal.

  Here, the first delay circuit compares a capacitor that charges and discharges according to the input from the outside, a terminal voltage of the capacitor, and a predetermined reference voltage, and according to the comparison result, It is good also as a structure provided with the comparator which outputs a 1st output signal.

  The second delay circuit compares a capacitor that charges and discharges according to the first output signal, a terminal voltage of the capacitor, and a predetermined reference voltage, and determines the first delay circuit according to the comparison result. It is good also as a structure provided with the comparator which outputs 2 output signals.

  Further, an AND of an inverting element that inverts one of the first output signal and the second output signal, an output signal of the inverting element, and the other of the first output signal and the second output signal. An AND element that calculates and outputs the output pulse signal, and the inverting element and the AND element generate an output pulse signal obtained by delaying the input pulse signal from the first output signal and the second output signal. It is good also as a structure.

  According to the present invention, it is possible to generate an output pulse signal obtained by delaying an input pulse signal without using a clock pulse.

  As shown in FIG. 1, the delay pulse generation circuit 100 according to the embodiment of the present invention includes a first switching element 10, a first delay unit 12, a first comparator 14, a second switching element 16, and a second delay unit 18. And the second comparator 20. The first switching element 10, the first delay unit 12 and the first comparator 14 constitute a first delay circuit 102, and the second switching element 16, the second delay unit 18 and the second comparator 20 are a second delay. The circuit 104 is configured.

  That is, the delay pulse generation circuit 100 in this embodiment includes a first delay circuit 102 that starts an operation in response to an input pulse signal from the outside, and the first delay circuit 102 has a first delay from the start of the operation. A second delay circuit 104 that outputs a first output signal after a delay time, and starts an operation after a first delay time from the input of an input pulse signal in response to the first output signal. 104 outputs a second output signal after a second delay time from the start of the operation. An output pulse signal is generated and output based on the first output signal and the second output signal.

  Hereinafter, the configuration and operation of the delay pulse generation circuit 100 shown in FIG. 2 will be described with reference to a specific example.

  The first switching element 10 is composed of a transistor. The first delay unit 12 includes a constant current source I1. A capacitor C1 is connected in series to the constant current source I1 of the first delay unit 12, and the first switching element 10 is connected to the connection point. One end of the capacitor C1 is grounded. Thus, when the first switching element 10 is off (open), the electric charge is charged from the constant current source I1 to the capacitor C1, and when the first switching element 10 is on (closed), the capacitor C1 passes through the first switching element 10. Charge is discharged. In addition, a limiter circuit including a transistor Tr1 is connected to a terminal of the capacitor C1 that is not grounded, and the maximum terminal voltage of the capacitor C1 is determined by the voltage applied to the base of the transistor Tr1. -Limited to the voltage between the emitters.

  The first comparator 14 includes a differential amplifier. The terminal voltage X1 of the capacitor C1 is input to the inverting input terminal of the differential amplifier of the first comparator 14. The first reference voltage V1 is input to the non-inverting input terminal of the differential amplifier of the first comparator 14. Therefore, when the terminal voltage X1 of the capacitor C1 is smaller than the first reference voltage V1, the output A of the first comparator 14 is at a high level, and when the terminal voltage X1 of the capacitor C1 is equal to or higher than the first reference voltage V1, The output A of the comparator 14 becomes low level.

  The second delay circuit 104 can have a structure similar to that of the first delay circuit 102. The second switching element 16 is composed of a transistor. The second delay unit 18 includes a constant current source I2. A capacitor C2 is connected in series to the constant current source I2 of the second delay unit 18, and the second switching element 16 is connected to the connection point. One end of the capacitor C2 is grounded. Thereby, when the second switching element 16 is off (open), the electric charge is charged from the constant current source I2 to the capacitor C2, and when the second switching element 16 is on (closed), the capacitor C2 passes through the second switching element 16. Charge is discharged. Further, a limiter circuit including a transistor Tr2 is connected to a terminal of the capacitor C2 that is not grounded, and the maximum terminal voltage of the capacitor C2 is determined by the voltage applied to the base of the transistor Tr2, and the collector of the transistor Tr2. -Limited to the voltage between the emitters.

  The second comparator 20 includes a differential amplifier. The terminal voltage X2 of the capacitor C2 is input to the inverting input terminal of the differential amplifier of the second comparator 20. The second reference voltage V2 is input to the non-inverting input terminal of the differential amplifier of the second comparator 20. Therefore, when the terminal voltage X2 of the capacitor C2 is smaller than the second reference voltage V2, the output B of the second comparator 20 is at a high level, and when the terminal voltage X2 of the capacitor C2 is equal to or higher than the second reference voltage V2, the second voltage is output. The output B of the comparator 20 becomes low level.

  The output A of the first comparator 14 is input to the inverting element 22. The inverting element 22 inverts the output A of the first comparator 14 and outputs it to the AND element. The output B of the second comparator 20 and the output of the inverting element 22 are input to the AND element 24. The AND element 24 calculates a logical product of the output B of the second comparator 20 and the output of the inverting element 22 and outputs it as an output pulse signal.

  Next, a specific operation when an input pulse signal is input to the delay pulse generation circuit 100 will be described with reference to the timing chart of FIG. In FIG. 3, the vertical axis represents the level (voltage) of each signal, and the horizontal axis represents time.

  When the input pulse signal becomes high level at time t1, the first switching element 10 is turned on (closed), the charge stored in the capacitor C1 is discharged through the first switching element 10, and the terminal voltage X1 becomes low. Become a level. Along with this, the terminal voltage X1 becomes smaller than the first reference voltage V1, and the output A of the first comparator 14 is changed to a high level. Further, as the output A becomes high level, the second switching element 16 is turned on (closed), and the electric charge stored in the capacitor C2 is discharged through the second switching element 16, and the terminal voltage X2 becomes low level. Along with this, the terminal voltage X2 becomes smaller than the second reference voltage V2, and the output B of the second comparator 20 is changed to a high level.

  At this time, since the inverted signal of the output A is at a low level, the output pulse signal output from the AND element 24 is at a low level.

  When the input pulse signal changes to a low level at time t2, the first switching element 10 is turned off (opened), and electric charge starts to be charged from the constant current source I1 to the capacitor C1. The time T1 until the terminal voltage X1 of the capacitor C1 becomes equal to or higher than the first reference voltage V1, that is, the delay time T1 from the start to the end of the delay process in the first delay circuit 102 is expressed by T1 = C1 × V1 / I1. Is done.

  The delay time T1 can be appropriately adjusted according to the output current value of the constant current source I1, the capacitance value of the capacitor C1, the voltage value applied to the base of the transistor Tr1, and the like.

  Since the terminal voltage X1 is smaller than the first reference voltage V1 during the period from the start of charging the capacitor C1 until the terminal voltage X1 of the capacitor C1 becomes equal to or higher than the first reference voltage V1, the output A of the first comparator 14 Is maintained at a high level. If it does so, the 2nd switching element 16 will maintain an ON (closed) state, and the capacitor | condenser C2 will also maintain a discharge state. Therefore, the terminal voltage X2 is smaller than the second reference voltage V2, and the output B of the second comparator 20 is also maintained at a high level.

  At this time, since the inverted signal of the output A is still at the low level, the output pulse signal output from the AND element 24 is at the low level.

  When the capacitor C1 is charged until the terminal voltage X1 becomes equal to or higher than the first reference voltage V1 at time t3, the output A of the first comparator 14 changes from high level to low level. This timing is the end timing of the delay processing in the first delay circuit 102. Along with this, the second switching element 16 is changed to the off (open) state, and the capacitor C2 changes from the discharged state to the charged state. That is, electric charge starts to be charged from the constant current source I2 to the capacitor C2. The time T2 until the terminal voltage X2 of the capacitor C2 becomes equal to or higher than the second reference voltage V2, that is, the delay time T2 from the start to the end of the delay process in the second delay circuit 104 is expressed by T2 = C2 × V2 / I2. Is done.

  In the present embodiment, it is preferable that the delay time T2 is set in advance so as to be equal to the pulse width of the input pulse signal. The delay time T2 can be appropriately adjusted according to the output current value of the constant current source I2, the capacitance value of the capacitor C2, the voltage applied to the base of the transistor Tr2, and the like.

  Since the terminal voltage X2 is smaller than the second reference voltage V2 from the start of charge accumulation in the capacitor C2 until the terminal voltage X2 of the capacitor C2 becomes equal to or higher than the second reference voltage V2, the output B of the second comparator 20 Is maintained at a high level.

  At this time, since the inverted signal of the output A becomes the high level, the output pulse signal output from the AND element 24 changes from the low level to the high level.

  When the capacitor C2 is charged until the terminal voltage X2 becomes equal to or higher than the second reference voltage V2 at time t4, the output B of the second comparator 20 changes from high level to low level. Along with this, the output pulse signal output from the AND element 24 changes from the high level to the low level.

  As described above, according to the present embodiment, an output pulse signal obtained by delaying an input pulse signal can be generated without using a process such as counting clock pulses. Thereby, the configuration of the delay pulse generating circuit can be simplified. In addition, the problem of increased power consumption and circuit heat generation associated with higher frequencies can be avoided.

  In addition, since the counter is not used, an abnormal reset pulse is not applied due to disturbance or the like and the counter is not erroneously reset, and there is no possibility that the delay time or time interval is shifted due to disturbance or the like.

  Note that the present invention is not limited to the embodiment shown in FIG. 2, and any delay circuit may be used as long as a plurality of delay circuits are connected in series to delay the rise and fall of the pulse. For example, the first output signal output from the first delay circuit and the second output signal output from the second delay circuit change from a high level to a low level according to the input pulse signal. You can also

It is a block diagram which shows the basic composition of the delay pulse generation circuit in embodiment of this invention. It is a figure which shows the structural example of the delay pulse generation circuit in embodiment of this invention. It is a timing chart explaining the effect | action of the delay pulse generation circuit in embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 1st switching element, 12 1st delay part, 14 1st comparator, 16 2nd switching element, 18 2nd delay part, 20 2nd comparator, 22 Inversion element, 24 AND element, 100 Delay pulse generation circuit, 102 1st delay circuit, 104 2nd delay circuit.

Claims (4)

A first delay circuit that starts a delay process in response to an external input pulse signal and outputs a predetermined first output signal after a first delay time from the start of the delay process;
In response to the first output signal, a delay process is started after a first delay time from the start of the delay process, and a predetermined second output signal is output after a second delay time from the start of the delay process. And a delay circuit of
A delayed pulse generating circuit, wherein an output pulse signal obtained by delaying the input pulse signal is generated from the first output signal and the second output signal. The delayed pulse generation circuit according to claim 1,
The first delay circuit includes:
A capacitor that charges and discharges according to the external input;
A comparator that compares the terminal voltage of the capacitor with a predetermined reference voltage and outputs the first output signal according to the comparison result;
A delay pulse generating circuit comprising: The delayed pulse generation circuit according to claim 1 or 2,
The second delay circuit includes:
A capacitor that charges and discharges according to the first output signal;
A comparator that compares the terminal voltage of the capacitor with a predetermined reference voltage and outputs the second output signal according to the comparison result;
A delay pulse generating circuit comprising: The delay pulse generation circuit according to any one of claims 1 to 3,
An inverting element that inverts one of the first output signal and the second output signal;
An AND element that calculates and outputs a logical product of the output signal of the inverting element and the other of the first output signal and the second output signal;
A delay pulse generation circuit, wherein the inverting element and the AND element generate an output pulse signal obtained by delaying the input pulse signal from the first output signal and the second output signal.

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