JP2009009512A - Bus system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the data transfer efficiency in a bus system which is so configured that a data signal is transmitted/received between a master module and one of a plurality of slave modules which are connected through a system bus, on the basis of a command of the master module. <P>SOLUTION: Slave modules 2A and 2B inform a master module 1 of their load conditions, and the master module 1 reduces priorities of the command for slave modules 2A and 2B according as loads are heavier. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bus system, and more particularly to a bus system in which data is transmitted and received between a master module and a plurality of slave modules.

  FIG. 8 is a configuration diagram of a conventional bus system.

  The master module 1 and slave modules 2A and 2B are connected via a system bus 4.

  The master module 1 and the slave modules 2A and 2B exchange various signals via the system bus 4. FIG. 8 shows only signals necessary for explanation.

  The bus request signal 5 and the write data signal 7 output by the master module 1 are input to the slave modules 2A and 2B via the system bus 4.

  The bus response signal 6 and the read data signal 8 output by the slave modules 2A and 2B are input to the master module 1 via the system bus 4.

  FIG. 9 is a time chart of a conventional bus system.

  When making a read request, first, the master module 1 outputs a data read command together with the bus request signal 5 to the slave modules 2A and 2B. Next, the slave module 2A outputs a bus response signal 6 and responds. Thereafter, when read data is ready in the slave module 2A, the read data signal 8 is output to the master module 1 together with the read data valid signal and status.

  In a bus system used for a microcomputer or the like, measures are taken to prevent the latency for a specific access from affecting the latency of the entire system bus in order to improve performance. As an example of such measures, there are a function of issuing a plurality of bus instructions without waiting for the end of bus access and a function of out-of-order processing of bus instructions (Non-Patent Document 1).

May Woman, “AXI specification for high-performance buses added to AMBA 3.0”, Design Wave Magazine, December 2003, Volume 73, p. 47-57

  The following analysis was made by the present inventors.

  In the prior art, there are restrictions on the size of the command queue of the master module 1 and the slave modules 2A and 2B, the number of command IDs issued on the system bus 4 and the like in order to issue multiple bus instructions and out-of-order processing. When either of the upper limits is reached, the command cannot be issued, or the slave modules 2A and 2B are denied access.

  Such a phenomenon frequently occurs in a system in which the command queues of the slave modules 2A and 2B are small and a bus system in which the command ID is small due to bus specifications.

  In the master module 1 such as a bridge, a plurality of bus requests are generated.

  For example, when access is denied due to the command queue remaining amount limit of the slave module 2A, useless traffic occurs on the system bus 4 as a result from the bus request of the master module 1 to the reply of access denial by the bus response. As a result, the bus transfer efficiency decreases. Further, when dummy data is transferred following the bus response, the bus transfer efficiency is further reduced (FIG. 10).

  If such traffic can be avoided, for example, data transfer to another slave module 2B can be performed, and the system bus 4 can be used effectively. Therefore, it is preferable to hold the bus request so that access is denied from the beginning so that another request is preferentially accessed.

  Therefore, in a bus system configured to transmit and receive data signals based on a command of the master module between a master module and a plurality of slave modules connected via the system bus, transfer efficiency is improved. Is an issue.

  In the bus system according to the first aspect of the present invention, a data signal is transmitted / received between a master module connected via a system bus and one of a plurality of slave modules based on a command of the master module. In the bus system configured as described above, the slave module is configured to notify the master module of its own load status, and the master module lowers the priority of commands to the slave module as the load increases. It was configured as described above.

  With the bus system according to the present invention, the frequency with which data transfer requests by the master module are rejected by the slave module is reduced, and unnecessary traffic on the system bus can be reduced, so that the data transfer efficiency on the system bus can be improved. it can.

  The bus system according to the first aspect of the present invention is as described above.

  The bus system according to the first development mode is characterized in that the slave module notifies the load status in a data signal transmitted to the master module.

  In the bus system according to the second development mode, the load status is the remaining command queue remaining in the slave module, and the master module is more likely to issue the command queue than the number of commands that the slave module intends to issue. The present invention is characterized in that the command priority for the slave module with a small remaining amount is lowered.

  A bus system according to a third development mode is characterized in that the system bus includes a selector that selects any one of the load situations notified from the slave module and notifies the master module.

  The bus system according to a fourth development mode is characterized in that the selector is configured to select any one of the load situations based on a round robin method.

  Referring to FIG. 1, the bus system according to the embodiment of the present invention refers to a load that notifies the system bus 4 of the load status of the slave modules 2A and 2B from the slave modules 2A and 2B to the master module 1. A status notification signal 9 is added.

  The load status notification signal 9 notifies the command queue remaining amount of the slave modules 2A and 2B. In the master module 1, the command issue priority is changed according to the command queue remaining amount of the target slave modules 2A and 2B.

  In the master module 1, if there is no remaining command queue in the target slave modules 2A and 2B, the command issuance is suspended, and the number of commands scheduled to be issued by the master module 1 and the remaining command queue in the target slave modules 2A and 2B are determined. If the remaining command queue amounts of the target slave modules 2A and 2B are insufficient, the command issue priority to the target slave modules 2A and 2B is lowered.

  FIG. 1 shows a block diagram of a bus system according to a first embodiment of the present invention.

  Compared to the configuration diagram of the conventional bus system (FIG. 8), a load status notification signal 9 is newly added.

  The load status notification signal 9 is output by the slave modules 2A and 2B and input to the master module 1 via the system bus 4.

  The load status notification signal 9 includes the remaining command queues of the slave modules 2A and 2B and the slave module ID for identifying the slave modules 2A and 2B.

  FIG. 2 is a more detailed configuration diagram for the bus system according to the first embodiment of the present invention.

  The master module 1 includes a load status table 11 and records the load status of the slave modules 2A and 2B in the load status table 11.

  The load status notification signal 9 output from the slave modules 2A and 2B is input to the load status notification signal selector 10 provided in the system bus 4, and one of the slave modules 2A and 2B is selected and notified to the master module 1. The

  FIG. 3 is a time chart of the bus system according to the first embodiment.

  The operation of the first embodiment will be described with reference to FIG.

  Each of the slave modules 2A and 2B outputs a load status notification signal 9 continuously. The load status notification signal 9 notifies the slave module ID and the remaining command queue.

  The load status notification signal selector 10 selects which of the slave modules 2A and 2B is notified of the load status notification signal 9 to the master module 1. The selection method may be, for example, a round robin method.

  The master module 1 reads the slave module ID and the command queue remaining amount from the received load status notification signal 9, and updates the command queue remaining amount of each of the slave modules 2A and 2B recorded in the load status table 11.

  In the master module 1, when a bus request is generated for the slave modules 2A and 2B, if the remaining command queue is zero in the load status table 11, the bus request is suspended and the remaining command queue Re-evaluate when is updated. Also, the number of bus request commands is compared with the remaining command queue, and if the remaining command queue is smaller, the priority of the bus request is lowered.

  When the remaining command queues of the slave modules 2A and 2B are 0, when a bus request is made, a certain bus bandwidth is occupied by the bus request signal and the bus response signal. Also, depending on the bus system, dummy data transfer is involved, so that a larger bus bandwidth is occupied. However, since data transfer is not actually performed, transfer efficiency is reduced.

  In the present invention, by holding a bus request that is rejected by the slave modules 2A and 2B, data transfer can be performed even during a period in which error information was notified in the prior art.

  Also in the prior art, a method of issuing another command without waiting for the end of the command is known. For this reason, when the master module 1 issues commands continuously without waiting for the responses of the slave modules 2A and 2B, a large number of commands whose responses are rejected occur.

  In the bus system according to the present invention, since the command issuance is suspended in such a case, it is possible to prevent a command that is rejected by the slave modules 2A and 2B from being issued on the system bus 4.

  FIG. 4 is a block diagram of a bus system according to the second embodiment of the present invention.

  In the first embodiment, the load status notification signal 9 is realized as an independent signal.

  In the present embodiment, the extended read data signal 12 that combines the load status notification signal 9 and the read data signal 8 is used.

  The shared use of the read data signal 8 and the load status notification signal 9 is performed in a time-sharing manner. When the RDVALID signal is active, the read data signal 8 is a function from the prior art, and when the RDVALID signal is inactive, the load status notification is performed. Signal 9 can be used.

  As a result, the number of signals in the system bus 4 can be reduced as compared with the first embodiment, and the present invention can be realized with the same number of signals as in the prior art (FIG. 8).

  The operation of the second embodiment will be described with reference to the time chart of FIG.

  The extended read data signal 12 is output from the slave modules 2A and 2B and input to the master module 1 via the system bus 4. Of the extended read data signal 12, the load status notification signal 9 includes a slave module ID for identifying the slave modules 2A and 2B together with the remaining command queues of the slave modules 2A and 2B.

  FIG. 5 shows in more detail the block diagram of the bus system according to the second embodiment of the present invention.

  The master module 1 includes a load status table 11 that records the load status of the slave modules 2A and 2B.

  The extended read data signal 12 output from each slave module 2A, 2B is input to the load status notification signal selector 10, and the extended read data signal 12 output from any one of the slave modules 2A, 2B is selected. The master module 1 is notified.

  FIG. 7 is a flowchart of the operation of the load status notification signal selector 10.

  The load status notification signal selector 10 determines whether the extended read data signal 12 is the read data signal 8 or the load status notification signal 9 (step S71).

  When the extended read data signal 12 is the read data signal 8, the load status notification signal selector 10 preferentially selects the slave module that outputs the read data (step S72).

  On the other hand, when the extended read data signal 12 is the load status notification signal 9, the load status notification signal selector 10 selects the slave modules 2A and 2B by round robin (step S73).

  In the master module 1, when a request to use the system bus 4 is generated for the slave modules 2A and 2B, if the remaining command queue recorded in the load status table 11 is zero, the bus request is suspended. Re-evaluate when the remaining command queue is updated.

  Also, the command number of the bus request and the command queue remaining amount are compared, and if the command queue remaining amount is smaller, the priority of the bus request is lowered.

  According to the second embodiment, it is possible to notify the load status of the slave modules 2A and 2B without increasing the number of signals on the system bus 4 as compared with the conventional technique (FIG. 8).

  In the bus system according to the third embodiment of the present invention, the estimated value of the latency of the slave modules 2A and 2B is notified in the load status notification signal 9.

  The master module 1 uses this estimated latency value when making a bus request. When the number of remaining commands that can be issued by the master module 1 is small, a bus request is made by lowering the priority of a bus request having a large latency.

  In the first and second embodiments described above, the remaining amount of the command queue of the slave modules 2A and 2B is notified by the load status notification signal 9. However, in the third embodiment, the slave modules 2A and 2B send commands to the command queue. Notify the estimated latency when accepting.

  In the first and second embodiments, after the master module 1 issues a bus request, measures are taken for cases where the command queue remaining amount is insufficient in the slave modules 2A and 2B and access is denied.

  In the third embodiment, measures are taken when the number of remaining commands that the master module 1 can issue is small.

  The number of commands that can be issued by the master module 1 is limited by the command queue of the master module 1 and the remaining number of command IDs of the system bus 4. When the number of remaining issued commands is small, when a command with a long latency is issued, the waiting time until the next command is issued becomes long. Therefore, the master module 1 preferably issues a command with a short latency with priority.

1 is a configuration diagram of a bus system according to a first embodiment of the present invention. 1 is a detailed configuration diagram of a bus system according to a first embodiment of the present invention. It is a time chart of the bus system concerning the 1st example of the present invention. It is a block diagram of the bus system which concerns on 2nd Example of this invention. It is a detailed block diagram of the bus system based on 2nd Example of this invention. It is a time chart of the bus system which concerns on 2nd Example of this invention. It is a flowchart of the load condition notification signal selector in the bus system based on 2nd Example of this invention. It is a block diagram of the conventional bus system. It is a time chart of the conventional bus system. It is a time chart of the conventional bus system.

Explanation of symbols

1 Master module 2A, 2B Slave module 4 System bus 5 Bus request signal 6 Bus response signal 7 Write data signal 8 Read data signal 9 Load status notification signal 10 Load status notification signal selector 11 Load status table 12 Extended read data signal

Claims (5)

In a bus system configured to transmit / receive a data signal based on a command of the master module between a master module and any of a plurality of slave modules connected via a system bus,
The slave module is configured to notify the master module of its own load status;
The bus system, wherein the master module is configured to lower the priority of a command for the slave module as the load increases.   The bus system according to claim 1, wherein the slave module is configured to notify the load status in a data signal transmitted to the master module. The load status is the command queue remaining amount of the slave module,
The master module is configured to lower a command priority for a slave module having a remaining command queue remaining amount less than the number of commands to be issued among the slave modules. The bus system according to 1 or 2.   The bus according to any one of claims 1 to 3, wherein the system bus includes a selector that selects any one of the load conditions notified from the slave module and notifies the master module. system.   The bus system according to claim 4, wherein the selector is configured to select any one of the load situations based on a round robin method.

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