JP2008304599A - Method of driving display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a display panel to display an image of high quality. <P>SOLUTION: When driving display cells formed on the display panel to emit light with a plurality of grayscales, for the grayscales with higher luminance than a predetermined luminance level, a different luminance weight is allocated for each display line for each display line group consisting of the plurality of adjoining display lines, and a line dithering drive is executed to make each of the display cell belonging to each display line emit light with different luminance levels is performed. While for the grayscales with the lowest luminance among each of the grayscales with higher luminance than the predetermined luminance level, the luminance difference is made smaller between the luminance level when emitting light by the display cell belonging to the display line allocated with the largest luminance weight in comparison with the other luminance and the luminance level when emitting light by the display cell belonging to the display line allocated with the minimum luminance weight. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display panel driving method.

  As a two-dimensional image display panel, a plasma display device equipped with a plasma display panel (hereinafter referred to as PDP) in which a plurality of discharge cells are arranged in a matrix has been commercialized. In the plasma display apparatus, various brightness levels represented by the input video signal are expressed by driving the PDP based on the subfield method. In driving based on the subfield method, the display period of one field is divided into a plurality of subfields, and the following driving is performed for each subfield. That is, each discharge cell is set to a lighting mode or a non-lighting mode according to an input video signal, and only the discharge cells set to the lighting mode are repeatedly discharged for the number of times assigned to this subfield. According to this driving, an intermediate luminance corresponding to the total number of discharge luminescence generated within one field period can be obtained.

  Here, when performing driving based on the above-described subfield method, a driving method is proposed in which discharge light emission is performed only in each subfield continuous from the first subfield in order to prevent the occurrence of false contours. (For example, see FIG. 2 of Patent Document 1).

  However, in such a driving method, there is a limit to the number of subfields that divide one field, which causes a problem that the number of luminance gradations is insufficient. Therefore, the lack of the number of gradations is compensated by applying multi-gradation processing such as dither processing to the input video signal. In the dither processing, first, a different dither value is assigned to each pixel block made up of a plurality of pixels adjacent in the vertical and horizontal directions of the screen in correspondence with each pixel position in the pixel block. Next, pixel data corresponding to each pixel in the pixel block (data representing a luminance level represented by the input video signal) and a dither value corresponding to each pixel position are added. Then, the upper bit group in the pixel data after the dither addition is extracted, and the number of subfields in which discharge light emission should be performed continuously from the first subfield is determined according to the value of the upper bit group. As a result, the luminance corresponding to the average luminance of each pixel in the pixel block as described above is visually recognized.

  Further, in addition to the dither processing as described above, each pixel is caused to emit light with a different luminance weight for each display line in the display line group for each display line group consisting of a plurality of adjacent display lines. A drive method that performs line dither drive has been proposed (see, for example, Patent Document 2).

  FIG. 1 is a diagram illustrating an example of a light emission driving pattern when line dither driving is performed (see, for example, FIG. 4 of Patent Document 2).

  In the line dither drive shown in FIG. 1, in each gradation (MD “000” to MD “100”) when the luminance level indicated by the input video signal is divided into five stages, every four adjacent display lines. The brightness levels when the discharge cells belonging to the display line are caused to emit light are made different.

For example, in FIG. 1, in the driving of the second gradation (MD “001”) that represents one level higher than the first gradation (MD “000”) representing the lowest luminance,
Fourth (4N-3) display line: luminance level “2”
Fourth (4N-2) display line: luminance level “4”
Fourth (4N-1) display line: luminance level “6”
4th (4N) display line: Brightness level “8”
The discharge cells belonging to each display line are caused to emit light.

Further, in the driving of the third gradation (MD “010”) that expresses one level higher than the second gradation (MD “001”),
Fourth (4N-3) display line: luminance level “10”
4th (4N-2) display line: Brightness level “12”
(4N-1) th display line: luminance level “14”
4th (4N) display line: Brightness level “16”
The discharge cells belonging to each display line are caused to emit light.

Further, in the driving of the fourth gradation (MD “011”) that represents the brightness by one level higher than the third gradation (MD “010”),
Fourth (4N-3) display line: luminance level “18”
4th (4N-2) display line: Brightness level “20”
(4N-1) th display line: luminance level “22”
4th (4N) display line: Brightness level “24”
The discharge cells belonging to each display line are caused to emit light.

  Therefore, by performing such line dither driving based on the pixel data obtained by the dither processing as described above, for example, the discharge cells in the block have different brightnesses for each block of discharge cells for 4 rows × 4 columns. Light can be emitted at the level. At this time, the luminance corresponding to the average value of the luminance at the time of light emission of each discharge cell in each block is visually recognized.

  That is, each discharge cell in the block is caused to emit light with a luminance pattern (hereinafter referred to as a dither pattern) such that the average value is a value corresponding to the luminance value represented by the input video signal.

  Here, according to the line dither drive shown in FIG. 1, for each display line, the luminance difference between adjacent gradations in the discharge cells belonging to the display line is “8”. For example, since the discharge cells belonging to the (4N-3) th display line emit light at the luminance level “2” in the second gradation and the luminance level “10” in the third gradation, the luminance difference is “8”. It becomes. Further, since the discharge cells belonging to the (4N) th display line emit light at the luminance level “8” in the second gradation and the luminance level “16” in the third gradation, the luminance difference is also “8”. . In this way, even when the luminance weight is given to each display line, there is no variation in the luminance difference between adjacent gradations, so that a dither pattern representing the luminance value indicated by the input video signal can be easily formed. It becomes possible to make it.

  By the way, in the driving based on the subfield method as described above, when the luminance level indicated by the input video signal becomes low to some extent, it is impossible to apply a luminance weight to each display line.

  Therefore, for example, as shown in FIG. 1, the line dither drive is not performed at the first gradation (MD “000”) that expresses a lower luminance than the predetermined luminance.

  However, if the gray scale level where the line dither drive is not performed and the gray scale level where the line dither drive is performed coexist, the brightness difference between the gray levels for each display line varies at the boundary.

For example, the luminance difference for each display line between the first gradation (MD “000”) and the second gradation (MD “001”) shown in FIG.
4th (4N-3) display line: “2”
4th (4N-2) display line: "4"
4th (4N-1) display line: "6"
4th (4N) display line: “8”
As a result, the brightness difference varies.

Therefore, it is difficult to form a dither pattern representing the luminance value indicated by the input video signal at the time of low luminance gradation. Therefore, at this time, there is a problem that a dither pattern representing a luminance value slightly different from the luminance value indicated by the input video signal has to be adopted, and image quality deterioration occurs.
JP 2006-11224 A JP 2006-47970 A

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a display panel driving method capable of displaying a high-quality image.

  The display panel driving method according to claim 1 is for each of the first to M-th gradations (M: an integer of 2 or more) representing different luminance levels of the display cells arranged in each display line of the display panel. A display panel driving method for emitting light at a luminance level corresponding to one gradation corresponding to a luminance level indicated by a video signal, wherein a predetermined luminance level is selected from each of the first to Mth gradations. In a gradation representing high luminance, a luminance weight is assigned to each display line in the display line group for each display line group consisting of a plurality of adjacent display lines, and each display line is displayed based on the luminance weight. Line dither driving is performed to cause the display cells belonging to the line to emit light at different luminance levels, and among the gradations representing the lowest brightness among the gradations representing the brightness higher than the predetermined brightness level, other gradations are used. In comparison, the luminance level during the light emitting operation performed by the display cell belonging to the display line to which the maximum luminance weight is assigned and the display cell belonging to the display line to which the minimum luminance weight is assigned. The difference in luminance from the luminance level during the light emission operation is small.

  According to a third aspect of the present invention, there is provided a display panel driving method in which a display panel in which a plurality of display cells bearing pixels is arranged in each display line is displayed in units according to pixel data corresponding to each pixel based on a video signal. A display panel driving method in which gradation driving is performed for each of a plurality of subfields within a period, wherein each of the subfields is a number of times that only the display cells in a lighting mode are assigned to the subfield. A sustain process for repeatedly emitting light, and an address process for performing an erasing address operation for selectively shifting each of the display cells from the lighting mode state to the extinguishing mode state according to the pixel data, Subfield consisting of W (W: integer of 2 or more) subfields continuously arranged in the display period In the address process of each subfield belonging to one subfield group in each of the groups, only the display cells belonging to one display line group among the different first to Wth display line groups are subject to the erasure. In the addressing process of at least one subfield of each of the subfields belonging to the one subfield group, the address operation is performed, and at least one different from the one display line group together with the one display line group The erase address operation is executed for display cells belonging to the display line group.

  When the display cells formed on the display panel are driven to emit light with a plurality of gradations, the display lines are displayed for each display line group composed of a plurality of adjacent display lines in a gradation representing a luminance lower than a predetermined luminance level. The same luminance weight is assigned to each display cell, and each display cell belonging to each display line is caused to emit light at a luminance level corresponding to the gradation. On the other hand, in a gradation representing a luminance higher than a predetermined luminance level, line dither driving is performed in which different luminance weights are assigned to each display line for each display line group, and each display cell belonging to each display line emits light at a different luminance level. Execute. At this time, among the gradations representing the brightness higher than the predetermined brightness level, the display representing the lowest brightness among the gradations representing the brightness belongs to the display line to which the maximum brightness weight is assigned as compared with the other gradations. The luminance difference between the luminance level at the time of light emission performed in the cell and the luminance level at the time of light emission performed in the display cell belonging to the display line to which the minimum luminance weight is assigned is reduced.

  With such driving, the gradation that represents the lowest luminance among the gradations for which the line dither driving is performed, and the gradation that represents the lower luminance by one level than this gradation (the gradation in which the line dither driving is not performed) , The luminance difference for each display line is relatively small. Therefore, even when a low-brightness image is displayed, it is easy to form a dither pattern that represents the brightness value indicated by the input video signal, and a high-quality image can be provided.

  FIG. 2 is a diagram showing a schematic configuration of a plasma display apparatus for driving a plasma display panel according to the display panel driving method of the present invention.

In FIG. 2, a PDP 100 as a plasma display panel includes a front substrate (not shown) serving as a display surface, and a rear substrate (positioned opposite to the front substrate across a discharge space filled with a discharge gas). (Not shown). On the front substrate, row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n are formed alternately and parallel to each other. On the back substrate, column electrodes D _{1 to} D _m are formed so as to cross over the row electrodes. The row electrodes X _{1 to} X _n and Y _{1 to} Y _n have a structure that bears the first to nth display lines of the PDP _{100 with} a pair of row electrodes X and Y that are adjacent to each other. Discharge cells G (display cells) serving as pixels are formed at intersections (including discharge spaces) between the row electrode pairs and the column electrodes. That is, in the PDP 100, (n × m) discharge cells G _{(1,1) to} G _{(n, m)} are formed in a matrix.

  The pixel data conversion circuit 10 converts the luminance level for each pixel based on the input video signal into, for example, pixel data PD represented by 6 bits, and supplies this to the multi-gradation processing circuit 20.

  The multi-gradation processing circuit 20 includes an adder 200, a line offset data generation circuit 210, and an upper bit extraction circuit 230. The line offset data generation circuit 210 generates line offset data as shown in FIG.

  That is, the line offset data generation circuit 210 supplies pixel data PD corresponding to the (8N-7) th and (8N-4) th display lines [N: natural number less than (n / 8)] of the PDP 100. If it is, line offset data indicating “0” (decimal number expression) is supplied to the adder 200. When the pixel data PD corresponding to the (8N-6) th and (8N-1) th display lines is supplied, the line offset data generation circuit 210 sets “2” (decimal number representation). Is supplied to the adder 200. When the pixel data PD corresponding to the (8N-5) th and (8N-2) th display lines is supplied, the line offset data generation circuit 210 sets “6” (decimal number representation). Is supplied to the adder 200. When the pixel data PD corresponding to the (8N-3) th and (8N) th display lines is supplied, the line offset data generation circuit 210 indicates “4” (decimal number representation). Line offset data is supplied to the adder 200.

  The adder 200 supplies 6-bit offset addition pixel data KD obtained by adding the line offset data to the 6-bit pixel data PD supplied from the pixel data conversion circuit 10 to the upper bit extraction circuit 230. . The upper bit extraction circuit 230 truncates the lower 2 bits of the offset addition pixel data KD and supplies the remaining upper 4 bits to the pixel drive data generation circuit 30 as gradation pixel data MD.

  That is, the multi-gradation processing circuit 20 adds the line offset data as shown in FIG. 3 to each pixel data PD, thereby dividing the entire luminance range into eight stages as shown in FIG. 4-bit gradation pixel data MD corresponding to 8 gradations is generated and supplied to the pixel drive data generation circuit 30.

  The pixel drive data generation circuit 30 converts the gradation pixel data MD into 7-bit pixel drive data GD according to a conversion table as shown in FIG. Each bit of the pixel drive data GD has a logic level indicating whether or not the discharge cell G is subjected to selective erasure address discharge in the address process (described later) of the subfield corresponding to the bit digit. At this time, the first to seventh bits of the pixel drive data GD have the following correspondence with subfields SF0, SF1, and SF2, subfield groups SG3 to SG5, and subfield SF6, which will be described later.

1st bit: SF0
Second bit: SF1
Third bit: SF2
4th bit: SG3
5th bit: SG4
6th bit: SG5
7th bit: SF6
The memory 40 sequentially captures and stores pixel drive data GD for each pixel. Each time pixel drive data GD ₁ , _{1 to} GD _n , _m for one frame (n rows × m columns) is written, the following readout is performed. That is, the memory 40 reads out the bit digit bit corresponding to the subfield (or subfield group) from the pixel drive data GD for each subfield described later as the pixel drive data bit DB, and displays this one display. The lines are supplied to the column electrode driver 50 line by line.

  The drive control circuit 60 outputs various drive control signals for driving the PDP 100 in grayscale every one field or one frame display period (hereinafter referred to as a unit display period) according to the light emission drive sequence shown in FIG. Are supplied to the column electrode driver 50, the row electrode Y driver 70, and the row electrode X driver 80, respectively. The panel drive unit outputs various drive pulses in the subfields SF0, SF1, SF2, and the subfield groups SG3 (SF31 to SF34), SG4 (SF41 to SF44), SG5 (SF51 to SF54), and SF6 as shown in FIG. The voltage is applied to each discharge cell G via the column electrode D and the row electrodes X and Y.

That is, first, in the reset process R of the first subfield SF0, the row electrode Y driver 70 and the row electrode X driver 80 apply a reset pulse to each of the discharge cells G _{(1,1) to} G _{(n, m).} As a result, all discharge cells G are reset and discharged, and are initialized to a lighting mode (a state in which a predetermined amount of wall charges is formed).

Next, in the address process W0 of SF0, the column electrode driver 50 generates a pixel data pulse having a pulse voltage corresponding to the pixel drive data bit DB corresponding to the subfield SF0, and this is generated for one display line (m the number) per time to the column electrodes D ₁ to D _m, respectively. For example, the column electrode driver 50 is supplied with a pixel drive data bit DB of a predetermined high voltage and logic level 0 when a pixel drive data bit DB of logic level 1 to be shifted to the extinguishing mode state is supplied. Generates a pixel data pulse of low voltage (ground potential). Further, during this time, the row electrode Y driver 70 alternately and sequentially applies the scan pulse to each of the row electrodes Y _{1 to} Y _n . At this time, a selective erasure address discharge is generated in the discharge cell G to which a high voltage pixel data pulse to be shifted to the extinguishing mode state is applied together with the scan pulse. After the end of the selective erasure address discharge, the wall charges formed in the discharge cell G disappear, and the discharge cell G shifts to the extinguishing mode. On the other hand, although the scan pulse is applied, no discharge as described above occurs in the discharge cell G to which the low-voltage pixel data pulse is applied. Therefore, the discharge cell G maintains the state (lighting mode or extinguishing mode state) until just before that.

  Next, in the sustain process I of each of the subfields SF1 and SF2, the row electrode Y driver 70 and the row electrode X driver 80 are repeated by the number of sustain pulses previously assigned to the subfield, and all the row electrodes X A sustain pulse is applied alternately to Y and Y. In the present embodiment, each subfield (SF0 to SF2, SF31 to SF34, SF41 to SF44, SF51 to SF54, and SF6) is assigned the same number “2” as the number of sustain pulses applied. Shall.

  By executing the sustain process I, only the discharge cells G in the lighting mode are repeatedly subjected to the sustain discharge for the number of times of the sustain pulse application, and the light emission state associated with the discharge is maintained.

  Next, in each subfield in each of the subfield groups SG3 to SG5, immediately after the sustain process I, driving based on the following address processes W1, W2, W3, or W4 is performed.

In the address process W1, the row electrode Y driver 70, first of the row electrodes _{Y 1 ~Y n (8N-5} ) th and the (8N-2) th row electrodes Y each sequentially alternatively scan pulse to Apply. During this time, the column electrode driver 50 generates pixel data pulses corresponding to the discharge cells G belonging to the (8N-5) th and (8N-2) th row electrodes Y based on the pixel drive data bit DB. These are applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronism with the scanning pulse. The column electrode driver 50 generates a pixel data pulse having a predetermined high voltage when a pixel driving data bit DB having a logic level 1 for switching the discharge cell to the extinguishing mode is supplied. When the pixel drive data bit DB is supplied, a low voltage (ground voltage) pixel data pulse is generated. At this time, the selective erasure address discharge is generated only in the discharge cells G to which the scan pulse is applied and the pixel data pulse having a high voltage is applied. By this selective erasure address discharge, the wall charges formed in the discharge cell G are erased, and the discharge cell G is set to the extinguishing mode. On the other hand, the selective erase address discharge as described above is not generated in the discharge cell G to which the pixel data pulse having a low voltage is applied although the scan pulse is applied. Therefore, the discharge cell G maintains the state (lighting mode or extinguishing mode) until just before that.

  Thus, in the address process W1, only the discharge cells G belonging to the (8N-5) th and (8N-2) th display lines from among the first to nth display lines in the PDP 100 are targeted. An address operation for selectively changing each discharge cell G from the lighting mode state to the extinguishing mode state is performed.

Further, in the address process W2, row electrode Y driver 70, the row electrodes Y ₁ second (8N-3) of the to Y _n-th and the (8N) th row electrodes Y each sequentially alternatively scan pulse to Apply. During this time, the column electrode driver 50 generates pixel data pulses corresponding to the discharge cells G belonging to the (8N-3) th and (8N) th row electrodes Y based on the pixel drive data bit DB. and it applies the column electrodes D ₁ to D _m by one display line in synchronization with the scanning pulse (m pieces). The column electrode driver 50 generates a pixel data pulse having a predetermined high voltage when a pixel driving data bit DB having a logic level 1 for switching the discharge cell to the extinguishing mode is supplied. When the pixel drive data bit DB is supplied, a low voltage (ground voltage) pixel data pulse is generated. At this time, the selective erasure address discharge is generated only in the discharge cells G to which the scan pulse is applied and the pixel data pulse having a high voltage is applied. By this selective erasure address discharge, the wall charges formed in the discharge cell G are erased, and the discharge cell G is set to the extinguishing mode. On the other hand, the selective erase address discharge as described above is not generated in the discharge cell G to which the pixel data pulse having a low voltage is applied although the scan pulse is applied. Therefore, the discharge cell G maintains the state (lighting mode or extinguishing mode) until just before that.

  As described above, in the address process W2, only the discharge cells G belonging to the (8N-3) th and (8N) th display lines among the first to nth display lines in the PDP 100 are targeted. An address operation for selectively transitioning each G from the lighting mode state to the extinguishing mode state is performed.

Further, in the address process W3, the row electrode Y driver 70, the row electrodes Y ₁ second (8N-6) of the to Y _n-th and the (8N-1) th row electrodes Y each sequentially alternatively the A scan pulse is applied. During this time, the column electrode driver 50 generates pixel data pulses corresponding to the discharge cells G belonging to the (8N-6) th and (8N-1) th row electrodes Y based on the pixel drive data bit DB. These are applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronism with the scanning pulse. The column electrode driver 50 generates a pixel data pulse of a predetermined high voltage when a logic level 1 pixel drive data bit DB for switching the discharge cell to the extinguishing mode is supplied. When the pixel drive data bit DB is supplied, a low voltage (ground voltage) pixel data pulse is generated. At this time, the selective erasure address discharge is generated only in the discharge cells G to which the scan pulse is applied and the pixel data pulse having a high voltage is applied. By this selective erasure address discharge, the wall charges formed in the discharge cell G are erased, and the discharge cell G is set to the extinguishing mode. On the other hand, the selective erase address discharge as described above is not generated in the discharge cell G to which the pixel data pulse having a low voltage is applied although the scan pulse is applied. Therefore, the discharge cell G maintains the state (lighting mode or extinguishing mode) until just before that.

  Thus, in the address process W3, only the discharge cells G belonging to the (8N-6) th and (8N-1) th display lines among the first to nth display lines in the PDP 100 are targeted. An address operation for selectively changing each discharge cell G from the lighting mode state to the extinguishing mode state is performed.

Further, in the address process W4, the row electrode Y driver 70, the row electrodes Y ₁ second (8N-7) of the to Y _n-th and the (8N-4) th row electrodes Y each sequentially alternatively the A scan pulse is applied. During this time, the column electrode driver 50 generates pixel data pulses corresponding to the discharge cells G belonging to the (8N-7) th and (8N-4) th row electrodes Y based on the pixel drive data bit DB. These are applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronism with the scanning pulse. The column electrode driver 50 generates a pixel data pulse having a predetermined high voltage when a pixel driving data bit DB having a logic level 1 for switching the discharge cell to the extinguishing mode is supplied. When the pixel drive data bit DB is supplied, a low voltage (ground voltage) pixel data pulse is generated. At this time, the selective erasure address discharge is generated only in the discharge cells G to which the scan pulse is applied and the pixel data pulse having a high voltage is applied. By this selective erasure address discharge, the wall charges formed in the discharge cell G are erased, and the discharge cell G is set to the extinguishing mode. On the other hand, the selective erase address discharge as described above is not generated in the discharge cell G to which the pixel data pulse having a low voltage is applied although the scan pulse is applied. Therefore, the discharge cell G maintains the state (lighting mode or extinguishing mode) until just before that.

  Thus, in the address process W4, only the discharge cells G belonging to the (8N-7) th and (8N-4) th display lines from among the first to nth display lines in the PDP 100 are targeted. An address operation for selectively changing each discharge cell G from the lighting mode state to the extinguishing mode state is performed.

  Here, as shown in FIG. 5, in the first subfield in each of the subfield groups SG3 to SG5, that is, SF31, SF41, and SF51, driving based on the address process W1 is performed. In the second subfield in each of SG3 to SG5, that is, each of SF32, SF42, and SF52, driving based on the address process W2 is performed. In the third subfield in each of SG3 to SG5, that is, each of SF33, SF43, and SF53, driving based on the address process W3 is performed. Further, in the last subfield in each of SG3 to SG5, that is, each of SF34, SF44, and SF54, driving based on the address process W4 is performed.

  In addition, only in the head SG3 in each of the subfield groups SG3 to SG5, in the head subfield SF31 in the SG3, the address step W3 is performed following the address step W1. Further, only in the second subfield SF32 in SG3, the address process W4 is performed following the address process W2.

Then, in the last subfield SF6, the sustain process I and the erase process E are sequentially performed. In the erasing step E, the row electrode Y driver 70 applies an erasing pulse to each of the row electrodes Y _{1 to} Y _n , thereby erasing and discharging each of the discharge cells G in the lighting mode state to enter the extinguishing mode state. Transition.

  The panel driving unit drives the PDP 100 according to the light emission driving sequence to drive each discharge cell G to emit light in the form shown in each of the first to eighth gradations shown in FIG. 4 for each unit display period. .

  In other words, the panel drive unit determines that the luminance range that can be expressed by the input video signal is within the unit display period in accordance with the gradation pixel data MD that represents the eight stages (first to eighth gradations) as shown in FIG. The discharge cell G is subjected to selective erasure address discharge only in the address process of one subfield (indicated by black circles) in each subfield. According to the light emission drive sequence shown in FIG. 5, the opportunity to change the discharge cell from the extinguishing mode to the lighting mode in each subfield within the unit display period is the reset of the leading subfield SF0. It is only process R. Therefore, the discharge cell G that has transitioned to the off mode state in the address process (W0, W1, W2, W3, or W4) of one subfield within the unit display period returns to the on mode in the subsequent subfields. There is nothing. Therefore, the discharge cell G maintains the lighting mode state in each of the subfields continuous from the head until the transition to the extinguishing mode in the address process of the subfield indicated by the black circle in FIG. In the sustain process I, sustain discharge is performed (indicated by white circles). At this time, an intermediate luminance corresponding to the total number of sustain discharges generated in each sustain process I in the unit display period is visually recognized.

  For example, in the first gradation drive that is performed when the gradation pixel data MD is [0000] representing the lowest luminance level, the panel drive unit performs the discharge cell G only in the first subfield SF0 as shown in FIG. Are selectively erased and discharged (indicated by black circles), and the discharge cells G are shifted to the extinguishing mode. Therefore, according to the driving of the first gradation, since no sustain discharge is generated in the unit display period, the lowest luminance level 0 responsible for black display is expressed.

  Further, in the second gradation drive performed when the gradation pixel data MD is [0001] representing a luminance higher than [0000] by one step, the panel drive unit performs subfield SF1 within the unit display period. Only the discharge cell G is subjected to selective erasure address discharge (indicated by a double black circle), and the discharge cell G is shifted to the extinguishing mode. Therefore, according to the driving of the second gradation, the sustain discharge is generated only in the sustain process I of the subfield SF1 within the unit display period. At this time, a luminance level “2” corresponding to the number of sustain discharges generated in SF1 is expressed.

  In the third gradation drive that is performed when the gradation pixel data MD is [0010], which represents one level higher than the above [0001], the panel drive unit performs subfields within the display period. The discharge cell G is subjected to selective erasure address discharge only by SF2 (indicated by a double black circle), and the discharge cell G is shifted to the extinguishing mode. Therefore, according to the driving of the third gradation, the sustain discharge is generated only in the sustain process I of each of the subfields SF1 and SF2 within the unit display period. At this time, a luminance level “4” corresponding to the total number of sustain discharges generated in SF1 and SF2 is expressed.

  Here, in each of the first to third gradations expressing lower luminance than the predetermined luminance level, the panel driving unit assigns the same luminance weight to all the display lines and each discharge cell belonging to each display line. Are emitted at the same luminance level corresponding to the gradation.

On the other hand, in each of the fourth to seventh gradations expressing higher brightness than the predetermined brightness level, eight adjacent display lines, that is,
(8N-7) display line: 1st, 9th, 17th, ..., (n-7) display line (8N-6) display line: 2nd, 10th, 18th, ... ..., (n-6) display line (8N-5) display line: 3rd, 11th, 19th, ..., (n-5) display line (8N-4) display line: No. 4th, 12th, 20th, ..., (n-4) display line (8N-3) display line: 5th, 13th, 21st, ..., (n-3) display line (8N-2) display line: 6th, 14th, 22nd, ..., (n-2) display line (8N-1) display line: 7th, 15th, 23rd, ... -(N-1) display line (8N) display line: By assigning the following luminance weights to the 8th, 16th, 24th, ..., (n) display lines Then, so-called line dither driving is performed in which each discharge cell G belonging to each display line emits light at a different luminance level.

  In such line dither driving, the number of subfields (indicated by white circles) in which the discharge cells G belonging to the display line are to be sustain-discharged (the number within the unit display period) is different for each display line. .

  For example, as shown in FIG. 4, in the fourth gradation driving according to the gradation pixel data MD [0011], the panel driving unit performs (8N-6), (8N-5), (8N) -2) and the discharge cells belonging to the (8N-1) th display line are subjected to selective erasure address discharge only by the subfield SF31 (indicated by double black circles). For the discharge cells belonging to the (8N-7) th, (8N-4), (8N-3) and (8N) display lines, the panel driver discharges only in the subfield SF32. The cell G is subjected to selective erase address discharge (indicated by a double black circle). As a result, the discharge cells belonging to the (8N-6) th, (8N-5), (8N-2) and (8N-1) display lines are connected to the subfields SF1, SF2 and A sustain discharge is generated only in the sustain process I of each SF31. On the other hand, the discharge cells belonging to the (8N-7) th, (8N-4), (8N-3), and (8N) display lines are subfields SF1, SF2, SF31, and SF32 within the unit display period. A sustain discharge is generated only in each sustain process I.

Therefore, according to the fourth gradation drive, according to the total number of sustain discharges generated in the unit display period,
The discharge cells belonging to the (8N-7) th display line have a luminance level of “8”,
The discharge cells belonging to the (8N-6) th display line have a luminance level of “6”,
The discharge cells belonging to the (8N-5) th display line have a luminance level of “6”,
The discharge cells belonging to the (8N-4) th display line have a luminance level of “8”,
The discharge cells belonging to the (8N-3) th display line have a luminance level of “8”,
The discharge cells belonging to the (8N-2) th display line have a luminance level of “6”,
The discharge cells belonging to the (8N-1) th display line have a luminance level of “6”,
The discharge cells belonging to the (8N) th display line have a luminance level of “8”,
Each emits light.

  In other words, in the fourth gradation drive, two stages of luminance weights are assigned to each of the eight adjacent display lines, and the discharge cells belonging to the display line are driven. At this time, the luminance difference between the luminance level “8” corresponding to the maximum luminance weight and the luminance level “6” corresponding to the minimum luminance weight is “2”.

  Next, in the fifth gradation drive corresponding to the gradation pixel data MD of [0100] representing the brightness higher by one step than [0011], the panel drive unit performs the (8N-7) and (8N) -4) Selective erasure address discharge is caused in SF34 to the discharge cells belonging to the display line (indicated by double black circles). As a result, the discharge cells belonging to the (8N-7) th and (8N-4) th display lines continuously sustain in the subfields SF1, SF2, and SF31 to SF34. In the fifth gradation driving, the panel driving unit causes selective erasure address discharge in SF33 for the discharge cells belonging to the (8N-6) th and (8N-1) th display lines ( (Indicated by double black circles). As a result, the discharge cells belonging to the (8N-6) th and (8N-1) th display lines are continuously sustain-discharged in each of the subfields SF1, SF2, SF31 to SF33. In the fifth gradation drive, the panel driver generates a selective erase address discharge in SF41 for the discharge cells belonging to the (8N-5) th and (8N-2) th display lines ( (Indicated by double black circles). As a result, the discharge cells belonging to the (8N-5) th and (8N-2) th display lines continuously sustain in subfields SF1, SF2, SF31 to SF34, and SF41, respectively. In the fifth gradation drive, the panel drive unit causes the selective erase address discharge to occur in SF42 for the discharge cells belonging to the (8N-3) th and (8N) display lines (double). (Indicated by a black circle). As a result, the discharge cells belonging to the (8N-3) th and (8N) th display lines continuously sustain in the subfields SF1, SF2, SF31 to SF34, SF41, and SF42.

Therefore, according to the fifth gradation drive, according to the total number of sustain discharges generated within the unit display period,
The discharge cells belonging to the (8N-7) th display line have a luminance level of “12”,
The discharge cells belonging to the (8N-6) th display line have luminance level “10”,
The discharge cells belonging to the (8N-5) th display line have a luminance level of “14”,
The discharge cells belonging to the (8N-4) th display line have a luminance level of “12”,
The discharge cells belonging to the (8N-3) th display line have a luminance level of “16”,
The discharge cells belonging to the (8N-2) th display line have a luminance level of “14”,
The discharge cells belonging to the (8N-1) th display line have a luminance level of “10”,
The discharge cells belonging to the (8N) th display line have a luminance level of “16”,
Each emits light.

  In other words, in the fifth gradation drive, four levels of luminance weights are assigned to each of the eight adjacent display lines, and the discharge cells belonging to the display line are driven. At this time, the luminance difference between the luminance level “16” corresponding to the maximum luminance weight and the luminance level “10” corresponding to the minimum luminance weight is “6”.

  Next, in the driving of the sixth gradation corresponding to the gradation pixel data MD of [0101] representing the brightness higher than [0100] by one step, the panel driving unit performs the (8N-7) and (8N) -4) Selective erasure address discharge is caused in SF44 to the discharge cells belonging to the display line (indicated by double black circles). As a result, the discharge cells belonging to the (8N-7) th and (8N-4) th display lines continuously sustain in the subfields SF1, SF2, SF31 to SF34, and SF41 to SF44. In the sixth gradation drive, the panel driver generates a selective erase address discharge in SF43 for the discharge cells belonging to the (8N-6) th and (8N-1) th display lines ( (Indicated by double black circles). As a result, the discharge cells belonging to the (8N-6) th and (8N-1) th display lines continuously sustain in the subfields SF1, SF2, SF31 to SF34, and SF41 to SF43. In the sixth gradation driving, the panel driving unit causes the selective erasure address discharge in SF51 for the discharge cells belonging to the (8N-5) th and (8N-2) th display lines ( (Indicated by double black circles). As a result, the discharge cells belonging to the (8N-5) th and (8N-2) th display lines continuously sustain in subfields SF1, SF2, SF31 to SF34, SF41 to SF44, and SF51, respectively. . In the sixth gradation drive, the panel drive unit causes the selective erase address discharge to occur in SF52 for the discharge cells belonging to the (8N-3) th and (8N) display lines (double). (Indicated by a black circle). As a result, the discharge cells belonging to the (8N-3) th and (8N) th display lines continuously sustain in the subfields SF1, SF2, SF31 to SF34, SF41 to SF44, SF51 and SF52, respectively. .

Therefore, according to the sixth gradation drive, according to the total number of sustain discharges generated in the unit display period,
The discharge cells belonging to the (8N-7) th display line have a luminance level of “20”,
The discharge cells belonging to the (8N-6) th display line have a luminance level of “18”,
The discharge cells belonging to the (8N-5) th display line have a luminance level of “22”,
The discharge cells belonging to the (8N-4) th display line have a luminance level of “20”,
The discharge cells belonging to the (8N-3) th display line have a luminance level of “24”,
The discharge cells belonging to the (8N-2) th display line have a luminance level of “22”,
The discharge cells belonging to the (8N-1) th display line have a luminance level of “18”,
The discharge cells belonging to the (8N) th display line have a luminance level of “24”,
Each emits light.

  In other words, in the sixth gradation drive, four stages of luminance weights are assigned to each of the eight adjacent display lines, and the discharge cells belonging to the display line are driven. At this time, the luminance difference between the luminance level “24” corresponding to the maximum luminance weight and the luminance level “18” corresponding to the minimum luminance weight is “6”.

  Next, in the driving of the seventh gradation corresponding to the gradation pixel data MD of [0110] representing the brightness higher by one step than [0101], the panel driving unit performs the (8N-7) and (8N) -4) Selective erasure address discharge is generated in SF54 for the discharge cells belonging to the display line (indicated by double black circles). As a result, the discharge cells belonging to the (8N-7) th and (8N-4) th display lines are continuously sustain-discharged in each of the subfields SF1, SF2, SF31 to SF34, SF41 to SF44, and SF51 to SF54. become. In the seventh gradation driving, the panel driving unit causes selective erasure address discharge in SF53 for the discharge cells belonging to the (8N-6) th and (8N-1) display lines ( (Indicated by double black circles). As a result, the discharge cells belonging to the (8N-6) th and (8N-1) th display lines are continuously sustain-discharged in each of the subfields SF1, SF2, SF31 to SF34, SF41 to SF44, and SF51 to SF53. become. In the seventh gradation drive, for the discharge cells belonging to the (8N-5) th, (8N-3), (8N-2) and (8N) display lines, the panel driver is In the unit display period, no selective erasure address discharge is performed. Accordingly, the discharge cells belonging to the (8N-5) th, (8N-3), (8N-2) and (8N) display lines are subfields SF1, SF2, SF31 to SF34, SF41 to SF44, In each of SF51 to SF54 and SF6, sustain discharge is continuously performed.

Therefore, according to the driving of the seventh gradation, according to the total number of sustain discharges generated within the unit display period,
The discharge cells belonging to the (8N-7) th display line have a luminance level of “28”,
The discharge cells belonging to the (8N-6) th display line have a luminance level of “26”,
The discharge cells belonging to the (8N-5) th display line have a luminance level of “30”,
The discharge cells belonging to the (8N-4) th display line have a luminance level of “28”,
The discharge cells belonging to the (8N-3) th display line have a luminance level of “30”,
The discharge cells belonging to the (8N-2) th display line have a luminance level of “30”,
The discharge cells belonging to the (8N-1) th display line have a luminance level of “26”,
The discharge cells belonging to the (8N) th display line have a luminance level of “30”,
Each emits light.

  That is, in the drive of the seventh gradation, three levels of luminance weights are assigned to each of the eight adjacent display lines, and the discharge cells belonging to the display line are driven. At this time, the luminance difference between the luminance level “30” corresponding to the maximum luminance weight and the luminance level “26” corresponding to the minimum luminance weight is “4”.

  In the eighth gradation drive according to the gradation pixel data MD of [0111] representing the maximum luminance, the panel drive unit does not perform any selective erase address discharge within the unit display period for all discharge cells. . As a result, the discharge cells continuously sustain in subfields SF1, SF2, SF31 to SF34, SF41 to SF44, SF51 to SF54, and SF6.

  Therefore, according to the eighth gradation drive, all the discharge cells G emit light at the luminance level “30” regardless of the display line to which the discharge cells G belong.

  As described above, in the plasma display device shown in FIG. 2, among the gradations for which line dither driving is performed, in each of the fifth and sixth gradations as shown in FIG. Are assigned to each display line, and the discharge cells belonging to that display line are driven to emit light at different brightness levels. At this time, the luminance difference between the luminance level corresponding to the maximum luminance weight and the luminance level corresponding to the minimum luminance weight is “6”. Further, the luminance difference for each display line between the fifth and sixth gradations is all “8” as shown in FIG. 6A, and there is no variation.

  On the other hand, among the gradations (fourth to seventh gradations) for which line dither driving is performed, in the gradation representing the lowest luminance, that is, the fourth gradation, there are two stages for each of the eight adjacent display lines. A luminance weight is assigned to drive the discharge cells belonging to the display line. At this time, line dither driving is not performed in the third gradation that represents a lower luminance by one level than the fourth gradation, and therefore, the ratio between the third gradation and the fourth gradation is different between the other gradations. As a result, the variation in luminance difference for each display line becomes large.

  Therefore, in the fourth gradation, when the luminance weight is assigned to each of the eight adjacent display lines for driving, the luminance difference between the luminance level corresponding to the maximum luminance weight and the luminance level corresponding to the minimum luminance weight is obtained. As described above, the luminance difference “2” is smaller than the luminance difference “6” at the fifth or sixth gradation. Thus, the luminance difference for each display line between the third and fourth gradations is (8N-7), (8N-4), (8N-3) as shown in FIG. 6B. And the (8N) display line is "4", the (8N-6), (8N-5), (8N-2) and (8N-1) display lines are "2", and the variation width Becomes “2”.

  That is, in the fourth gradation, the luminance difference between the luminance level corresponding to the maximum luminance weight to be assigned to each display line and the luminance level corresponding to the minimum luminance weight is compared with the fifth or sixth gradation as described above. By making it smaller, the variation in luminance difference for each display line is reduced.

  Therefore, among the gradations (fourth to seventh gradations) for which line dither driving is performed, the gradation that expresses the lowest luminance (fourth gradation) and the gradation (fourth gradation). The luminance difference for each display line between the gradations (third gradation) that represents low luminance only by one level and does not perform line dither driving is relatively small.

  Therefore, even when a low-brightness image is displayed, it is easy to form a dither pattern that represents the brightness value indicated by the input video signal, and a high-quality image can be provided.

It is a figure which shows an example of the light emission drive pattern at the time of implementing line dither drive. It is a figure which shows the structure of the plasma display apparatus which drives the plasma display panel as a display panel. It is a figure which shows an example of the line offset data produced | generated in the line offset data production | generation circuit 210. FIG. It is a figure which shows the light emission drive pattern for every gradation implemented in the plasma display apparatus shown by FIG. It is a figure which shows an example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. The luminance difference for each display line between the fifth and sixth gradations for which line dither driving is performed, and the display line between the third gradation for not performing line dither driving and the fourth gradation for performing line dither driving. It is a figure which shows the brightness | luminance difference for every.

Explanation of symbols

60 drive control circuit 100 PDP
210 Line offset data generation circuit

Claims (6)

The display cells arranged in each display line of the display panel correspond to the luminance level indicated by the video signal in each of the first to Mth gradations (M: an integer of 2 or more) expressing different luminance levels. A method of driving a display panel that emits light at a luminance level corresponding to one gradation,
In each of the first to Mth gradations, a gradation representing a luminance higher than a predetermined luminance level, a luminance weight is assigned to each display line in the display line group for each display line group including a plurality of adjacent display lines. And performing line dither driving for causing the display cells belonging to each display line to emit light at different luminance levels for each display line based on the luminance weight,
Among the gradations representing the brightness higher than the predetermined brightness level, the gradation representing the lowest brightness in the display cell belonging to the display line to which the maximum brightness weight is assigned as compared with the other gradations. A difference in luminance between a luminance level at the time of light emission operation performed and a luminance level at the time of light emission operation performed by a display cell belonging to the display line to which the minimum luminance weight is assigned is small. Driving method of display panel.   Among the first to M-th gradations, the gradations representing lower brightness than the predetermined brightness level are assigned to the respective display lines by assigning the same brightness weight to each display line in the display line group. 2. The display panel driving method according to claim 1, wherein each display cell emits light at a luminance level of 1 corresponding to the gradation. Display in which a display panel in which a plurality of display cells bearing pixels are arranged in each display line is gray-scale driven for each of a plurality of subfields within a unit display period according to pixel data corresponding to each pixel based on a video signal A panel driving method,
In each of the subfields, a sustain process in which only the display cells in the lighting mode are repeatedly emitted for the number of times assigned to the subfield, and each of the display cells is selectively selected according to the pixel data. An address process for performing an erase address operation to be changed from the lighting mode state to the extinguishing mode state,
In the address process of each of the subfields belonging to one subfield group among each of the subfield groups composed of W (W: an integer of 2 or more) subfields continuously arranged in the unit display period. , Performing the erase address operation only on display cells belonging to one display line group among first to Wth display line groups different from each other,
In the address process of at least one subfield of each of the subfields belonging to the one subfield group, the display belonging to at least one display line group different from the one display line group together with the one display line group A method of driving a display panel, wherein the erase address operation is executed also for a cell. Within the unit display period, the display cell is transitioned from the extinguishing mode state to the lighting mode state only in the top subfield.
The lighting mode state is maintained until the display cell is changed from the lighting mode state to the extinguishing mode state in the address process of one subfield within the unit display period. The method for driving a display panel according to claim 3. In the unit display period, in the address process of the subfield arranged immediately before the one subfield group, the erase address operation is performed on all display cells,
In the address process of the first subfield of each subfield belonging to the one subfield group, display cells belonging to a display line group different from the one display line group together with the one display line group are also targeted. 4. The method of driving a display panel according to claim 3, wherein an erase address operation is executed.   4. The display line group consisting of W display lines adjacent to each other includes display lines belonging to the one display line group and a display line group different from the one display line group, respectively. A driving method of the display panel according to 1.

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