JP2008294479A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a back irradiation type solid-state imaging apparatus that can be improved in quantum efficiency by suppressing the occurrence of a dark current by suppressing the occurrence of crystal defects caused by metallic contamination during a process. <P>SOLUTION: The apparatus has a wiring layer 36 formed on a first surface of a p-type epitaxial layer 10, an n-type region 12 which is formed on the p-type epitaxial layer 10, and stores electric charges generated by photoelectric conversion, and a p<SP>+</SP>-type impurity layer 11 which is formed on a second surface side of the p-type epitaxial layer 10 rather than the n-type region 12, and has an impurity concentration higher than that of the p-type epitaxial layer 10. The device receives light from the second surface side of the p-type epitaxial layer 10. An impurity concentration of the p<SP>+</SP>-type impurity layer 11 has a gradient with a higher concentration toward the second surface side, and becomes the maximum concentration at a position on the second surface. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a back-illuminated solid-state imaging device that receives light from a side opposite to a side on which a wiring layer is formed.

  In recent years, from the viewpoint of improving the aperture ratio for light reception and improving the flexibility of the layout of the wiring layer, a wiring layer can be formed on the front side of the semiconductor layer, and light can be incident from the back side of the semiconductor layer so that imaging can be performed. There has been known a back-illuminated fixed imaging device. As back-illuminated solid-state imaging devices, a CCD type (for example, see Patent Document 1) and a MOS type (for example, see Patent Document 2) have been proposed.

In the manufacturing process of a back-illuminated solid-state imaging device, when a metal enters a semiconductor layer in which a light receiving portion or the like is formed, a crystal defect caused by the metal occurs, and an image defect called a white scratch is generated by the crystal defect. End up. In order to suppress this image defect, it is necessary to consider how to getter the metal that has penetrated into the semiconductor layer during the manufacturing process of the back-illuminated solid-state imaging device. A gettering layer for gettering metal is usually formed outside the active region of the semiconductor layer.
JP 2002-151673 A JP 2003-31785 A

  However, in the manufacturing process of the back-illuminated solid-state imaging device, the formation of the gettering layer is restricted. For example, when a back-illuminated solid-state imaging device is formed using a silicon layer of an SOI substrate, even if a gettering layer is formed on a silicon substrate facing the silicon layer with the silicon oxide layer interposed therebetween, the oxidation is performed. The silicon layer becomes a barrier, and the metal that enters the silicon layer cannot be gettered.

  On the other hand, it is also important to suppress the occurrence of dark current due to depletion of the interface that becomes the light incident surface (back surface) of the semiconductor layer and the decrease in sensitivity. For this reason, it is necessary to consider a process for increasing the majority carrier concentration at the interface position of the semiconductor layer.

  An object of the present invention is to provide a solid-state imaging device capable of suppressing generation of dark current and improving quantum efficiency.

  In order to achieve the above object, a solid-state imaging device according to the present invention stores a wiring layer formed on a first surface of a first conductivity type epitaxial layer and charges generated by photoelectric conversion formed on the epitaxial layer. And a first conductivity type impurity layer formed on the second surface side of the epitaxial layer than the second conductivity type region and having a higher impurity concentration than the epitaxial layer, Light is received from the second surface side of the epitaxial layer, and the impurity concentration of the first conductivity type impurity layer has a concentration gradient that increases toward the second surface side, and reaches the maximum concentration at the position of the second surface. It is specified as follows.

  Preferably, the thickness of the epitaxial layer is 4 μm to 10 μm.

  Preferably, a first conductivity type region is further formed on the surface layer of the first surface of the epitaxial layer.

  Preferably, a substrate having a thermal expansion coefficient different from that of the epitaxial layer is formed on the first surface side of the epitaxial layer.

In the above-described solid-state imaging device of the present invention, the first conductivity type impurity layer formed in the epitaxial layer has a concentration gradient in which the impurity concentration becomes higher toward the second surface side, and is maximum at the position of the second surface. It is specified to be a concentration.
By having the above-described concentration gradient, an electric field is generated so that the charges generated in the epitaxial layer move to the second conductivity type region, so that the charges are effectively accumulated in the second conductivity type region.
Further, since the maximum concentration is obtained at the position of the second surface, formation of a potential well at the position of the second surface is prevented, and charges generated in the epitaxial layer are trapped at the interface (second surface) position. Is prevented.

  According to the solid-state imaging device of the present invention, generation of dark current can be suppressed and quantum efficiency can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, an example will be described in which electrons are used as signal charges, the first conductivity type is p-type, and the second conductivity type is n-type. When holes are used as signal charges, the above polarities may be reversed.

  FIG. 1 is a cross-sectional view of the solid-state imaging device according to the present embodiment. In this embodiment, a MOS type solid-state imaging device called a CMOS image sensor will be described.

In the present embodiment, a silicon p-type epitaxial layer 10 is used as a substrate. The thickness of the p-type epitaxial layer 10 depends on the specifications of the solid-state imaging device, but is 4 to 6 μm for visible light and 6 to 10 μm for near infrared. In addition, the p-type impurity concentration (acceptor concentration) of the p-type epitaxial layer 10 is about 1 × 10 ¹⁴ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ , depending on the specifications of the solid-state imaging device.

  A wiring layer 36 is formed on the first surface (front surface) of the p-type epitaxial layer 10 described above, and the solid-state imaging device according to the present embodiment has a second side opposite to the side on which the wiring layer 36 is formed. It is configured to receive light from two sides (back side). That is, a back-illuminated solid-state imaging device is configured.

A p ⁺ -type impurity layer (first conductivity type impurity layer) 11 containing a p-type impurity at a higher concentration than the p-type epitaxial layer 10 is formed on the surface layer of the second surface of the p-type epitaxial layer 10. As will be described later, the p ⁺ -type impurity layer 11 suppresses the generation of dark current and improves the quantum efficiency.

  In the p-type epitaxial layer 10, an n-type region 12 is formed for each pixel. Light incident on the p-type epitaxial layer 10 is photoelectrically converted by a photodiode centered on a pn junction between the p-type epitaxial layer 10 and the n-type region 12 and accumulated in the n-type region 12.

A p ⁺ type region 13 for forming a buried photodiode is formed on the n type region 12, that is, on the surface layer of the first surface of the p type epitaxial layer 10. The p ⁺ type region 13 is p ⁺
It has the same function as the type impurity layer 11.

  An n-type region 14 and an n-type region 15 are formed on the first surface side of the p-type epitaxial layer 10. The n-type region 14 becomes a floating diffusion. The n-type region 15 becomes the source or drain of a transistor other than the transfer transistor. A p-type region 16 that partitions the pixel region is formed on the first surface side of the p-type epitaxial layer 10 in order to prevent signal charges from leaking to adjacent pixels.

  A gate electrode 32 of a transfer transistor and a gate electrode 33 of a transistor other than the transfer transistor are formed on the first surface of the p-type epitaxial layer 10 via a gate insulating film 31. In FIG. 1, one transistor other than the transfer transistor is shown, but the number is not limited.

  A wiring layer 36 in which a wiring 34 and an interlayer insulating film 35 are laminated is formed on the first surface of the p-type epitaxial layer 10 so as to cover a transistor or the like. The wiring 34 is made of, for example, aluminum, and the interlayer insulating film 35 is made of, for example, silicon oxide. In FIG. 1, a two-layer wiring is illustrated, but a three-layer wiring or a four-layer wiring may be used.

  A support substrate 40 for increasing the strength of the p-type epitaxial layer 10 is formed on the wiring layer 36. The support substrate 40 is preferably formed of silicon in order to prevent warpage due to a difference in thermal expansion coefficient from that of the p-type epitaxial layer 10, but quartz glass may be used. However, if the strength of the p-type epitaxial layer 10 can be ensured, the support substrate 40 need not be provided.

  A passivation film 51 made of silicon nitride is formed on the second surface side of the p-type epitaxial layer 10 via a silicon oxide film (not shown). A color filter 52 is formed on the passivation film 51, and an on-chip lens 53 is formed on the color filter 52. Although not shown, a light shielding film that opens each pixel may be provided between the silicon oxide film (not shown) and the passivation film 51.

  In the solid-state imaging device, light incident from the second surface (back surface) side of the p-type epitaxial layer 10 enters the p-type epitaxial layer 10 via the on-chip lens 53 and the color filter 52. Electrons generated in the p-type epitaxial layer 10 by the incidence of light are accumulated in the n-type region 12 without being trapped near the interface (second surface).

  When a voltage is applied to the gate electrode 32 and the transfer transistor is turned on, the electrons accumulated in the n-type region 12 are transferred to the n-type region 14 serving as a floating diffusion. Although not shown, the n-type region 14 is connected to the gate electrode of the amplification transistor, and the potential of the n-type region 14 is amplified by the amplification transistor and output.

  After reading, the potential of the n-type region 14 that becomes floating diffusion is reset to the power supply potential, that is, electrons accumulated in the n-type region 14 are discharged.

FIG. 2 is a schematic diagram showing a potential (potential) from the second surface of the p-type epitaxial layer 10 to the p ⁺ -type region 13.

The potential increases in the depth direction from the second surface of the p-type epitaxial layer 10 toward the p ⁺ -type impurity layer 11, the p-type epitaxial layer 10, and the n-type region 12. The potential decreases again from the n-type region 12 to the p ⁺ -type region 13.

  In the present embodiment, no potential well is formed in the surface layer of the second surface of the p-type epitaxial layer 10. If a potential well is formed in the surface layer of the second surface, electrons generated by photoelectric conversion are also accumulated in this surface layer portion. The electrons accumulated in this portion are difficult to read out or discharge completely, causing dark current and leading to a decrease in quantum efficiency.

  In this embodiment, since a potential well (a portion having a high potential) is not formed on the surface layer of the second surface of the p-type epitaxial layer 10, electrons generated by photoelectric conversion are the n-type having the highest potential. It is effectively accumulated in the area 12. Since electrons accumulated in the n-type region 12 can be completely read out or discharged, generation of dark current can be suppressed and quantum efficiency can be improved.

For potential distribution shown in FIG. 2, the surface layer of the second surface, as compared with the p-type epitaxial layer 10 high-concentration p ⁺ -type impurity layer 11 is formed, and the impurity concentration of the p ⁺ -type impurity layer 11 Is formed so as to have the maximum density at the position of the second surface.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

As shown in FIG. 3A, carbon ions are implanted into the substrate 20 to form a gettering layer 21 at a predetermined depth from the surface of the substrate 20. The substrate 20 is a single crystal silicon substrate formed by, for example, the Czochralski (CZ) method. Before this ion implantation, a silicon oxide film may be formed as a contamination prevention film for preventing contamination and channeling due to ion implantation. The substrate 20 is a p-type substrate in an element that handles electrons as a signal. The amount of carbon to be implanted is about 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² where a gettering effect can be expected. Further, it is necessary to form the gettering layer 21 relatively deeply so that the gettering layer 21 is not formed on the surface of the substrate 20. For example, ion implantation is performed with relatively high energy of about 100 keV to 300 keV. The reason why the gettering layer 21 is formed deep is to ensure good crystallinity of the p-type epitaxial layer 10 to be formed later.

Next, as shown in FIG. 3B, a p ⁺ -type impurity layer 22 is formed on the substrate surface side of the gettering layer 21 by ion-implanting p-type impurities such as boron into the substrate 20.

  When the contamination prevention film is formed on the surface of the substrate 20, after removing the contamination prevention film, the p-type epitaxial layer 10 is formed by an epitaxial growth method as shown in FIG. As described above, the thickness and p-type impurity concentration of the p-type epitaxial layer 10 are determined by the specifications of the solid-state imaging device. Note that heat treatment (annealing) for improving the crystallinity of the surface of the substrate 20 may be performed before the step of forming the p-type epitaxial layer 10. This is because the crystallinity of the substrate 20 is deteriorated due to carbon implantation or the like, so that the crystallinity of the p-type epitaxial layer 10 formed on the substrate 20 is improved by improving the crystallinity of the substrate 20 by heat treatment. Because it does.

Since the p ⁺ -type impurity layer 22 is formed on the surface of the substrate 20, from the interface between the p-type epitaxial layer 10 and the substrate 20, the p-type impurity in the p ⁺ -type impurity layer 22 into the p-type epitaxial layer 10 side Spread. Thereby, a p ⁺ -type impurity layer 11 containing a p-type impurity at a higher concentration than the p-type epitaxial layer 10 is formed from the interface to a predetermined depth. The p ⁺ -type impurity layer 11 formed in this way has a concentration gradient such that the impurity concentration increases toward the p ⁺ -type impurity layer 22 serving as a p-type impurity supply source. The p ⁺ type impurity layers 11 and 22 formed on the substrate 20 and the p type epitaxial layer 10 so as to straddle the interface between the substrate 20 and the p type epitaxial layer 10 correspond to the first conductivity type impurity layer of the present invention. To do.

Next, as shown in FIG. 4A, a circuit is formed in the p-type epitaxial layer 10. For example, an n-type region 12 serving as a photodiode, a p ⁺ -type region 13, an n-type region 14 serving as a floating diffusion, and an n-type region 15 serving as a source or drain of a transistor are formed. Further, a gate insulating film 31 is formed on the p-type epitaxial layer 10 by a thermal oxidation method, and gate electrodes 32 and 33 of transistors are further formed. Note that the order of forming these can be changed as appropriate. For example, the n-type region 14 and the n-type region 15 may be formed after the gate electrodes 32 and 33 are formed.

  Next, as shown in FIG. 4B, a wiring layer 36 is formed on the p-type epitaxial layer 10 so as to cover the transistor. In the formation of the wiring layer 36, multilayer wiring is formed by repeating the formation of the wiring 34 and the formation of the interlayer insulating film 35.

  Next, as shown in FIG. 5A, a support substrate 40 made of, for example, silicon is formed on the wiring layer 36. The support substrate 40 may be formed by pouring silicon onto the wiring layer 36 or a silicon substrate may be attached.

Next, as shown in FIG. 5B, the substrate 20 is removed. The thickness of the substrate 20 is about 600 to 800 μm. Therefore, first, after removing about several hundred μm using a grinder, the remaining several tens of μm film is removed by wet etching. At this time, the substrate 20 including the gettering layer 21 and the p ⁺ -type impurity layer 22 is removed from the back surface side, and further, the surface layer of the p ⁺ -type impurity layer 11 so that the removal interface enters the p ⁺ -type impurity layer 11. Is also removed. For example, wet etching is performed using a mixed solution of hydrofluoric acid (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH) while monitoring the film thickness.

  FIG. 6 is a schematic diagram showing the p-type impurity concentration in the depth direction with the exposed surface of the substrate 20 as the reference position (0).

As shown in FIG. 6, the p ⁺ -type impurity layer 22 for the high-concentration p-type impurity is introduced, the maximum concentration of the p-type impurity in the region of p ⁺ -type impurity layer 22. As described above, the p ⁺ -type impurity layer 11 formed by diffusing the p-type impurity from the p ⁺ -type impurity layer 22 has a p-type impurity as it goes from the p-type epitaxial layer 10 side to the p ⁺ -type impurity layer 22 side. It has a concentration gradient that increases the concentration. Although not as large as p ⁺ -type impurity layer 11, p-type impurities in p ⁺ -type impurity layer 22 are also diffused in gettering layer 21.

From the back side, to remove the substrate 20 including the gettering layer 21 and the p ⁺ -type impurity layer 22, by further removing the interface so that enters the p ⁺ -type impurity layer 11, the remaining p ⁺ -type impurity layer 11 is The p-type impurity concentration has a concentration gradient that increases toward the removal interface, and the maximum concentration is obtained at the removal interface. Further, since the interface between the p ⁺ -type impurity layer 22 and the p ⁺ -type impurity layer 11, that is, the interface between the substrate 20 and the p-type epitaxial layer 10 is poor in crystallinity, the removal interface is allowed to enter the p ⁺ -type impurity layer 11. Is preferred.

  As the subsequent steps, the passivation film 51 is formed on the p-type epitaxial layer 10, the color filter 52 is formed, and the on-chip lens 53 is formed, whereby the solid-state imaging device shown in FIG.

  As described above, in the method for manufacturing the solid-state imaging device according to the present embodiment, the gettering layer 21 formed in the vicinity of the light incident surface of the p-type epitaxial layer 10 exists until the substrate 20 is removed. Therefore, in the process of forming the semiconductor region in the p-type epitaxial layer 10 and the wiring layer forming process shown in FIGS. It can be captured and the generation of crystal defects due to metal contamination can be suppressed.

  Therefore, it is possible to manufacture a solid-state imaging device with little dark current and white scratches. Further, since the gettering layer 21 is removed from the manufactured solid-state imaging device, it is not affected by the dark current from the gettering layer 21 having poor crystallinity.

Further, by selecting conditions such as temperature and growth rate when the p-type epitaxial layer 10 is formed, the p ⁺ -type impurity layer 11 having a desired concentration gradient can be formed. By having a concentration gradient, electrons generated by photoelectric conversion are effectively accumulated in the n-type region 12, so that a solid-state imaging device with high quantum efficiency can be manufactured.

  Further, since a structure in which the concentration of the p-type impurity is maximized can be produced at the position of the interface (second surface) of the p-type epitaxial layer 10, the generation of dark current near the interface can be suppressed.

The present invention is not limited to the description of the above embodiment.
In the present embodiment, a MOS type solid-state imaging device called a CMOS image sensor has been described, but the present invention can also be applied to a CCD type solid-state imaging device. For the formation of the gettering layer 21, impurities other than carbon may be ion-implanted, for example, phosphorus may be ion-implanted. Further, the p ⁺ -type impurity layer 22 may be formed before the gettering layer 21 is formed.

When the p-type epitaxial layer 10 is formed in multiple stages, the p ⁺ -type impurity layer 22 may be formed during the formation of the p-type epitaxial layer 10. In this case, after the p ⁺ -type impurity layer 22 is formed, the p-type epitaxial layer 10 is formed again (temperature is about 1100 ° C.). Therefore, the p type impurity in the p ⁺ type impurity layer 22 is diffused into the p type epitaxial layer 10 to form the p ⁺ type impurity layer 11. In this way, two or more thermal histories are applied during the formation of the p-type epitaxial layer 10, so that crystal defects in the gettering layer 21 further grow and the gettering capability can be improved.

Further, the p ⁺ -type impurity layer 22 may be formed after the p-type epitaxial layer 10 is formed. In this case, for example, after the p ⁺ -type impurity layer 22 is formed, an annealing process for improving the crystallinity of the p-type epitaxial layer 10 is performed, so that the p-type impurity in the p ⁺ -type impurity layer 22 is p. The p ⁺ type impurity layer 11 is formed by diffusing into the type epitaxial layer 10.

In the present embodiment, the p-type epitaxial layer 10 is used. However, when holes are used as signal charges, for example, the n-type epitaxial layer 10 can also be used. In this case, for example, the polarities of various impurity regions may be reversed. For example, the p ⁺ -type impurity layer 11 becomes an n ⁺ impurity layer.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing of the solid-state imaging device concerning this embodiment. It is a schematic diagram showing a potential (potential) from the second surface of the p-type epitaxial layer to the p ⁺ -type region. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is a schematic diagram which shows the p-type impurity density | concentration in the depth direction which made the exposed surface of the board | substrate 20 the reference position (0).

Explanation of symbols

10 ... p-type epitaxial layer, 11 ... p ⁺ type impurity layer, 12 ... n-type region, 13 ... p ⁺ -type region, 14 ... n-type region, 15 ... n-type region, 16 ... p-type region, 20 ... substrate, DESCRIPTION OF SYMBOLS 21 ... Gettering layer, 22 ... p ^<+> type impurity layer, 31 ... Gate insulating film, 32 ... Gate electrode, 33 ... Gate electrode, 34 ... Wiring, 35 ... Interlayer insulating film, 36 ... Wiring layer, 40 ... Support substrate, 51 ... Passivation film, 52 ... Color filter, 53 ... On-chip lens

Claims (4)

A wiring layer formed on the first surface of the first conductivity type epitaxial layer;
A second conductivity type region that is formed in the epitaxial layer and accumulates charges generated by photoelectric conversion;
A first conductivity type impurity layer formed on the second surface side of the epitaxial layer than the second conductivity type region and having a higher impurity concentration than the epitaxial layer;
Receiving light from the second surface side of the epitaxial layer;
A solid-state imaging device, wherein the impurity concentration of the first conductivity type impurity layer has a concentration gradient that increases toward the second surface side, and is defined to have a maximum concentration at the position of the second surface. The solid-state imaging device according to claim 1, wherein a thickness of the epitaxial layer is 4 μm to 10 μm. The solid-state imaging device according to claim 1, wherein a first conductivity type region is further formed on a surface layer of the first surface of the epitaxial layer. The solid-state imaging device according to claim 1, wherein a substrate having a thermal expansion coefficient different from that of the epitaxial layer is formed on the first surface side of the epitaxial layer.

Images