JP2008293387A - Data lookahead apparatus, data processing system, data lookahead processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data lookahead apparatus which can shorten access time of reading prescribed data by a processing apparatus. <P>SOLUTION: The data lookahead apparatus is provided with an address range information storage means which memorizes an address range information of a storage domain where data of processing object at data storage means is memorized, a data holding means which holds data read ahead from a data storage means, a control means which writes data read ahead to the data holding means while looking-ahead data from the data storage means based on the address range information memorized in the address range information storage means, and a data reading means which reads data from the data holding means based on address information concerning prescribed data output from a processing apparatus which requests reading of data of processing object and which outputs the read-out data toward the processing apparatus. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data prefetching device, a data processing system, and a data prefetching processing program.

  A device such as a processor that is interposed between a bus master and a storage device and exchanges data with them, such as a data prefetching device, a memory control device, and a data transfer device, temporarily holds data. It has a buffer and has a data prefetching mechanism (data prefetching function) that performs prefetch processing of data from the storage device and write processing to the buffer of prefetched data in response to a read request from the bus master. is doing.

  When the data corresponding to the read address related to the read access from the bus master is stored in the buffer, that is, when it hits, the hit data is output from the buffer to the bus master.

  As is well known, the buffer cannot store all the data stored in the storage device as prefetched data from the viewpoint of the limitation of the storage capacity (retention capacity). Therefore, there may be a case where data corresponding to the read address output from the bus master is not stored in the buffer, that is, a hit miss occurs.

As an apparatus having a data prefetching mechanism, for example, those disclosed in Patent Documents 1 to 4 are known.
Japanese Patent Laid-Open No. 6-243037 JP 2001-229074 A JP 2001-256169 A JP 2003-173291 A

  An object of the present invention is to provide a data prefetching device, a data processing system, and a data prefetching processing program that can shorten the access time for reading out predetermined data to be processed by a processing device.

  In order to solve the above-mentioned problem, the data prefetching device according to the first aspect of the present invention provides address range information of a storage area in which the predetermined data of the data storage means for storing the predetermined data to be processed is stored. Address range information storage means for storing, data holding means for holding data prefetched from the data storage means, and data from the data storage means based on address range information stored in the address range information storage means The data based on the address information related to the predetermined data output from the control means for pre-reading and writing the pre-read data to the data holding means and the processing device for executing the predetermined processing on the predetermined data Data reading that reads data from the holding means and outputs the read data to the processing device And having a stage, a.

  According to a second aspect of the present invention, in the first aspect of the present invention, when the predetermined data is not all written to the data holding means, the control means is configured for the data that has not been prefetched. The data read-ahead process and the write process are performed in accordance with the storage capacity of the free area of the data holding unit after the data reading unit performs the data reading process.

  According to a third aspect of the present invention, in the first or second aspect of the invention, the address range information storage unit is configured to perform the processing when the predetermined data is divided and stored in the data storage unit. A plurality of address range information corresponding to a plurality of storage areas in which data after division is stored is stored, and the control unit performs data based on the plurality of address range information stored in the address range information storage unit. The prefetching process and the writing process are performed.

  In order to solve the above problem, a data processing system according to a fourth aspect of the present invention includes a data storage unit that stores predetermined data to be processed, and a processing device that executes predetermined processing on the predetermined data. A data prefetching device that prefetches data from the data storage means and outputs the prefetched data to the processing device, and the data prefetching device stores the predetermined data of the data storage means Address range information storage means for storing address range information of the storage area being stored, data holding means for holding data prefetched from the data storage means, and address range information stored in the address range information storage means Control for prefetching data from the data storage means based on the data and writing the prefetched data to the data holding means And data reading means for reading data from the data holding means based on address information related to the predetermined data output from the processing device and outputting the read data to the processing device. It is characterized by that.

  According to a fifth aspect of the present invention, in the invention according to the fourth aspect of the invention, when all of the predetermined data is not written to the data holding means, the control means The data read-ahead process and the write process are performed in accordance with the storage capacity of the free area of the data holding unit after the data reading unit performs the data reading process.

  According to a sixth aspect of the present invention, in the invention according to the fourth or fifth aspect, the address range information storage unit includes the address range information storage unit when the predetermined data is divided and stored in the data storage unit. A plurality of address range information corresponding to a plurality of storage areas in which data after division is stored is stored, and the control unit performs data based on the plurality of address range information stored in the address range information storage unit. The prefetching process and the writing process are performed.

  The invention according to claim 7 is the invention according to claim 6, wherein the data storage means stores a part of the address range information among the plurality of address range information, and the data prefetching device Based on the storage location information stored in the storage location information storage means and the storage location information storage means for storing the storage location information of the data storage means in which some address range information is stored, the data storage Address range information reading means for reading address range information from the means, and the control means uses the address range information reading means for data stored in the storage area based on the partial address range information. Based on the read address range information, data prefetching processing and writing processing are performed.

  In order to solve the above-mentioned problem, the data prefetch processing program according to the present invention described in claim 8 stores the address range information of the storage area where the predetermined data to be processed in the data storage means is stored in the address range information storage means. Pre-stored by a pre-store process, a pre-process for storing data in advance, a pre-read process for executing data pre-read from the data storage unit based on the address range information stored in the address range information storage unit, Data is read from the data holding means based on a holding process for holding data in the data holding means and address information related to the predetermined data output from the processing device, and the read data is directed to the processing device. It is characterized by causing a computer to execute an output data reading process.

  According to the first aspect of the present invention, for the predetermined data to be processed on which the predetermined processing is executed by the processing device, the control means stores the data in the data storage means based on the address range information in the address range information storage means. The predetermined data is prefetched, and the prefetched data is written in the data holding unit, so that the access time for reading the predetermined data to be processed by the processing apparatus can be shortened.

  According to the second aspect of the present invention, when the data amount of the predetermined data to be processed exceeds the holding capacity of the data holding unit, the control unit performs the data reading process by the data reading unit. Data prefetching processing and writing processing can be performed in accordance with the storage capacity of the free area of the data storage means.

  According to the invention described in claim 3, even when the predetermined data to be processed is divided and stored in a plurality of non-contiguous storage areas of the data storage means, the control means Based on a plurality of pieces of address range information corresponding to the area, data prefetching processing and writing processing can be performed.

  According to the fourth aspect of the present invention, for the predetermined data to be processed on which the predetermined processing is executed by the processing device, the control means stores the data in the data storage means based on the address range information in the address range information storage means. It is possible to pre-read predetermined data to be processed and write the pre-read data to the data holding unit, thereby shortening the access time for reading the predetermined data to be processed by the processing device.

  According to the fifth aspect of the present invention, when the data amount of the predetermined data to be processed exceeds the storage capacity of the data holding unit, the control unit performs the data reading process by the data reading unit. Data prefetching processing and writing processing can be performed in accordance with the storage capacity of the free area of the data storage means.

  According to the invention described in claim 6, even when the predetermined data to be processed is divided and stored in a plurality of non-contiguous storage areas of the data storage means, the control means Based on a plurality of address range information corresponding to a plurality of storage areas in which data is stored, data prefetching processing and writing processing can be performed.

  According to the seventh aspect of the present invention, when predetermined data to be processed is divided and stored in the data storage means, a plurality of addresses corresponding to a plurality of storage areas in which the divided data is stored When all of the range information cannot be stored in the address range information storage unit, the address range information that cannot be stored in the address range information storage unit can be stored in the data storage unit.

  According to the invention described in claim 8, the predetermined data to be processed in the data storage unit is prefetched based on the address range information in the address range information storage unit, and the preread data is held in the data holding unit. It is possible to provide software that shortens the access time for reading the predetermined data to be processed by the processing device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  (Embodiment 1)

  FIG. 1 shows a configuration of a data processing system according to the first embodiment.

  As shown in FIG. 1, the data processing system includes a plurality of bus masters 10, 20, 30, 40, a system bus 100, a data prefetching device 200, a memory controller 400, and an external storage device 500.

  The plurality of bus masters 10 to 40 and the data prefetching device 200 are connected via the system bus 100.

  The system bus 100 is connected to a plurality of bus masters including one or more other bus masters (not shown) in addition to the plurality of bus masters 10 to 40 and is one of bus slaves. The data prefetching device 200 is connected with other bus slaves (not shown).

  The plurality of bus masters 10 to 40 are processing devices that execute predetermined processing on data to be processed, for example, image processing devices that perform different image processing, and predetermined data (for example, image processing targets) of processing targets (for example, image processing targets). Hereinafter, the external storage device 500 that stores data including “processing target data” is accessed.

  Specifically, the plurality of bus masters 10 to 40 execute image processing (predetermined processing) on the processing target data read from the external storage device 500. As shown in FIG. Image processing is sequentially executed in the order of arrangement of the master 10, the buster master 20, the buster master 30, and the buster master 40. In this case, data exchange between these bus masters is performed via the external storage device 500.

  That is, the bus master 10 performs image processing on the processing target data obtained by the read access to the external storage device 500, and the processing target data after the image processing is transferred to the system bus 100 and the data prefetching device 200 (to be described later in DMA control). Unit 300) and the memory controller 400, the data is stored in the external storage device 500. Next, the bus master 20 performs image processing on the processing target data obtained by the read access to the external storage device 500, and the processing target data after the image processing is transferred to the system bus 100 and the data prefetching device 200 (to be described later). The data is stored in the external storage device 500 via the control unit 300) and the memory controller 400. The buster masters 30 and 40 perform the same processing as described above.

  Again, a description will be given with reference to FIG. The system bus 100 can access each bus master at an arbitrary timing and performs bus arbitration (bus arbitration).

  Access to the external storage device 500 from the system bus 100 is performed through the data prefetching device 200 and the memory controller 400.

  The data prefetching device 200 performs data prefetching (data prefetch) processing on the external storage device 500 via the memory controller 400. In addition, the data prefetching device 200 performs data write processing or data read processing on the external storage device 500 via the memory controller 400 by direct memory access (DMA).

  The memory controller 400 accesses the external storage device 500 in accordance with a data prefetching instruction (command) from the data prefetching apparatus 200, a data writing instruction (command) or a data reading instruction (command) by the DMA.

  The external storage device 500 stores data including data to be processed as described above, and includes, for example, a DRAM (Dynamic Random Access Memory: an occasional write / read memory that requires a memory holding operation).

  Next, the functional configuration of the data prefetching apparatus 200 will be described with reference to FIG.

  As shown in FIG. 3, the data prefetching apparatus 200 includes an input control unit 210, a temporary buffer management unit 220, a temporary buffer 230, an output control unit 240, and a DMA control unit 300.

  The input control unit 210 analyzes the access from the system bus 100 and determines whether the access is related to data prefetch processing or access related to read or write, and outputs the determined result and access information to the DMA control unit 300. .

  The access related to the data prefetching process includes, for example, address range information (start address and end address) of the storage area of the processing target data stored in the external storage device 500 and an instruction for setting the address. Since the access information (address range information and address setting instruction) is output from the bus master that has acquired the right to use the bus, the input control unit 210 receives the access information and determination results received via the system bus 100. To the DMA controller 300 is output to the effect that the access is related to the data prefetching process.

  The read-related access includes read access to processing target data and read access to data other than processing target data. Note that the read access to the processing target data means the read access to the temporary buffer 230. The access related to writing includes write access to processing target data and write access to data other than processing target data. Since these pieces of access information are output from the bus master that has acquired the right to use the bus, the input control unit 210 indicates that the access information is received via the system bus 100 and the access is related to read or write as a determination result. And output to the DMA control unit 300.

  The temporary buffer management unit 220 manages all or part of the processing target data prefetched from the external storage device 500 and temporarily stored in the temporary buffer 230, and addresses all or part of the processing target data. A memory (not shown) that stores mapping information in which (address in the address space of the external storage device 500) is mapped to an address in the address space of the temporary buffer, a read pointer, and a write pointer is provided.

  In addition, the temporary buffer management unit 220 performs the following processes (1) to (5).

  (1) When address information (address space address of the external storage device 50) output from the DMA control unit 300, which will be described later, and a data prefetching instruction are received, the address information is passed to the output control unit 240 and the data Request prefetch processing.

  (2) When the data prefetched from the external storage device 500 is stored in the temporary buffer 230 by the prefetching process of the output control unit 240 described later, the mapping information is generated and stored in the memory (not shown), Further, the write pointer is made to point to the last address (address space address of the external storage device 500) related to the written data. In addition, the address (address space address of the external storage device 500) indicated by the write pointer and the fact that the prefetch processing is interrupted are output to the DMA control unit 300.

  (3) When read address information (address in the address space of the external storage device 500) output from the DMA control unit 300 described later is received, the read address information and the memory (not shown) store the read address information. Based on the mapping information, it is confirmed that the data corresponding to the read address exists in the data held in the temporary buffer 230. Thereafter, the temporary buffer 230 is given an address in the address space of the temporary buffer 230 corresponding to the read address, and instructed to output the corresponding data to the input control unit 210 (read output instruction). Further, the read pointer is made to indicate the last address (address space address of the external storage device 50) related to the read data.

  The information of the read pointer is used when the temporary buffer management unit 220 obtains an empty area of the temporary buffer 230. That is, a storage area corresponding to the address range from the address at the time when the read output is instructed to the address indicated by the read pointer is obtained as a free area.

  (4) The empty area of the temporary buffer 230 after data is output from the temporary buffer 230 by the process of (3) above is obtained, and the storage capacity of this empty area is notified to the DMA control unit 300.

  (5) When read address information (address in the address space of the external storage device 50) output from the DMA control unit 300, which will be described later, is received in order to perform the prefetch process while the data prefetch process is interrupted. Passes the address information to the output control unit 240 and requests data prefetching.

  The temporary buffer 230 temporarily holds processing target data prefetched from the external storage device 500, and includes, for example, an SRAM (Static Random Access Memory).

  When there is a read access request from the DMA control unit 300, the output control unit 240 outputs the read data returned from the memory controller 400 to the DMA control unit 300, while the temporary buffer management unit 220 performs read access. When requested, the read data returned from the memory controller 400 is written into the temporary buffer 230.

  The DMA control unit 300 includes a DMA control unit internal setting I / F 310, an address management register 320, an address determination / generation unit 330, and a DMA processing unit 340.

  The DMA control unit internal setting I / F 310 is an access to the address management register 320 based on data received from the input control unit 210 (such as an address for read access and an address to be set), or It is determined whether the access is to other than the address management register 320, and a predetermined process is performed according to the determined result.

  The access to the address management register 320 includes access related to data prefetching processing. Accesses other than the address management register 320 include read access and write access.

  When the DMA control unit internal setting I / F 310 determines that the access is to the address management register 320, the address range information described above is set in the address management register 320, and access to other than the address management register 320 is performed. If it is determined that there is, for example, a read address relating to read access is output to the address determination / generation unit 330.

  In addition, the DMA control unit internal setting I / F 310 outputs processing start and processing end to the DMA processing unit 340 and provides the information stored in the address management register 320 to the input control unit 210.

  The address management register 320 is assigned an area for storing three pieces of information: address range information, current address, and status.

  The address management register 320 has a function of an address range information storage unit that stores address range information of a storage area in which processing target data of the external storage device 500 is stored.

  In the present specification, the address range information means a start address and an end address of an address space (real address space) of a storage area in which processing target data is stored.

  The address range information is output to the data prefetching device 200 from the bus master that has performed write access (write processing) on the processing target data after the image processing is performed, and is further set in the DMA control unit of the DMA control unit 300. The data is written into the address management register 320 by the general I / F 310.

  The current address is an address related to processing target data stored in the external storage device 500 and means a final address related to data (prefetched data) stored in the temporary buffer 230. That is, it means an address notified from the temporary buffer management unit 220 to the DMA control unit 300 together with the fact that the prefetch processing is interrupted.

  The status means that valid data is stored in the designated address space.

  The fact that valid data has been stored in the address space is output from the bus master that has performed write access (write processing) to the data to be processed after image processing to the data prefetching device 200, and further DMA The data is written in the address management register 320 by the DMA control unit internal setting I / F 310 of the control unit 300.

  In other words, when the bus master currently acquiring the right to use the bus stores the data to be processed after the image processing is performed in the external storage device 500, the data effective in the address space of the external storage device 500 Is stored to the DMA control unit 300. The fact that valid data is stored in the address space is stored in the address management register 32 via the input control unit 210 and the DMA control unit internal setting I / F 310. When the bus master releases the right to use the bus, the next bus master acquires the right to use the bus and performs image processing.

  The bus master 10 at the foremost stage performs image processing on the processing target data that has been write-accessed (written) by the bus master that requests the bus master 10 to perform image processing.

  The address determination / generation unit 330 generates an address for DMA access to the external storage device 500 based on the start address, end address, and current address as address range information stored in the address management register 320. The generated address is output to the DMA processing unit 340.

  Further, when the address determination / generation unit 330 receives the read address from the DMA control unit internal setting I / F 310, it is determined whether or not the read address is an address for read access to the temporary buffer 230, that is, It is determined whether or not the address is included in the address range from the start address to the end address stored in the address management register 320, and the determination result and the read address are output to the DMA processing unit 340.

  The DMA processing unit 340 manages the DMA cycle of the external storage device 500.

The DMA processing unit 340 outputs a read address to the output control unit 240 when the determination result from the address determination / generation unit 330 indicates that the address is not included in the address range.
In contrast, when the determination result from the address determination / generation unit 330 received by the DMA processing unit 340 is an address included in the address range, the DMA control unit 300 receives the DMA processing unit 340. The read address is output to the temporary buffer management unit 220.

  The DMA control unit 300 has a function of controlling each component of the DMA control unit internal setting I / F 310, the address management register 320, the address determination / generation unit 330, and the DMA processing unit 340 described above.

  In the first embodiment, the data storage unit described above corresponds to the external storage device 500, the address range information storage unit described above corresponds to the address management register 320, the data storage unit described above corresponds to the temporary buffer 230, and The control means corresponds to the DMA control section 300, the temporary buffer management section 220, and the output control section 240, and the data reading means described above corresponds to the DMA control section 300 and the temporary buffer management section 220.

  Next, data prefetching processing (hereinafter referred to as “data prefetching processing”) of the data prefetching apparatus 200 will be described with reference to FIGS.

  4 is a diagram for explaining the data prefetching process, FIG. 5 is a diagram showing in detail the DMA control unit of FIG. 4, and FIG. 6 is a diagram for explaining a series of data prefetching processes.

  Here, it is assumed that the storage capacity of the temporary buffer 230 is smaller than the data amount of the processing target data. That is, it is assumed that all of the processing target data cannot be prefetched and stored in the temporary buffer 230.

  The fact that valid data is stored in the address space output from the bus master that has performed write access (write processing) of the processing target data, and the start address and end address as address range information are data via the system bus 100. When input to the input control unit 210 of the prefetching apparatus 200, the input control unit 210 determines that the access is related to the data prefetching process based on the information, and the determination result is as shown in FIG. 4 and FIG. Information from the bus master received via the system bus 100 is output to the DMA controller 300 (P1 * 1).

  In the DMA control unit 300, the DMA control unit internal setting I / F 310 that has received the determination result from the input control unit 210, that valid data is stored in the address space, and the address range information is based on the determination result. It is determined that the access is to the address management register 320, and as shown in FIG. 5, the fact that valid data is stored in the address space is stored in the address management register 320, and the start address and the address range information are The end address is stored in the address management register 320 (P11 in FIG. 5).

  Further, the DMA control unit internal setting I / F 310 clears (initializes) the contents of the area where the current address of the address management register 320 is stored.

  When the address range information is stored in the address management register 320 as described above, the DMA control unit internal setting 1 / F 310 notifies the address determination / generation unit 330 that the address setting has been completed (see FIG. 5 P12).

  The address determination / generation unit 330 that has received the notification that the address setting has been completed reads the address range information (start address and end address) from the address management register 320 (P13 in FIG. 5), and this read start address and end An address of data to be prefetched is generated based on the address, and the generated address is output to the DMA processing unit 340 (P14 in FIG. 5).

  The address determination / generation unit 330 generates a continuous address with reference to the start address and outputs the generated address to the DMA processing unit 340. The address generation processing receives the prefetch interruption instruction from the temporary buffer management unit 220. Or until the address to be generated reaches the end address.

  Data corresponding to a predetermined range of addresses generated in this way is prefetched.

  The DMA processing unit 340 outputs the DMA cycle signal to the output control unit 240 (P15 in FIG. 5).

  When the DMA processing unit 340 receives an address (address information) generated for data prefetching, the DMA control unit 300, as shown in FIGS. 4 and 5, reads data prefetching instructions and address information (generated address). ) Is output to the temporary buffer management unit 220 (P1 * 2).

  The temporary buffer management unit 220 that has received the data prefetch instruction and the address information (generated address) determines that it is a data prefetch process, and sends a request for the address information and the data prefetch process (read access) to the output control unit 240. Output (P1 * 3).

  When the output control unit 240 outputs the received address information and data prefetch instruction to the memory controller 400 in accordance with the DMA cycle signal from the DMA processing unit 340 (P1 * 4), the memory controller 400 stores the external storage device. Data corresponding to the address information is read from 500 (P1 * 5 in FIG. 4), and this prefetched data is output to the output control unit 240 (P1 * 6).

  The output control unit 240 that has received the prefetch data from the memory controller 400 stores the prefetch data in the temporary buffer 230 (P1 * 7).

  By the way, the temporary buffer management unit 220 monitors the temporary buffer 230 after requesting the output control unit 240 to perform the prefetch process, and the data prefetched from the external storage device 500 by the prefetch process of the output control unit 240 is temporarily stored. When stored in the buffer 230, the mapping information, that is, mapping information between the address of the external storage device 500 (the address acquired from the DMA control unit 300) and the address of the temporary buffer 230 is generated. The data is stored in the memory (not shown), and the write pointer points to the last address (address in the address space of the external storage device 500) related to the written data.

  Then, the temporary buffer management unit 220 stores the temporary buffer when the data amount of the pre-read data stored in the temporary buffer 230 reaches a preset data amount (when the predetermined storage capacity of the temporary buffer 230 is reached). The final address relating to the data stored in 230, that is, the current address (address indicated by the write pointer) and the pre-read processing interruption are output to the DMA control unit 300 (P2). Wait until requested.

  In the DMA control unit 300 that has received the pre-read processing suspension and current address information, the address determination / generation unit 330 interrupts the address generation processing, and the DMA control unit internal setting I / F 310 manages the current address as an address. Store in register 320.

  When a bus master currently acquiring the right to use the bus outputs a read address to the data prefetching device 200 as a bus slave in order to perform read access to the data to be processed, the read address is transmitted via the system bus 100. Are input to the input control unit 210 of the data prefetching device 200.

  The input control unit 210 determines that the access is a read access based on the read address from the bus master, and the determination result and the read from the bus master received via the system bus 100 as shown in FIGS. The address is output to the DMA control unit 300 (P3 * 1).

  In the DMA control unit 300, the DMA control unit internal setting I / F 310 that has received the determination result from the input control unit 210 and the read address determines that the access is to other than the address management register 320 based on the received determination result. Then, the received read address is output to the address determination / generation unit 330 (P31 in FIG. 5).

  The address determination / generation unit 330 determines whether the read address from the DMA control unit internal setting I / F 310 is an address included in the address range from the start address to the end address stored in the address management register 320. When the read address is determined to be an address included in the address range, the determination result and the read address are output to the DMA processing unit 340 (P32 in FIG. 5).

  When the determination result by the address determination / generation unit 330 is an address included in the address range, the DMA control unit 300 outputs the read address received by the DMA processing unit 340 to the temporary buffer management unit 220. (P3 * 2).

  When the temporary buffer management unit 220 receives the read address information (address in the address space of the external storage device 500) output from the DMA control unit 300, the temporary buffer management unit 220 stores the read address information in the memory (not shown). On the basis of the mapping information, it is confirmed that data corresponding to the read address exists in the data held in the temporary buffer 230.

  The temporary buffer management unit 220 confirming that the read address is held in the temporary buffer 230 in this manner gives the temporary buffer 230 the address of the address space of the temporary buffer 230 corresponding to the read address, An instruction is given to output the corresponding data to the input control unit 210 (P3 * 3).

  The temporary buffer management unit 220 inputs a synchronization signal synchronized with an output signal (address and read output instruction) to the temporary buffer 230 as a timing at which the input control unit 210 should take in the data output from the temporary buffer 230. It outputs to the control part 210 (P3 * 4).

  When the temporary buffer 230 that has received the address and read output instruction from the temporary buffer management unit 220 outputs data (read data) corresponding to the address to the input control unit 210 (P3 * 5), input control is performed. The unit 210 fetches the read data output from the temporary buffer 230 in synchronization with the synchronization signal from the temporary buffer management unit 220, and the fetched read data is a bus that is a request source of read access via the system bus 100. Output to the master.

  In addition, the temporary buffer management unit 220 points the read pointer to the last address (address space address of the external storage device 500) related to the read data.

  As described above, when data (read data) is read from the temporary buffer 230 based on the address from the temporary buffer management unit 220, the storage area of the temporary buffer 230 in which the read data is stored becomes an empty area. .

  Therefore, the temporary buffer management unit 220 stores a storage area corresponding to an address range from the address indicated by the read pointer at the time when the read output instruction is output to the temporary buffer 230 to the address indicated by the current read pointer, that is, a free area. When this free area reaches a predetermined free area set in advance, a prefetching restart instruction is output to the DMA controller 300 (P4).

  In the DMA control unit 300 that has received the prefetch resumption instruction, the address determination / generation unit 330 generates an address of data to be prefetched based on the address next to the current address stored in the address management register 320 (see FIG. 5), the generated address is output to the DMA processing unit 340 (see P14 in FIG. 5). The DMA processing unit 340 outputs the DMA cycle signal to the output control unit 240 (see P15 in FIG. 5).

  The address determination / generation unit 330 generates a continuous address based on the next address of the current address and outputs it to the DMA processing unit 340. This address generation processing is prefetched from the temporary buffer management unit 220. The process is executed until an interruption instruction is received or an address to be generated reaches an end address.

  Thereafter, as shown in FIG. 4 and FIG. 5, prefetching processing similar to the processing of P1 * 3 to P1 * 7 is performed (P5 * 2 to P5 * 6).

  As described above, when image processing is performed on the processing target data stored in the external storage device 500 by the bus master that has acquired the right to use the bus, the data prefetching device 200 is as shown in FIG. In addition, when the processes of P1 to P5 are performed and not all the processing target data can be stored in the temporary buffer 230, the processes of P2 to P5 are repeated, and finally the process of P3 is performed and the process is terminated.

  In FIG. 6, P1 to P5 correspond to the symbols P1 to P5 shown in FIGS. 4 and 5, and P1 * 1 to P1 * 7, P3 * 1 to P3 * 5, P5 * 1 to P1. * 6 corresponds to those symbols shown in FIG. 4 and FIG.

  Here, a specific example of the data prefetching process will be described with reference to FIGS.

  As shown in FIG. 7, the external storage device 500 has an address space from 0x0 (hexadecimal) to 0xFFFFFFFF (hexadecimal), for example, and has an address range from the start address to the end address of the address space. Data to be processed is stored in the corresponding storage area. This storage area functions as an image data area for storing data to be processed as image data.

  On the other hand, the temporary buffer 230 is an address space from the head address to the last address, and a holding area (storage area) corresponding to this address space is set to a prescribed holding capacity.

  By executing the processing of P1 in FIG. 6 (P1 * 1 to P1 * 7 in FIGS. 4 and 6) described above, the processing target data stored in the external storage device 500 is referred to with reference to the start address. Data corresponding to a predetermined access unit corresponding to successive addresses is copied, and the copied data is stored in the temporary buffer 230 as prefetched data.

  Here, when the data amount of the pre-read data stored in the temporary buffer 230 reaches the holding capacity of the temporary buffer 230, the above-described processing of P2 in FIG. 6 (P2 in FIGS. 4 and 6) is executed. As a result, the processing target data D1 # stored in the storage area corresponding to the address range from the start address of the address space of the external storage device 500 to the current address is stored in the temporary buffer 230 as prefetched data.

  In this state, the processing of P3 in FIG. 6 (P3 * 1 to P1 * 5 in FIGS. 4 and 6) described above is executed, so that the processing target data stored in the temporary buffer 230 as shown in FIG. D1 # is read out and output to the bus master that is the source of the read access request.

  In this manner, data is read from the temporary buffer 230, and the above-described P4 in FIG. 6 (FIGS. 4 and 4) is caused by the fact that the empty area of the temporary buffer 230 has reached a predetermined empty area. 6 P4) and the above-described P5 in FIG. 6 (P5 * 1 to P1 * 6 in FIG. 4 and FIG. 6) are executed, so that the external storage is performed as shown in FIG. With respect to the processing target data stored in the apparatus 500, data of a predetermined access unit is copied corresponding to a continuous address with reference to the previous current address (current address stored in the address management register 320). The copied data is stored in the temporary buffer 230 as prefetched data.

  Here, when the data amount of the pre-read data stored in the temporary buffer 230 reaches the holding capacity of the temporary buffer 230, the above-described processing of P2 in FIG. 6 (P2 in FIGS. 4 and 6) is executed. As a result, the processing target data D2 # stored in the storage area corresponding to the address range from the address next to the previous current address to the current current address in the address space of the external storage device 500 is pre-read data as the temporary buffer 230. Will be stored.

  As described above, in the temporary buffer 230, the prefetched data prefetched from the external storage device 500 is refilled each time a predetermined empty area is generated.

  In this state, the processing of P3 in FIG. 6 (P3 * 1 to P1 * 5 in FIGS. 4 and 6) described above is executed, so that the processing stored in the temporary buffer 230 as shown in FIG. The target data D1 # is read out and output to the bus master that is the read access request source.

  In this manner, data is read from the temporary buffer 230, and the above-described P4 in FIG. 6 (FIGS. 4 and 4) is caused by the fact that the empty area of the temporary buffer 230 has reached a predetermined empty area. 6 P4) and the above-described P5 in FIG. 6 (P5 * 1 to P1 * 6 in FIG. 4 and FIG. 6) are executed, as shown in FIG. Similar to the data prefetching processing of the processing target data D2 #, regarding the processing target data stored in the external storage device 500, data in a predetermined access unit is copied corresponding to consecutive addresses with reference to the previous current address. The copied data is stored in the temporary buffer 230 as prefetched data.

  Here, when the data amount of the pre-read data stored in the temporary buffer 230 reaches the holding capacity of the temporary buffer 230, the above-described processing of P2 in FIG. 6 (P2 in FIGS. 4 and 6) is executed. As a result, as shown in FIG. 11, the processing target data D3 # stored in the storage area corresponding to the address range from the address next to the previous current address to the current current address in the address space of the external storage device 500 Is stored in the temporary buffer 230 as prefetched data.

  Then, the processes of P2 to P5 in FIG. 6 described above are repeated until the current address reaches the end address, and finally the process of P3 is performed.

  Next, read access processing by the data prefetching device 200 when the bus master that has acquired the right to use the bus performs predetermined processing on data other than the processing target data stored in the external storage device 500 will be described. .

  In the data prefetching apparatus 200, the same processing as the above-described P3 * 1 (see FIGS. 4 and 5) is performed, and the read address from the bus master, which is the read access request source, becomes the system bus 100 and input control. The data is input to the DMA control unit 300 via the unit 210.

  The DMA control unit 300 performs the same processing as P31 (see FIG. 5) described above, and the accepted read address is input to the address determination / generation unit 330.

  The address determination / generation unit 330 determines whether the read address from the DMA control unit internal setting I / F 310 is an address included in the address range from the start address to the end address stored in the address management register 320. Determine. In this case, the address determination / generation unit 330 determines that the read address is not included in the address range, and outputs the determination result and the accepted read address to the DMA processing unit 340.

  When the received determination result from the address determination / generation unit 330 is an address that is not included in the address range, the DMA processing unit 340 directs the received read address and DMA cycle signal to the output control unit 240. Output.

  When the output control unit 240 outputs the received read address and read command to the memory controller 400 according to the DMA cycle signal from the DMA processing unit 340, the memory controller 400 responds to the read address from the external storage device 500. Data to be read (data other than the data to be processed) is read, and the read data (read data) is output to the output control unit 240.

  The read data received by the output control unit 240 is input to the input control unit 210 via the DMA control unit 300 and further input to the bus master that is the request source of the read access via the system bus 100.

  Next, data prefetching processing by the data prefetching processing apparatus 200 will be described with reference to FIG.

  FIG. 12 is a flowchart showing the processing procedure of the data prefetching process.

  As shown in FIG. 12, in the data prefetching apparatus 200, the DMA control unit 300 sets (stores) each address in the address management register 320 in the same manner as the processing of P11 (see FIG. 5) described above (step S101). Then, the same processing as P12 to P15 (see FIG. 5) described above is performed, and, similarly to the processing of P1 * 2 (see FIG. 5) described above, a data prefetch instruction and address information (generated address) are temporarily stored. The data is output to the buffer management unit 220 (S102).

  Next, similarly to the processing of P1 * 3 to P1 * 7 (see FIG. 5) described above, with respect to the processing target data stored in the external storage device 500, the temporary buffer management unit 220 is directed to the output control unit 220. Data corresponding to successive addresses based on the output start address is prefetched, and the prefetched data (prefetched data) is stored in the temporary buffer 230 (step S103). In this case, the prefetch data is stored until a predetermined storage capacity of the temporary buffer 230 is reached.

  In this way, when the prefetch read is stored in the temporary buffer 230 and the processing of P2 (see FIG. 5) described above is performed, the input control unit 210 determines whether or not there is a read access from the bus master. (Step S104) If there is no read access, the system waits until there is a read access. On the other hand, if there is a read access, it is a read access, similar to the process of P3 * 1 (see FIG. 5) described above. The fact (determination result) and the accepted read address are output to the DMA control unit 300.

  In the DMA control unit 300, in order to start the read access process (step S105), the DMA control unit internal setting I / F 310 performs the same process as the above-described P31 (see FIG. 5), and further determines the address. / Generating section 330 determines whether or not the read address is included in the address range based on the address range information, similarly to the process of P32 (see FIG. 5) described above (step S106).

  If it is determined in step S106 that the read address is included in the address range, it corresponds to the designated address from the temporary buffer 230, as in the above-described processing of P3 * 2 to P3 * 5 (see FIG. 5). Data is read out and output to the bus master that is the source of the read access request (step S107).

  When step S107 is performed and the same processing as in P4 (see FIG. 5) described above is performed, in the DMA control unit 300, the address determination / generation unit 330 displays the current address stored in the address management register 320. It is determined whether or not has reached the end address (step S108).

  Here, when the current address reaches the end address, it means that the data up to the end address is prefetched and stored in the temporary buffer 230 with respect to the processing target data stored in the external storage device 500. On the other hand, if the current address does not reach the end address, it means that there is data to be prefetched regarding the processing target data stored in the external storage device 500.

  If it is determined in step S108 that the current address stored in the address management register 320 has reached the end address, the data prefetching process is terminated.

  On the other hand, if it is determined in step S108 that the current address stored in the address management register 320 has not reached the end address, the address determination / generation unit 330 performs address management in the same manner as in the process of P13 described above. Based on the address next to the current address stored in the register 320, an address of data to be prefetched is generated. In this case, consecutive addresses are generated with reference to the next address of the current address.

  Then, similarly to the processing of P13, P15, and P5 * 1 to P5 * 6 described above, data corresponding to the address generated by the address determination / generation unit 330 is prefetched from the external storage device 500 and stored in the temporary buffer 230. Stored (step S109). In this case, data in a predetermined access unit is prefetched corresponding to consecutive addresses on the basis of the generated address.

  After step S109 is completed, the read access process is terminated, and the process returns to step S104.

  By the way, when it is determined in step S106 that the read address is not included in the address range, as described above, a predetermined process is performed on data other than the data to be processed by the bus master that has acquired the right to use the bus. As in the case of read access processing by the data prefetch device 200, read access is performed to the external storage device 500, and the data corresponding to the read address is directed to the bus master that is the request source of the read access. Is output (step S111). Then, it progresses to step S110.

  In the first embodiment, a plurality of bus masters access the data prefetching device 200 via the system bus 100. However, a bus arbiter (bus arbitration circuit) that arbitrates access from each bus master is used. It may be provided outside or inside the data prefetching device 200, and each of the bus masters may access the data prefetching device 200 via a bus arbiter.

  In the first embodiment, a plurality of bus masters that perform predetermined processing (for example, image processing) are connected to the system bus 100. However, predetermined processing (for example, image processing) is performed. One bus master may be connected to the system bus 100.

  Further, in the first embodiment, one temporary buffer is provided in the data prefetching apparatus 200, but a plurality of temporary buffers may be provided.

  In this case, the temporary buffer management unit 220 notifies the output control unit 240 that it indicates which pre-read data should be stored in the temporary buffer among the plurality of temporary buffers. The prefetch data returned from 400 is stored in the notified temporary buffer.

  Next, the temporary buffer management unit 220 generates mapping information in which an address (address space address of the external storage device 200) related to prefetched data prefetched from the external storage device 500 is mapped to an address space of a specific temporary buffer. .

  Then, when reading data corresponding to the read address related to read access from the bus master, the temporary buffer management unit 220 stores data corresponding to the read address from a plurality of temporary buffers based on the mapping information. A stored temporary buffer is specified, and a read address is given to the specified temporary buffer to output data.

  (Embodiment 2)

  The data processing system according to the second embodiment has the same configuration as that of the data processing system according to the first embodiment shown in FIG.

  FIG. 13 shows a functional configuration of the data prefetching apparatus according to the second embodiment. The data prefetching device 200 has a configuration in which the address management register 310 is changed to the address management RAM 600 in the configuration of the DMA control unit 300 of the data prefetching device 200 of the first embodiment shown in FIG.

  In the second embodiment, the external storage device 500 divides the processing target data into a plurality of storage areas as shown in FIG.

  In this example, the processing target data is divided into four, and the four pieces of divided data (divided data) are distributed and stored in four storage areas. Incidentally, the divided data D0 is stored in the storage area MA0, the divided data D1 is stored in the storage area MA1, the divided data D2 is stored in the storage area MA2, and the divided data D3 is stored in the storage area MA3.

  The start address 0 and the end address 0 mean the start address and the end address related to the storage area MA0, the start address 1 and the end address 1 mean the start address and the end address related to the storage area MA1, the start address 2 and the end address 2 means a start address and an end address related to the storage area MA1, and a start address 3 and an end address 3 mean a start address and an end address related to the storage area MA3.

  As shown in FIG. 13, the address management RAM 600 stores a plurality of address range information corresponding to a plurality of storage areas of the external storage device 500. These address range information means the start address and end address of the address space (real address space) of the corresponding storage area, as in the first embodiment. The address management RAM 600 is composed of a RAM (Random Access Memory).

  In the second embodiment, as shown in FIG. 15, the DMA control unit internal setting I / F 310 generates an address profile in which each of a plurality of address range information is associated with pointer information to the next address area. The generated address profile is stored in the address management RAM 600.

  Incidentally, the pointer 1 is the address range information of the set of the start address 1 and the end address 1, the pointer 2 is the address range information of the set of the start address 2 and the end address 2, the pointer 2 is the address range information of the start address 2, The pointer 3 is a value indicating the address range information of the set of the start address 3 and the end address 3 respectively.

  The address determination / generation unit 330 generates an address related to data to be prefetched based on an address profile (see FIG. 15) stored in the address management RAM 600.

  Further, the address determination / generation unit 330 determines whether the read address from the bus master that is the request source of read access is included in the address range corresponding to each address range information, so that the read address is processed. It is determined whether the read address is related to data.

  In the second embodiment, the address range information storage unit described above corresponds to the address management RAM 600.

  Next, data prefetching processing by the data prefetching processing apparatus 200 will be described with reference to FIG.

  FIG. 16 is a flowchart showing the processing procedure of the data prefetching process. This flowchart is a processing procedure in which step 201 is added to the processing procedure of the first embodiment shown in FIG.

  First, as shown in FIG. 16, the processes of steps S101 to S107 are executed.

  In this case, in step S101 (see P11 in FIG. 5), the DMA control unit internal setting I / F 310 in the DMA control unit 300 stores the address profile in the address management RAM 600.

  In addition, when generating the address information (generated address) related to the processing in step S102 described above, the address determination / generation unit 330 receives the first address range information (start address and end address) of the address address profile from the address management RAM 600. Is read (see P13 in FIG. 5), the address of the data to be prefetched is generated based on the read start address and end address, and the generated address is output to the DMA processing unit 340 (see P14 in FIG. 5). ).

  For example, in the case of the address profile shown in FIG. 15, the address determination / generation unit 330 reads the address range information of the start address 0 and the end address 0 in the address profile, and the data to be prefetched based on the address range information Address (address information) is generated.

  By the way, when step S107 is performed and the same processing as the above-described P4 (see FIG. 5) is performed, in the DMA control unit 300, the address determination / generation unit 330 displays the current stored in the address management RAM 600. It is determined whether the address has reached the end address in the address range information (start address and end address) related to the current prefetch process (step S108).

  Here, when the current address reaches the end address, the data up to the end address with respect to the current prefetch processing target divided data in the plurality of divided data related to the processing target data stored in the external storage device 500. Is pre-read and stored in the temporary buffer 230. On the other hand, when the current address does not reach the end address, the pre-read processing target in the plurality of divided data stored in the external storage device 500 is stored. This means that there is data to be read ahead regarding the divided data.

  If it is determined in step S108 that the current address has not reached the end address in the address range information related to the current prefetching process, the process proceeds to step S109.

  In step S109, the prefetching process is performed on the current divided data to be prefetched.

  On the other hand, in step S108, the address determination / generation unit 330, which has determined that the current address stored in the address management RAM 600 has reached the end address in the address range information related to the current prefetch process, Whether or not the next address area is specified is determined based on the pointer information to the next address area corresponding to the current address range information to be prefetched in (step S201).

  If it is determined in step S201 that the next address area is designated, the process proceeds to step S109.

  In step S109, the address determination / generation unit 330 generates an address to be prefetched based on the address range information of the set of the start address and the end address indicated by the pointer information to the next address area. Then, a prefetch process is performed on the divided data corresponding to the address information.

  For example, when the current address reaches the end address in the address range information of the set of the start address 0 and the end address 0, the address determination / generation unit 330 moves to the next address area corresponding to the address range information. Since the address to be prefetched is generated based on the address range information of the set of the start address 1 and the end address 1 indicated by the pointer 1 as the pointer information, in step S109, the division corresponding to the generated address information A look-ahead process is performed on the data.

  If it is determined in step S201 that the next address area is not designated, the data prefetching process is terminated.

  For example, in the case of the address profile shown in FIG. 15, when the current address range information to be prefetched is the address range information of the set of the start address 3 and the end address 3, the next address area corresponding to this address range information Since the pointer information to indicates that there is “none”, it means that all addresses related to the data to be prefetched (processing target data) are generated, and the prefetching processing for the processing target data has been completed.

  As described above, when “pointer information to the next address area = none (no next address area is specified) corresponding to the address range information to be processed by the current prefetch process, the data prefetch process is terminated.

  (Embodiment 3)

  The data processing system according to the third embodiment has the same configuration as that of the data processing system according to the first embodiment shown in FIG.

  FIG. 17 shows a functional configuration of the data prefetching apparatus according to the third embodiment. This data prefetching device 200 has a configuration in which a download control unit 700 is added to the configuration of the DMA control unit 300 of the data prefetching device 200 of the second embodiment shown in FIG.

  In the third embodiment, the external storage device 500 divides the processing target data into a plurality of storage areas and stores a plurality of address range information corresponding to the plurality of storage areas, as in the second embodiment. Part of address range information (single or plural address range information) is stored. This partial address range information is stored as an address profile.

  The processing target data is divided into, for example, (n + 1), and (n + 1) storage areas of the storage area MA0, the storage area MA1,..., The storage area MA (m),. Is remembered. Note that n and m are positive positive numbers, and the relationship of “n> m” is established.

  The address management RAM 600 stores address range information (a plurality of address range information) excluding the partial address range information among the plurality of address range information corresponding to the plurality of storage areas. This address range information is stored as an address profile.

  The plurality of address range information includes address range information of a set of start address 0 and end address 0 related to the storage area MA0, address range information of a set of start address 1 and end address 1 related to the storage area MA1,. It is assumed that the address range information is a set of start address m and end address m related to area MA (m),..., And the address range information of a set of start address n and end address n related to storage area MA (n). .

  In this case, the address profile of the address range information from “the address range information of the set of start address 0 and end address 0” to “the address range information of the set of start address m and end address m” (this is the first address profile) Is generated by the DMA control unit internal setting I / F 310. The first address profile is stored in the address management RAM 600 by the DMA control unit internal setting I / F 310.

  Of the plurality of address range information, addresses excluding address range information from “address range information of a set of start address 0 and end address 0” to “address range information of a set of start address m and end address m” Range information, that is, an address profile of a part of address range information (single or plural address range information) (this is referred to as a second address profile) is generated by the DMA control unit internal setting I / F 310.

  In the third embodiment, the second address profile is generated for each address range information.

  The second address profile is stored in the external storage device 500 via the DMA processing unit 340, the output control unit 340, and the memory controller 400.

  Here, when m = 3 and n = 6, the address range information from “the address range information of the set of start address 0 and end address 0” to “the address range information of the set of start address 3 and end address 3” The first address profile is stored in the address management RAM 600 (see FIG. 15).

  Further, as shown in FIG. 18, the second address range information for each address range information from “the address range information of the set of start address 4 and end address 4” to “the address range information of the set of start address 6 and end address 6”. The address profile is stored in the external storage device 500.

  Note that the first address profile and the second address profile include address range information (a combination of start address and end address) and pointer information to the next address area, as in the examples shown in FIGS. It is associated information.

  By the way, the pointer information to the next address area corresponding to the address range information of the set of the start address 3 and the end address 3 in the first address profile indicates “None”, and in the second address profile The pointer information to the next address area corresponding to the address range information of the set of the start address 6 and the end address 6 indicates “none”.

  The status stored in the address management RAM 600 stores status information indicating that valid data is stored in the designated address space, and address range information (second address profile) in the external storage device 500. Status information that means

  The download control unit 700 includes a memory 710 that functions as a storage location information storage unit that stores storage location information of the external storage device 500 in which the above-described second address profile (partial address range information) is stored. Based on the storage location information stored in the memory 710, there is a function of address range information reading means for reading the second address profile (partial address range information) from the external storage device 500.

  In addition, the download control unit 700 stores the second address profile read (downloaded) from the external storage device 500 in the memory 710, and determines whether the second address profile is stored in the memory 710. Notification to the unit 330.

  In the third embodiment, the address determination / generation unit 330 requests the download control unit 700 to read the second address profile from the external storage device 500 (download process), and also receives the second address profile from the download control unit 700. In response to the notification that the second address profile is stored, the second address profile stored in the memory 710 is read, and data to be prefetched based on the address range information of the read second address profile Generate an address for

  Next, data prefetch processing by the data prefetch processing apparatus 200 will be described with reference to FIG.

  FIG. 19 is a flowchart showing the processing procedure of the data prefetching process. This flowchart is a processing procedure in which step 301 and step S302 are added to the processing procedure of the second embodiment shown in FIG.

  First, as shown in FIG. 19, the processes of steps S101 to S108 and step S201 are executed.

  The address determination / generation unit 330 that has determined that the next address area is not specified in step S201 determines whether or not to read an address profile (second address profile) from the external storage device 500 (step S301).

  In step S301, the current prefetching process is performed based on the first address profile, and when “address information to the next address area = none” related to the first address profile, the current prefetch process is stored in the address management RAM 600. Whether or not the second address profile is to be read is determined based on the current status.

  On the other hand, when the current prefetching process is performed based on the second address profile, the “next address area” is related to the second address profile stored in the memory 710 in the download control unit 700. Whether or not the next second address profile is to be read is determined based on the “address information”.

  The address determination / generation unit 330 that has determined that the second address profile is to be read from the external storage device 500 in step S301 is read processing (downloading) of the second address profile from the external storage device 500 to the download control unit 700. Request).

  Then, the download control unit 700 reads the second address profile from the external storage device 500 via the DMA processing unit 340, the output control unit 240, and the memory controller 400 based on the storage location information stored in the memory 710. At the same time (step S302), the read second address profile is stored in the memory 710, and further, the address determination / generation unit 330 is notified that the second address profile is stored in the memory 710.

  After step S302 is completed, the process returns to step S108, and data prefetching processing is performed based on the read second address profile.

  That is, since the determination result in step S108 is “NO”, the address determination / generation unit 330 that has received the notification that the second address profile is stored from the download control unit 700 is stored in the memory 710. The second address profile is read, and the address of the data to be prefetched is generated based on the address range information of the read second address profile.

  Then, based on the address generated by the address determination / generation unit 330, data is prefetched from the external storage device 500, and the prefetched data is stored in the temporary buffer 230 (step S109).

  In step S301, since the address information to the next address area corresponding to the address range information of the second address profile that is the current prefetch processing target indicates “None”, the second address from the external storage device 500 is displayed. If it is determined not to read the address profile, the data prefetching process is terminated.

  (Embodiment 4)

  FIG. 20 shows a hardware configuration of the data prefetching apparatus according to the first embodiment shown in FIG.

  As shown in FIG. 20, the data prefetching apparatus 200 includes an input controller 2100 having the function of the input control unit 210 (see FIG. 3), a buffer management controller 2200 having the function of the temporary buffer management unit 220 (see FIG. 3), A buffer 2300 having a function of a buffer 230 (see FIG. 3), an output controller 2400 having a function of an output control unit 240 (see FIG. 3), a DMA controller 2500 having a function of the DMA control unit 300, and a ROM 2600 are provided. These components are connected via an internal bus 2700.

  The DMA controller 2500 includes a register 2510 having the function of the address management register 320. The DMA controller 2500 functions as a DMA control internal setting I / F 310, an address determination / generation unit 330 and a DMA processing unit 340.

  A ROM (Read Only Memory) 2600 stores a data pre-reading processing program (software) 2610 that causes a computer to execute the following processing steps (1) to (4).

  (1) A storage process in which address range information of a storage area where predetermined data to be processed in the external storage device (data storage unit) 500 is stored in a register (address range information storage unit) 2510 in advance.

  (2) A prefetching process in which data prefetching is executed from the external storage device (data storage unit) 500 based on the address range information stored in the register (address range information storage unit) 2510.

  (3) A holding process for holding data pre-read in the pre-reading process in a buffer (data holding unit) 2300.

  (4) Data is read from the buffer (data holding means) 2300 based on the address information related to the predetermined data to be processed output from the requesting bus master (processing device), and the read data is read from the requesting source. Data reading process to be output to the bus master (processing device).

  Incidentally, each of the input controller 2100, the buffer management controller 2200, the output controller 2400, and the DMA controller 2500 includes a RAM (Random Access Memory), not shown, and a data prefetch processing program 2610 stored in the ROM 2600 is illustrated. The program is read into the RAM that is not to be executed. These controllers execute the data prefetch processing program 2610 and cooperate to execute the data prefetch processing.

  The computer means an input controller 2100, a buffer management controller 2200, an output controller 2400, and a DMA controller 2500.

  The storage process described above is realized by the cooperation of the input controller 2100 and the DMA controller 2500, and corresponds to the processes of P1 * 1 and P11 shown in FIG.

  The above-described prefetching process is realized by the cooperation of the DMA controller 2500, the buffer management controller 2200, and the output controller 2400. Each of P13, P14, P1 * 2-P1 * 4, P1 * 6, and P2 shown in FIG. This corresponds to the processing or each processing of P4, P5 * 1 to P5 * 3 and P5 * 5 shown in FIG.

  The holding process described above is realized by the cooperation of the buffer management controller 2200 and the output controller 2400, and corresponds to the P1 * 7 process or the P5 * 6 process shown in FIG.

  The data reading process described above is realized by the cooperation of the DMA controller 2500 and the buffer management controller 2200, and corresponds to each process of P3 * 1, P31, P32, P3 * 2 to P3 * 5 shown in FIG.

  By the way, the data prefetching apparatus 200 of the second embodiment and the third embodiment also has the same hardware configuration as the data prefetching apparatus 200 shown in FIG.

  In the data prefetching apparatus 200 of these embodiments, the DMA controller 2500 includes a RAM that functions as the address management RAM 600 in place of the register 2510.

  In addition, in the data prefetching apparatus 200 according to the third embodiment, the DMA controller 2500 is configured to perform the function of the download control unit 700 in addition to the function of the constituent elements described above. The DMA controller 2500 includes, for example, a register and a buffer that perform the function of the memory 710.

  In the specification of the present application, each function of the data prefetching device is realized and the data prefetching processing program is recorded in the ROM as a recording medium. However, the data prefetching processing program is provided as follows. Is also possible.

  That is, the data pre-reading processing program may be stored and distributed in a computer-readable recording medium such as a DVD-ROM, CD-ROM, MO (magneto-optical disk), or flexible disk. In this case, after the data pre-reading device installs the program recorded on the recording medium, each controller executes the program. As an installation destination of this program, there is a memory such as a RAM or a storage device such as a hard disk. The data prefetching device loads the program stored in the storage device into the main storage device and executes it as necessary.

  Further, after the data prefetching device is connected to a computer such as a server device or a host computer via a communication line (for example, the Internet), the data prefetching device downloads the data prefetching processing program from the server device or the computer. This program may be executed. In this case, the download destination of the program includes a memory such as a RAM and a storage device (recording medium) such as a hard disk. The data prefetching device loads the program stored in the storage device into the main storage device and executes it as necessary.

  The present invention relates to a data prefetching device for prefetching data to be processed processed by a processing device as a single or a plurality of bus masters, an external storage device (data storage means) such as the data prefetching device, the processing device and a hard disk device. ).

1 is a configuration diagram illustrating a configuration of a data processing system according to a first embodiment. FIG. 10 is a diagram for explaining a flow of processing target data related to predetermined processing by a plurality of bus masters according to the first embodiment. 3 is a block diagram showing a functional configuration of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining in detail processing of a DMA control unit in data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining a series of flows of data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining a specific example of data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining a specific example of data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining a specific example of data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining a specific example of data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 6 is a diagram for explaining a specific example of data prefetching processing of the data prefetching apparatus according to Embodiment 1. FIG. 4 is a flowchart illustrating a processing procedure of data prefetching processing of the data prefetching apparatus according to the first embodiment. 6 is a block diagram illustrating a functional configuration of a data prefetching device according to Embodiment 2. FIG. FIG. 10 is a diagram showing an example of allocation of processing target data that is divided and stored in a plurality of storage areas in an external storage device included in a data processing system according to Embodiment 2. It is a figure which shows an example of the address profile memorize | stored in the address management RAM which concerns on Embodiment 2. FIG. 10 is a flowchart showing a processing procedure of data prefetching processing of the data prefetching apparatus according to the second embodiment. FIG. 10 is a block diagram illustrating a functional configuration of a data prefetching device according to a third embodiment. FIG. 10 is a diagram illustrating an example of an address profile stored in an external storage device included in a data processing system according to a third embodiment. 15 is a flowchart illustrating a processing procedure of data prefetching processing of the data prefetching apparatus according to the third embodiment. FIG. 10 is a configuration diagram illustrating a hardware configuration of a data prefetching device according to a fourth embodiment.

Explanation of symbols

1 Data processing system 10-40 Bus master 100 System bus 200 Data prefetching device 210 Input control unit 220 Temporary buffer management unit 230 Temporary buffer 240 Output control unit 300 DMA control unit 310 DMA control unit internal setting I / F
320 Address management register 330 Address determination / generation unit 340 DMA processing unit 400 Memory controller 500 External storage device 600 Address management RAM
700 Download Control Unit 710 Memory 2100 Input Controller 2200 Buffer Management Controller 2300 Buffer 2400 Output Controller 2500 DMA Controller 2510 Register 2600 ROM
2610 Data prefetch processing program

Claims (8)

Address range information storage means for storing address range information of a storage area in which the predetermined data is stored in a data storage means for storing predetermined data to be processed;
Data holding means for holding data prefetched from the data storage means;
Control means for prefetching data from the data storage means based on the address range information stored in the address range information storage means, and writing the prefetched data to the data holding means;
Data is read from the data holding unit based on address information related to the predetermined data output from the processing device that executes predetermined processing on the predetermined data, and the read data is output to the processing device Data reading means to perform,
A data prefetching device characterized by comprising: The control means includes
When not all of the predetermined data is written to the data holding unit, the data that has not been pre-read is stored in the empty area of the data holding unit after the data reading process is performed by the data reading unit. Depending on the storage capacity, data read-ahead processing and write processing are performed.
The data prefetching device according to claim 1. The address range information storage means includes
When the predetermined data is divided and stored in the data storage means, a plurality of address range information corresponding to a plurality of storage areas storing the data after the division is stored,
The control means includes
Performing prefetch processing and write processing of data based on a plurality of address range information stored in the address range information storage means;
The data prefetching device according to claim 1 or 2, characterized by the above. Data storage means for storing predetermined data to be processed;
A processing device for executing predetermined processing on the predetermined data;
A data prefetching device that prefetches data from the data storage means and outputs the prefetched data to the processing device;
Have
The data prefetching device is:
Address range information storage means for storing address range information of a storage area in which the predetermined data of the data storage means is stored;
Data holding means for holding data prefetched from the data storage means;
Control means for prefetching data from the data storage means based on the address range information stored in the address range information storage means, and writing the prefetched data to the data holding means;
Data reading means for reading data from the data holding means based on address information relating to the predetermined data output from the processing device, and outputting the read data to the processing device;
A data processing system comprising: The control means includes
When not all of the predetermined data is written to the data holding unit, the data that has not been pre-read is stored in the empty area of the data holding unit after the data reading process is performed by the data reading unit. Depending on the storage capacity, data read-ahead processing and write processing are performed.
5. A data processing system according to claim 4, wherein: The address range information storage means includes
When the predetermined data is divided and stored in the data storage means, a plurality of address range information corresponding to a plurality of storage areas storing the data after the division is stored,
The control means includes
Performing prefetch processing and write processing of data based on a plurality of address range information stored in the address range information storage means;
6. The data processing system according to claim 4, wherein the data processing system is a data processing system. The data storage means is
Storing some address range information among the plurality of address range information;
The data prefetching device is:
Storage location information storage means for storing storage location information of the data storage means in which the partial address range information is stored;
Address range information reading means for reading address range information from the data storage means based on the storage location information stored in the storage location information storage means;
Further comprising
The control means includes
For data stored in the storage area based on the partial address range information, data pre-read processing and write processing are performed based on the address range information read by the address range information reading means.
The data processing system according to claim 6. A storage process for storing address range information of a storage area in which predetermined data to be processed in the data storage unit is stored in the address range information storage unit;
A prefetching process for performing prefetching of data from the data storage unit based on the address range information stored in the address range information storage unit;
A holding process for holding data pre-read in the pre-reading process in a data holding unit;
A data read process for reading data from the data holding unit based on address information relating to the predetermined data output from the processing device, and outputting the read data to the processing device;
A data prefetching processing program that causes a computer to execute.

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