JP2008287134A - Pulse output circuit, shift register, scanning line driving circuit, data line driving circuit, electro-optical device, and electronic apparatus - Google Patents

Abstract

In a pulse output circuit composed of transistors of the same conductivity type, the gate voltage of the transistor is controlled.
A pulse output circuit having a clock input terminal A, a start pulse input terminal S, and an output terminal Y, a transistor M5 functioning as a switch for outputting a clock CK1 to the output terminal Y, and a transistor M5 An output unit 11D having a capacitive element C1 provided between the gate electrode and the output terminal Y, a transistor M6 functioning as a switch for supplying a ground potential to the output terminal Y, and a voltage based on the start pulse as a transistor. A first gate signal generation unit 12D that supplies the gate electrode of M5, and a second gate signal generation unit 13C that supplies a voltage based on the output pulse output from the output terminal Y to the gate electrode of the transistor M6. In 11D, a capacitive element C2 is provided between the gate electrode of the transistor M5 and the ground.
[Selection] Figure 6

Description

  The present invention relates to a pulse output circuit, a shift register, a scanning line driving circuit, a data line driving circuit, an electro-optical device, and an electronic apparatus.

  Electro-optical devices that perform display using electro-optical changes in electro-optical materials such as liquid crystal and organic EL (electroluminescence) are widely used as display devices for information processing equipment and televisions. Electro-optical devices include an active matrix type in which pixels are driven by pixel switches. That is, in the active matrix type electro-optical device, the pixel electrode is formed corresponding to the intersection of the scanning line extending in the row direction and the data line extending in the column direction. In addition, a pixel switch such as a thin film transistor that is turned on and off according to a scanning signal supplied to the scanning line is interposed between the pixel electrode and the data line at the intersection. On the other hand, a counter electrode is provided so as to face the pixel electrode through the electro-optic material.

  In such an electro-optical device, the scanning line driving circuit includes a shift register and generates a scanning signal for sequentially selecting a plurality of scanning lines. Some shift registers are composed of transistors of the same conductivity type and operate with a two-phase clock signal. For example, Patent Document 1 discloses a configuration shown in FIG. 18, and a timing chart thereof is shown in FIG.

  As shown in FIG. 18A, this shift register includes n-stage unit circuits (pulse output circuits), and each unit circuit is configured as shown in FIG. The shift register sequentially shifts the start pulse SP in accordance with the two-phase clock signals CK1 and CK2 shown in FIG. 19, and outputs output signals OUT1 to OUTn. Note that the high level of the clock signals CK1 and CK2 and the start pulse SP is VDD, and the low level is the ground potential GND (0 V).

  When the start pulse SP becomes high level, the transistor Tr101 is turned on simultaneously with the transistor Tr101 in the first stage unit circuit, and the node β becomes low level. Then, since the transistor Tr102 is turned off, the node α becomes high level (approximately VDD−Vth). Here, Vth is a threshold voltage of the transistor. Since the transistor Tr105 is turned on when the node α goes high, the output signal OUT1 goes high when the clock signal CK1 goes high thereafter. When the output signal OUT1 rises, the node α is further raised to a higher potential by the capacitor 107, the transistor Tr105 is sufficiently turned on, and the output signal OUT1 becomes the VDD level.

Next, when the clock signal CK1 falls, the output signal OUT1 also falls and returns to the low level. Subsequently, when the clock signal CK2 becomes high level, the output signal OUT2 rises. When the output signal OUT2 rises, the first-stage transistor Tr103 is turned on. At this time, since the transistor Tr104 is in an OFF state, the node β of the unit circuit in the first stage becomes a high level. If the node β is maintained at the high level, the transistor Tr102 is turned on, the node α is maintained at the low level, and the transistor Tr105 is maintained in the off state, so that the subsequent change in the clock signal CK1 does not affect the output signal OUT1. . By repeating the above operation, the start pulse SP is transferred.
JP 2004-226429 A (see FIG. 1)

  By the way, when a circuit having a so-called single channel is configured using transistors of the same conductivity type, it is necessary to take into account the amplitude drop due to Vth and the generation of a quasi-stationary leakage current in the inverter which is the basic configuration. For example, the circuit shown in FIG. 20A is a basic inverter composed of only N channels. In this circuit, the transistor M2 has a high resistance and is always on. When the input A is at the low level, the transistor M1 is turned off and the output X is pulled to the high level side. However, the output X is at most stopped at VDD-Vth due to the threshold voltage (hereinafter referred to as Vth) of the transistor M2. When the input A is at the high level, the transistor M1 is turned on and the output X is pulled to the low level side. However, the output X floats slightly from the GND level due to the contention with the resistance of the transistor M2, and the output X passes through the transistors M1, M2. Leakage current flows quasi-steadyly.

  As shown in FIG. 20 (B) or 20 (C), the use of the input A having the opposite phase to the input A can prevent floating and leakage current at the time of low level output, but it can be prevented at the time of high level output. Vth drop is not improved. Therefore, in order to prevent Vth drop, for example, as shown in FIG. 20D, a bootstrap circuit is configured using a transistor M3 functioning as a diode and a capacitor C, and the gate voltage when the transistor M2 is turned on is equal to or higher than VDD + Vth. It is necessary to increase it.

  18B, the output stage 41 including the transistor Tr105, the transistor Tr106, and the capacitor 107 can be regarded as an inverter. As illustrated in FIG. 19, the node α and the node β are in opposite phases. Become a relationship. Therefore, the output stage 41 has a configuration using the same bootstrap effect as that of the circuit shown in FIG. 20D. When the transistor Tr105 is turned on, the voltage of the node α serving as the gate voltage is not less than VDD + Vth. Has been enhanced.

  Here, the voltage actually applied to the node α is 2VDD−Vth obtained by adding the high level voltage (= VDD) of CK1 to the voltage (approximately VDD−Vth) due to the transistor Tr102 being turned off. Since the voltage necessary for the node α to prevent the drop of Vth is VDD + Vth, the difference between the actual voltage and the necessary voltage is VDD-2Vth.

  In general, it is known that when a voltage value applied to a transistor exceeds a rated value, deterioration of characteristics is accelerated and a failure occurrence rate is increased. For this reason, it is not preferable to apply an excessive gate voltage to the transistor. Furthermore, if the gate voltage can be controlled with a simple configuration, a highly reliable circuit can be configured without increasing the cost.

  Accordingly, an object of the present invention is to control the gate voltage of a transistor with a simple configuration in a pulse output circuit configured with transistors of the same conductivity type.

  In order to solve the above-described problem, a pulse output circuit (for example, Ua in FIG. 2) according to the first invention inputs a clock input terminal (for example, A in FIG. 2) for inputting a clock and a start pulse. A pulse output circuit having a start pulse input terminal (for example, S in FIG. 2) and an output terminal (for example, Y in FIG. 2) for outputting an output pulse based on the start pulse in synchronization with the clock. A first transistor (for example, M5 in FIG. 2) that functions as a switch that outputs a voltage based on a clock input from the input terminal to the output terminal, and is provided between the gate electrode and the output terminal of the first transistor. And a second transistor of the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the output terminal. And a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor (eg, M6 in FIG. 2). 1 gate signal generator (for example, 12A in FIG. 2) and a voltage based on the start pulse input to the start pulse input terminal are supplied to the gate electrode of the second transistor in a phase opposite to that of the first gate signal generator. A first gate signal generator (for example, 13A in FIG. 2), and the first gate signal generator has a third transistor (for example, in FIG. 2) with each gate electrode connected to the start pulse input terminal. M1) and a fourth transistor (for example, M8 in FIG. 2) are connected in series, and the voltage at the connection location is supplied to the first transistor, and one end of the fourth transistor Electrode is in contact with the ground.

  According to the present invention, when the start pulse is input, the voltage applied to the gate of the first transistor depends on the ratio of the on-resistance of the third transistor to the fourth transistor, so that the voltage is lower than the conventional voltage. Can do. At this time, the voltage applied to the gate of the first transistor can be controlled with a simple configuration by adjusting the capacity of the fourth transistor.

  In order to solve the above-described problem, a pulse output circuit according to another aspect of the first invention (for example, Ub in FIG. 4) includes a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, A pulse output circuit having an output terminal that outputs an output pulse based on a start pulse in synchronization with a clock, and functions as a switch that outputs a voltage based on the clock input from the clock input terminal to the output terminal. 1 transistor, the first capacitor element provided between the gate electrode of the first transistor and the output terminal, and the first transistor functioning as a switch for supplying a ground potential to the output terminal. An output unit including a second transistor (for example, 11B in FIG. 4) and a start pulse input to the start pulse input terminal A first gate signal generator for supplying a voltage based on the first transistor to the gate electrode of the first transistor; a first gate signal generator for applying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the second transistor; A second gate signal generation unit that supplies the signal in the opposite phase, and the output unit includes a second capacitor element (for example, C2 in FIG. 4) provided between the gate electrode of the first transistor and the ground location. It has been.

  According to the present invention, the voltage applied to the gate of the first transistor when the start pulse is input depends on the ratio between the capacitance of the first capacitive element and the capacitance of the second capacitive element, and thus is lower than in the prior art. It can be a voltage. At this time, the voltage applied to the gate of the first transistor can be controlled with a simple configuration by adjusting the capacitance of the second capacitor.

  In order to solve the above-described problem, a pulse output circuit according to the second invention (for example, Uc in FIG. 5) includes a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, and a start pulse. 1 is a pulse output circuit having an output terminal that outputs an output pulse based on the clock in synchronization with a clock, and functions as a switch that outputs a voltage based on the clock input from the clock input terminal to the output terminal And a first capacitor element provided between the gate electrode and the output terminal of the first transistor, and a second transistor of the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the output terminal Based on an output section (for example, 11C in FIG. 5) including a transistor and a start pulse input to a start pulse input terminal A first gate signal generator (for example, 12C in FIG. 5) that supplies a pressure to the gate electrode of the first transistor, and outputs a voltage based on the output pulse output from the output terminal to the gate electrode of the second transistor A second gate signal generation unit (for example, 13C in FIG. 5) that supplies a phase opposite to that of the pulse, and the first gate signal generation unit includes a third gate signal connected to the start pulse input terminal. The transistor and the fourth transistor are connected in series, the voltage at the connection point is supplied to the first transistor, and the electrode at one end of the fourth transistor is grounded.

  According to the present invention, when the start pulse is input, the voltage applied to the gate of the first transistor depends on the ratio of the on-resistance of the third transistor to the fourth transistor, so that the voltage is lower than the conventional voltage. Can do. At this time, the voltage applied to the gate of the first transistor can be controlled with a simple configuration by adjusting the capacity of the fourth transistor.

  In order to solve the above-described problem, another pulse output circuit according to the second invention (for example, Ud in FIG. 6) includes a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, and A pulse output circuit having an output terminal that outputs an output pulse based on a start pulse in synchronization with a clock, and functions as a switch that outputs a voltage based on the clock input from the clock input terminal to the output terminal. 1 transistor, the first capacitor element provided between the gate electrode of the first transistor and the output terminal, and the first transistor functioning as a switch for supplying a ground potential to the output terminal. A voltage based on the start pulse input to the output section including the second transistor and the start pulse input terminal; A first gate signal generator for supplying to the gate electrode of the transistor, and a second gate signal generator for supplying a voltage based on the output pulse output from the output terminal to the gate electrode of the second transistor in a phase opposite to the output pulse. A second capacitor element is provided between the gate electrode of the first transistor and the ground location.

  According to the present invention, the voltage applied to the gate of the first transistor when the start pulse is input depends on the ratio between the capacitance of the first capacitive element and the capacitance of the second capacitive element, and thus is lower than in the prior art. It can be a voltage. At this time, the voltage applied to the gate of the first transistor can be controlled with a simple configuration by adjusting the capacitance of the second capacitor.

  In order to solve the above-described problem, a pulse output circuit (for example, Ue in FIG. 8) according to the third invention includes a first clock input terminal (for example, A in FIG. 8) for inputting a first clock, A second clock input terminal (for example, UB in FIG. 8) for inputting a second clock having a phase opposite to that of one clock, a start pulse input terminal for inputting a start pulse, and an output pulse based on the start pulse are synchronized with the first clock. And a first transistor that functions as a switch that outputs a voltage based on a clock input from the first clock input terminal to the output terminal, and a first transistor. The same capacitance as the first capacitor element provided between the gate electrode and the output terminal of the first transistor and the first transistor functioning as a switch for supplying a ground potential to the output terminal. And a first gate signal generation unit (for example, in FIG. 8) that supplies a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor. 1C) and a second gate signal generator (for example, supplying a voltage based on the second clock input to the second clock input terminal to the gate electrode of the second transistor based on the output pulse output from the output terminal) E) of FIG. 8, and the first gate signal generation unit includes a third transistor and a fourth transistor, each having a gate electrode connected to the start pulse input terminal, connected in series, and a voltage at the connection portion. Is supplied to the first transistor, and the electrode at one end of the fourth transistor is grounded.

  According to the present invention, when the start pulse is input, the voltage applied to the gate of the first transistor depends on the ratio of the on-resistance of the third transistor to the fourth transistor, so that the voltage is lower than the conventional voltage. Can do. At this time, the voltage applied to the gate of the first transistor can be controlled with a simple configuration by adjusting the capacity of the fourth transistor.

  In order to solve the above-described problem, another aspect of the pulse output circuit according to the third aspect of the invention (for example, Uf in FIG. 9) includes a first clock input terminal for inputting a first clock, and a phase opposite to that of the first clock. A pulse output circuit comprising: a second clock input terminal for inputting the second clock; a start pulse input terminal for inputting a start pulse; and an output terminal for outputting an output pulse based on the start pulse in synchronization with the first clock. A first transistor functioning as a switch for outputting a voltage based on the first clock input from the first clock input terminal to the output terminal, and provided between the gate electrode and the output terminal of the first transistor. And a second transistor having the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the output terminal. An output section, a first gate signal generation section for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor, and a second clock input to the second clock input terminal. And a second gate signal generation unit that supplies a voltage based on the output pulse output from the output terminal to the gate electrode of the second transistor, and the output unit includes the gate electrode of the first transistor and the grounding location. A second capacitor element is provided therebetween.

  According to the present invention, the voltage applied to the gate of the first transistor when the start pulse is input depends on the ratio between the capacitance of the first capacitive element and the capacitance of the second capacitive element, and thus is lower than in the prior art. It can be a voltage. At this time, the voltage applied to the gate of the first transistor can be controlled with a simple configuration by adjusting the capacitance of the second capacitor.

  In order to solve the above-described problem, a pulse output circuit (for example, Ug in FIG. 11) according to a fourth invention includes a first clock input terminal (for example, A in FIG. 11) for inputting a first clock, A third clock input terminal for inputting a third clock that can be masked in phase with one clock (for example, P in FIG. 11), a start pulse input terminal for inputting a start pulse, and an output pulse based on the start pulse as the first clock A pulse output provided with a transfer terminal (for example, Y in FIG. 11) that outputs in synchronization with the output terminal and an output terminal (for example, O in FIG. 11) that outputs an output pulse based on the start pulse in synchronization with the third clock. A first transistor functioning as a switch for outputting a voltage based on the first clock input from the first clock input terminal to the transfer terminal; and a third clock A fifth transistor (for example, M11 in FIG. 11) that functions as a switch that outputs a voltage based on the third clock input from the power terminal to the output terminal, the gate electrode of the first transistor, and the gate of the fifth transistor A first capacitive element provided between the electrode and the transfer terminal; a second transistor of the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the transfer terminal; and a ground potential at the output terminal And an output section (for example, 11G in FIG. 11) having a sixth transistor (for example, M12 in FIG. 11) having the same conductivity type as the fifth transistor that functions as a switch for supplying the voltage to the start pulse input terminal A first voltage is supplied to the gate electrode of the first transistor and the gate electrode of the fifth transistor based on the generated start pulse. And a voltage based on the start pulse input to the start pulse input terminal is supplied to the gate electrode of the second transistor and the gate electrode of the sixth transistor in a phase opposite to that of the first gate signal generation unit. A first gate signal generation unit including a third transistor and a fourth transistor, each having a gate electrode connected to a start pulse input terminal, connected in series. Is supplied to the first transistor, and the electrode at one end of the fourth transistor is grounded.

  According to the present invention, when the start pulse is input, the voltage applied to the gates of the first transistor and the fifth transistor depends on the on-resistance ratio of the third transistor and the fourth transistor. It can be a low voltage. At this time, the voltage applied to the gates of the first transistor and the fifth transistor can be controlled with a simple configuration by adjusting the capability of the fourth transistor.

  In order to solve the above-described problem, a pulse output circuit according to another aspect of the fourth invention (for example, Uh in FIG. 13) has a first clock input terminal for inputting a first clock and an in-phase with the first clock. A third clock input terminal for inputting a maskable third clock, a start pulse input terminal for inputting a start pulse, a transfer terminal for outputting an output pulse based on the start pulse in synchronization with the first clock, and a start pulse A pulse output circuit having an output terminal for outputting an output pulse based on the first clock in synchronization with the third clock, and functioning as a switch for outputting a voltage based on the first clock input from the first clock input terminal to the transfer terminal As a switch for outputting to the output terminal a voltage based on the first transistor and the third clock input from the third clock input terminal As a switch for supplying the ground potential to the transfer terminal, the first transistor provided between the gate electrode of the first transistor, the gate electrode of the fifth transistor and the transfer terminal, and the transfer terminal An output unit comprising: a second transistor having the same conductivity type as the first transistor that functions; and a sixth transistor having the same conductivity type as the fifth transistor that functions as a switch for supplying a ground potential to the output terminal; A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor and the gate electrode of the fifth transistor; and the start pulse input to the start pulse input terminal Is applied to the gate electrode of the second transistor and the gate electrode of the sixth transistor. And a second gate signal generation unit that supplies the second signal signal in a phase opposite to that of the first signal generation unit. The output unit includes a second gate signal generation unit between the gate electrode of the first transistor and the gate electrode of the fifth transistor and the ground point. A capacitive element is provided.

  According to the present invention, when the start pulse is input, the voltage applied to the gates of the first transistor and the fifth transistor depends on the ratio between the capacitance of the first capacitive element and the capacitance of the second capacitive element. Therefore, the voltage can be made lower than before. At this time, the voltage applied to the gates of the first transistor and the fifth transistor can be controlled with a simple configuration by adjusting the capacitance of the second capacitor.

  Next, the shift register according to the present invention is obtained by connecting the above-described pulse output circuit in multiple stages so that the output terminal of the previous stage is connected to the start pulse input terminal of the next stage.

  Next, a scanning line driving circuit according to the present invention includes an electro-optical device including a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines. A plurality of scans that include the above-described shift register and that sequentially select a plurality of scan lines based on a plurality of output signals generated by transferring an input signal using the shift register. Generate a signal.

  Next, a data line driving circuit according to the present invention includes an electro-optical device including a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines. A plurality of pieces of data that include the above-described shift register and that exclusively sequentially select a plurality of data lines based on a plurality of output signals generated by transferring an input signal using the shift register. A line selection signal is generated.

  Next, according to the electro-optical device according to the invention, a plurality of scanning lines, a plurality of data lines, an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines, and the above-described scanning lines A driving circuit or the data line driving circuit described above.

  Next, an electronic apparatus according to the invention includes the above-described electro-optical device. Examples of such electronic devices include a portable information terminal, a mobile phone, a notebook computer, a video camera, and a projector.

<1. First Embodiment>
<1-1: First Mode of Shift Register and Unit Circuit>
First, the shift register 1 according to the present invention will be described. The shift register 1 is composed of transistors of the same conductivity type, and sequentially transfers start pulses STV in accordance with two-phase clock signals CK1 and CK2.

  FIG. 1 shows a block diagram of the shift register 1, and FIG. 2 shows a circuit diagram of the unit circuit Ua (Ua1 to Uan). As shown in FIG. 1, the shift register 1 includes n unit circuits Ua1, Ua2,. The unit circuit Ua includes a clock input terminal A, a set terminal S, a reset terminal R, and an output terminal Y. The first clock signal CK1 and the second clock signal CK2 are alternately supplied to the n unit circuits Ua1 to Uan.

  As shown in FIG. 2, the unit circuit Ua includes an output unit 11A, a first gate signal generation unit 12A, and a second gate signal generation unit 13A. The output unit 11A includes a transistor M5 and a transistor M6 connected in series with the output terminal Y between the clock input terminal A and the ground potential GND, and further between the output terminal Y and the gate of the transistor M5. The provided capacitive element C1 is provided. The transistor M5 functions as a switching element that outputs a clock signal supplied to the clock input terminal A to the output terminal Y, while the transistor M6 functions as a switching element that supplies the ground potential GND to the output terminal Y. In the drawing, the potential of the node α becomes the gate voltage of the transistor M5, and the potential of the node β becomes the gate voltage of the transistor M6.

  Based on the signal supplied to the set terminal S, the first gate signal generator 12A generates a first gate signal to be supplied to the gate of the transistor M5. Specifically, in the first gate signal generation unit 12A, the drain and gate are electrically connected to the power supply potential VDD and the set terminal S, respectively, and the source is electrically connected to the node α, as in the conventional case. And a transistor M2 having a drain electrically connected to the node α, a source grounded, and a gate electrically connected to the node β. Furthermore, in this aspect, the first gate signal generation unit 12A includes a transistor M8 that is connected in parallel to the transistor M2 and whose gate is electrically connected to the set terminal S.

  The second gate signal generator 13A generates a second gate signal to be supplied to the gate of the transistor M6 based on the signal supplied to the set terminal S and the signal supplied to the reset terminal R. Specifically, the second gate signal generation unit 13A includes a transistor M3 and a transistor M4 connected in series with the node β between the power supply potential VDD and the ground potential GND. The gate of the transistor M3 is electrically connected to the reset terminal R, the gate of the transistor M4 is electrically connected to the set terminal S, and the connection node β between the transistors M3 and M4 is electrically connected to the gate of the transistor M6. Is done.

  In the above configuration, when the set terminal S goes high, the transistor M8 is turned on together with the transistors M1 and M4. When the transistor M4 is turned on and the node β becomes low level and the transistor M2 is turned off, the potential of the node α is determined by the power supply voltage VDD and the on-resistance ratio of the transistors M1 and M8. Therefore, the potential of the node α can be made lower than the conventional voltage determined by the power supply voltages VDD and Vth.

  When the node α becomes high level and the transistor M5 is turned on and the clock signal CK1 of the input terminal A becomes high level, the potential of the node α is further increased to the high potential by the capacitor C1, and the transistor M5 is sufficiently The output signal Y becomes VDD.

  At this time, the voltage actually applied to the node α is the high level of CK1 when the voltage drop due to the addition of the transistor M8 is Vct1 and the node α is at the high level (approximately VDD−Vth−Vct1). 2VDD-Vth-Vct1 obtained by adding the voltage (= VDD). Since Vct1 is determined by the on-resistance ratio between the transistor M1 and the transistor M8, the necessary voltage VDD + Vth is secured by adjusting the capabilities of the transistor M1 and the transistor M8, particularly the newly added transistor M8 (that is, Vct <VDD−2Vth), the voltage of the node α, that is, the gate voltage of the transistor M5 can be controlled.

  The operation will be described with reference to the timing chart of the shift register 1 shown in FIG. When the start pulse STV becomes high level, the transistor M1 and the transistor M4 are turned on, and at the same time, the transistor M8 is turned on. Since the transistor M4 is turned on, the node β becomes low level. Then, since the transistor M2 is turned off, the node α becomes a high level. The voltage at this time is (approximately VDD−Vth−Vct1) as described above because the transistor M8 is on. Since the transistor M5 is turned on when the node α goes high, the output signal Y1 goes high when the clock signal CK1 goes high thereafter. When the output signal Y1 rises, the capacitive element C1 pushes the node α to a higher potential, the transistor M5 is sufficiently turned on, and the output signal Y1 becomes the VDD level. The voltage of the node α at this time is (approximately 2VDD−Vth−Vct1) as described above.

  Next, when the clock signal CK1 falls, the output signal Y1 also falls and returns to the low level. Subsequently, when the clock signal CK2 becomes high level, the output signal Y2 rises. When the output signal Y2 rises, the first-stage transistor M3 is turned on via the reset terminal R. At this time, since the transistor M4 is in an off state, the node β of the unit circuit in the first stage becomes a high level. If the node β is kept at the high level, the transistor M2 is kept on, the node α is kept at the low level, and the transistor M5 is kept off, so that the subsequent change in the clock signal CK1 affects the output signal Y. do not do. By repeating the above operation, the start pulse STV is transferred.

Note that in the case where the transistors M1 to M6 and M8 are N-channel type, the first clock signals CK1 and CK2 are preferably two-phase signals in which high-level periods do not overlap as shown in FIG. That is, the high level period of the first clock signal CK1 is included in the low level period of the second clock signal CK2, and the high level period of the second clock signal CK2 is included in the low level period of the first clock signal CK1.
<1-2: Second Mode of Unit Circuit>
A unit circuit Ub shown in FIG. 4 may be employed instead of the unit circuit Ua of the above-described embodiment. The unit circuit Ub includes a capacitive element C2 between the gate of the transistor M5 and the ground potential GND in the output unit 11B. On the other hand, the first gate signal generator 12B has the same configuration as the conventional one without using the transistor M8. Further, the second gate signal generation unit 13A has the same configuration as the conventional one.

  In the above configuration, when the set terminal S becomes high level, the transistor M4 is turned on together with the transistor M1. When the transistor M4 is turned on, the node β becomes low level, and when the transistor M2 is turned off, the node α becomes high level. The potential at this time is (approximately VDD-Vth) as in the prior art. When the node α is at a high level and the clock signal CK1 of the input terminal A is at a high level with the transistor M5 turned on, the potential of the node α is further increased to a higher potential by the capacitor C1, and the transistor M5 Is sufficiently turned on, and the output signal Y becomes VDD.

The voltage of the node α at this time is determined by the ratio of the capacitance of the capacitive element C1 and the capacitance of the capacitive element C2. That is, since the charge is redistributed between the capacitive element C1 and the capacitive element C2, the voltage value is lower than that in the conventional case. Thus, the gate voltage of the transistor M5 can be controlled by adjusting the capacitances of the capacitive element C1 and the capacitive element C2, particularly the newly added capacitive element C2.
In this example, the ground potential GND is supplied to one end of the capacitive element C2. However, since the capacitive element C2 is used to reduce the voltage of the node α by redistribution of charges, it is supplied to one end of the capacitive element C2. The potential to be applied may be a fixed potential lower than the power supply voltage VDD.

<2. Second Embodiment>
<2-1: First Mode of Unit Circuit>
The shift register of the second embodiment can have the same configuration as the shift register of the first embodiment shown in FIG. FIG. 5 shows a circuit diagram of the unit circuit Uc (Uc1 to Ucn) of the second embodiment. As shown in the figure, the unit circuit Uc includes an output unit 11C, a first gate signal generation unit 12C, and a second gate signal generation unit 13C. The output unit 11C includes a transistor M5 and a transistor M6 connected in series with the output terminal Y between the clock input terminal A and the ground potential GND, and further between the output terminal Y and the gate of the transistor M5. The provided capacitive element C1 is provided. The transistor M5 functions as a switching element that outputs a clock signal supplied to the clock input terminal A to the output terminal Y, while the transistor M6 functions as a switching element that supplies the ground potential GND to the output terminal Y. In the drawing, the potential of the node α becomes the gate voltage of the transistor M5, and the potential of the node β becomes the gate voltage of the transistor M6.

  The first gate signal generation unit 12C generates a first gate signal to be supplied to the gate of the transistor M5 based on the signal supplied to the set terminal S and the signal supplied to the reset terminal R. Specifically, the first gate signal generator 12C includes a transistor M1 having a diode connected to the set terminal S, a source electrically connected to the node α, a drain electrically connected to the node α, and a source grounded. And a transistor M2 whose gate is electrically connected to the reset terminal R, and a transistor M8 which is connected in parallel to the transistor M2 and whose gate is electrically connected to the set terminal S.

  The second gate signal generation unit 13C generates a second gate signal to be supplied to the gate of the transistor M6 based on the signal supplied to the output terminal Y. Specifically, the second gate signal generation unit 13C is connected in series with the transistor M3 that is diode-connected to the power supply potential VDD and the transistor M3 across the node β, the gate is electrically connected to the output terminal Y, and the source , And a grounded transistor M4. The node β is normally at a high level (approximately VDD−Vth) by the diode-connected transistor M3. For this reason, in a normal state, the transistor M6 is turned on, and the output terminal Y is at a low level output. Here, by setting the on-resistance of the transistor M3 to be sufficiently higher than M4, the node β becomes low level only while the output signal Y of its own stage is high level.

  In the above configuration, when the set terminal S becomes high level, the transistor M8 is turned on, the node α becomes high level via the diode-connected transistor M1, and is determined by the resistance ratio of the transistor M1 and the transistor M8. Potential (approximately VDD−Vth−Vct1). At this time, since the output signal Y of the next stage (the reset terminal R of the own stage) is at a low level, the transistor M2 is turned off. Since the transistor M5 is turned on when the node α goes high, the output signal Y goes high when the clock signal CK1 of the input terminal A goes high thereafter. Then, the potential of the node α is further increased to the higher potential (2VDD−Vth−Vct1) by the capacitive element C1, the transistor M5 is sufficiently turned on, and the output signal Y becomes VDD.

  When the output signal Y becomes high level, the transistor M4 is turned on, the node β falls to low level, and the transistor M6 is turned off. Thereafter, when the clock signal CK1 at the input terminal A falls to the low level, the output signal Y also falls to the low level. Subsequently, when the clock signal CK2 input to the next stage becomes a high level, the output signal Y (the reset signal R of the own stage) rises and the transistor M2 of the own stage is turned on. At this time, since the set terminal S has fallen to the low level, the node α returns to the low level. Since the node α does not have a leakage path from the power supply voltage, it keeps 0V thereafter, and the transistor M5 is kept off, so that the subsequent change of the clock signal CK1 does not affect the output signal Y. In this way, the start pulse STV is sequentially transferred.

  Thus, in this embodiment, Vct1 is determined by the on-resistance ratio of the transistor M1 and the transistor M8. Therefore, the necessary voltage can be adjusted by adjusting the capabilities of the transistor M1 and the transistor M8, particularly the newly added transistor M8. In a state where VDD + Vth is secured (that is, Vct <VDD−2Vth), the voltage of the node α, that is, the gate voltage of the transistor M5 can be controlled.

  Further, in this circuit, since the transistor M3 is always on, the node β is low level only when the output signal Y becomes active, but the node β is stably high level during other periods. . Therefore, there is an advantage that no malfunction occurs even when the threshold voltage Vth is significantly lowered. When the output signal Y becomes high level, a through current flows from the power supply VDD to the ground potential GND via the transistors M3 and M4. However, there is a practical problem by reducing the driving capability of the transistor M3 as much as possible. No.

<2-2: Second Mode of Unit Circuit>
A unit circuit Ud shown in FIG. 6 may be employed instead of the unit circuit Uc of the above-described embodiment. The unit circuit Ud includes a capacitive element C2 in the output unit 11D between the gate of the transistor M5 and the ground potential GND. On the other hand, the first gate signal generation unit 12D does not include the transistor M8. The second gate signal generation unit 13C has the same configuration as that of the first mode.

  In the above configuration, when the set terminal S becomes high level, the node α becomes high level (approximately VDD−Vth) via the diode-connected M1. At this time, since the output signal Y of the next stage (the reset terminal R of the own stage) is at a low level, the transistor M2 is turned off. Since the transistor M5 is turned on when the node α becomes high level, when the clock signal CK1 of the input terminal A thereafter becomes high level, the potential of the node α is further increased to a higher potential by the capacitor C1, and the transistor M5 Is sufficiently turned on, and the output signal Y becomes VDD.

The voltage of the node α at this time is determined by the ratio of the capacitance of the capacitive element C1 and the capacitance of the capacitive element C2. That is, since the charge is redistributed between the capacitive element C1 and the capacitive element C2, the voltage value is lower than that in the conventional case. Thus, the gate voltage of the transistor M5 can be controlled by adjusting the capacitances of the capacitive element C1 and the capacitive element C2, particularly the capacitive element C2.
In this example, the ground potential GND is supplied to one end of the capacitive element C2. However, since the capacitive element C2 is used to reduce the voltage of the node α by redistribution of charges, it is supplied to one end of the capacitive element C2. The potential to be applied may be a fixed potential lower than the power supply voltage VDD.

<3. Third Embodiment>
<3-1: First Mode of Shift Register and Unit Circuit>
A shift register 2 according to the third embodiment will be described. The shift register 2 is composed of transistors of the same conductivity type, and sequentially transfers start pulses STV in accordance with CK2 having a phase opposite to that of the two-phase clock signals CK1 and CK1.

  FIG. 7 shows a block diagram of the shift register 2, and FIG. 8 shows a circuit diagram of the unit circuits Ue (Ue1 to Uen). As shown in FIG. 7, the shift register 2 includes n unit circuits Ue1, Ue2,. The unit circuit Ue is supplied with the clock input terminal A to which one of the first clock signal CK1 and the second clock signal CK2 is supplied, and the other of the first clock signal CK1 and the second high level lock signal CK2. Clock input terminal B, set terminal S, reset terminal R, and output terminal Y. When the logic level of the set terminal S becomes high level (VDD in this example), when the signal supplied to the clock input terminal A becomes high level, the logic level of the output signal Y becomes high level, and the reset terminal S When the logic level becomes high, the logic level of the output signal Y becomes low.

  As shown in FIG. 8, the unit circuit Ue includes an output unit 11C, a first gate signal generation unit 12C, and a second gate signal generation unit 13E. The output unit 11C includes a transistor M5 and a transistor M6 connected in series with the output terminal Y between the clock input terminal A and the ground potential GND, and further between the output terminal Y and the gate of the transistor M5. The provided capacitive element C1 is provided. The transistor M5 functions as a switching element that outputs a clock signal supplied to the clock input terminal A to the output terminal Y, while the transistor M6 functions as a switching element that supplies the ground potential GND to the output terminal Y. In the drawing, the potential of the node α becomes the gate voltage of the transistor M5, and the potential of the node β becomes the gate voltage of the transistor M6.

  The first gate signal generation unit 12C generates a first gate signal to be supplied to the gate of the transistor M5 based on the signal supplied to the set terminal S and the signal supplied to the reset terminal R. Specifically, the first gate signal generator 12C includes a transistor M1 having a diode connected to the set terminal S, a source electrically connected to the node α, a drain electrically connected to the node α, and a source grounded. And a transistor M2 whose gate is electrically connected to the reset terminal R, and a transistor M8 which is connected in parallel to the transistor M2 and whose gate is electrically connected to the set terminal S.

  The second gate signal generator 13E generates a second gate signal to be supplied to the gate of the transistor M6 based on the clock signal supplied to the clock input terminal B and the signal supplied to the output terminal Y. Specifically, the second gate signal generation unit 13E includes a transistor M3 whose drain is electrically connected to the power supply potential VDD and whose gate is electrically connected to the clock input terminal B, and a transistor M3 series across the node β. , A transistor whose gate is electrically connected to the output terminal Y, and whose source is grounded.

  The node β is normally at a high level (approximately VDD−Vth) because the transistor M3 is repeatedly turned on by the clock signal CK2 input to the clock input terminal B. For this reason, in a normal state, the transistor M6 is turned on, and the output terminal Y is at a low level output. Here, by setting the on-resistance of the transistor M3 to be sufficiently higher than M4, the node β becomes low level only while the output signal Y of its own stage is high level.

  In the above configuration, when the set terminal S becomes high level, the transistor M8 is turned on, the node α becomes high level via the diode-connected transistor M1, and the ratio of the resistances of the transistors M1 and M8 is determined. The potential is determined (approximately VDD−Vth−Vct1). At this time, since the output signal Y of the next stage (the reset terminal R of the own stage) is at a low level, the transistor M2 is turned off. Since the transistor M5 is turned on when the node α goes high, the output signal Y goes high when the clock signal CK1 of the input terminal A goes high thereafter. Then, the potential of the node α is further increased to the higher potential (2VDD−Vth−Vct1) by the capacitive element C1, the transistor M5 is sufficiently turned on, and the output signal Y becomes VDD.

  When the output signal Y becomes high level, the transistor M4 is turned on, the node β falls to low level, and the transistor M6 is turned off. Thereafter, when the clock signal CK1 at the input terminal A falls to the low level, the output signal Y also falls to the low level. Subsequently, when the clock signal CK2 input to the next stage becomes a high level, the output signal Y (the reset signal R of the own stage) rises and the transistor M2 of the own stage is turned on. At this time, since the set terminal S has fallen to the low level, the node α returns to the low level. Since the node α does not have a leakage path from the power supply voltage, it keeps 0V thereafter, and the transistor M5 is kept off, so that the subsequent change of the clock signal CK1 does not affect the output signal Y. In this way, the start pulse STV is sequentially transferred.

  Thus, in this embodiment, Vct1 is determined by the on-resistance ratio of the transistor M1 and the transistor M8. Therefore, the necessary voltage VDD + Vth is secured by adjusting the capabilities of the transistors M1 and M8, particularly the transistor M8. In the state (that is, Vct <VDD−2Vth), the voltage of the node α, that is, the gate voltage of the transistor M5 can be controlled. Although this circuit is somewhat inferior in stability to a low Vth as compared with the circuit shown in the second embodiment, it does not generate leakage current via the transistor M3 and the transistor M4 when the transistor M4 is turned on, which occurs in the second embodiment. Has advantages.

<3-2: Second Mode of Unit Circuit>
A unit circuit Uf shown in FIG. 9 may be employed instead of the unit circuit Ue of the above-described embodiment. In the output unit 11D, the unit circuit Uf includes a capacitive element C2 between the gate of the transistor M5 and the ground potential GND. On the other hand, the first gate signal generation unit 12D does not include the transistor M8. The second gate signal generation unit 13E has the same configuration as that of the first mode.

  In the above configuration, when the set terminal S becomes high level, the node α becomes high level (approximately VDD−Vth) via the diode-connected M1. At this time, since the output signal Y of the next stage (the reset terminal R of the own stage) is at a low level, the transistor M2 is turned off. Since the transistor M5 is turned on when the node α becomes high level, when the clock signal CK1 of the input terminal A thereafter becomes high level, the potential of the node α is further increased to a higher potential by the capacitor C1, and the transistor M5 Is sufficiently turned on, and the output signal Y becomes VDD.

The voltage of the node α at this time is determined by the ratio of the capacitance of the capacitive element C1 and the capacitance of the capacitive element C2. That is, since the charge is redistributed between the capacitive element C1 and the capacitive element C2, the voltage value is lower than that in the conventional case. Thus, the gate voltage of the transistor M5 can be controlled by adjusting the capacitances of the capacitive element C1 and the capacitive element C2, particularly the capacitive element C2.
In this example, the ground potential GND is supplied to one end of the capacitive element C2. However, since the capacitive element C2 is used to reduce the voltage of the node α by redistribution of charges, it is supplied to one end of the capacitive element C2. The potential to be applied may be a fixed potential lower than the power supply voltage VDD.

<4. Fourth Embodiment>
<4-1: First Mode of Shift Register and Unit Circuit>
A shift register 3 according to the fourth embodiment will be described. The shift register 3 is composed of transistors of the same conductivity type, and sequentially transfers start pulses STV in accordance with two-phase clock signals CK1 and CK2. This embodiment is an example in which a part of a shift pulse is masked using a partial display clock signal.

  FIG. 10 shows a block diagram of the shift register 3, and FIG. 11 shows a circuit diagram of the unit circuit Ug (Ug1 to Ugn). As shown in FIG. 10, the shift register 3 includes n unit circuits Ug1, Ug2,..., Ugn. The unit circuit Ug is supplied with a clock input terminal A to which one of the first clock signal CK1 and the second clock signal CK2 is supplied, and one of the first partial display clock signal P1 and the second partial display clock signal P2. Clock input terminal P, set terminal S, reset terminal R, transfer signal terminal Y, and output terminal O. In this embodiment, the output from the terminal Y is involved in the transfer operation, and an output terminal O for shift pulse output is provided separately.

  The unit circuit Ug includes an output unit 11G, a first gate signal generation unit 12A, and a second gate signal generation unit 13A. The output unit 11G includes a transistor M11 and a transistor M12 connected in series between the input terminal P of the partial display clock and the ground potential GND in addition to the output unit 11A. The same signals as the gates of the transistors M5 and M6 are input to the gates of the transistors M11 and M12, respectively. The drain of the transistor M11 is electrically connected to the clock input terminal P, the source is electrically connected to the drain of the transistor M12 across the output terminal O, and the source of the transistor M12 is grounded. Further, the source potential of the transistor M5 becomes the output of the transfer signal Y.

  In the circuit of this figure, since the drive circuit for the transfer signal Y of the output stage 11G and the drive circuit for the output signal O are considered to have the same role, the transistor M5 and the transistor M11, and the transistor M6 and the transistor M12, respectively. Only the input clock signal is different. Therefore, the transfer signal Y based on the clock signal CK1 input from the input terminal A is output regardless of the partial display clock signal P, similarly to the output signal Y in the first embodiment. On the other hand, the output signal O of this circuit is output similarly to the output signal Y in the first embodiment only when the partial display clock signal P is input. Therefore, the output signal Y can be partially masked by masking the partial display clock signal P at a desired timing.

  That is, as shown in the timing chart of FIG. 12, the shift register 3 generates a shift pulse only during a period in which the partial display clock signal P is input. The partial clock signal P is generated based on the same clock as the clock signal CK. Specifically, the clock signal CK1 and the partial display clock signal P1 have the same phase, and the clock signal CK2 and the partial display clock signal P2 have the same phase. When the shift register 3 using such a partial display clock is applied to a scanning signal generating device, it applies a partial display clock only to the row corresponding to the display region, thereby making any non-continuous row a non-display region. Will be able to.

  Also in this embodiment, the voltage applied to the node α is equal to Vct1 when the voltage drop due to the addition of the transistor M8 is Vct1, and the voltage of the CK1 is approximately equal to VDD−Vth−Vct1. 2VDD-Vth-Vct1 is obtained by adding the high level voltage (= VDD). Since Vct1 is determined by the on-resistance ratio of the transistors M1 and M8, the necessary voltage VDD + Vth is secured by adjusting the capabilities of the transistors M1 and M8, particularly the transistor M8 (that is, Vct <VDD−2Vth). ), The voltage of the node α, that is, the gate voltages of the transistors M5 and M11 can be controlled.

<4-2: Second Mode of Unit Circuit>
A unit circuit Uh shown in FIG. 13 may be employed instead of the unit circuit Ug of the above-described embodiment. The unit circuit Uh includes a capacitive element C2 between the gate of the transistor M5 and the ground potential GND in the output unit 11H. On the other hand, the first gate signal generation unit 12B does not include the transistor M8. The second gate signal generation unit 13A has the same configuration as that of the first mode.

  Also in this aspect, the output signal O can be masked by the partial display clock P as in the first aspect. Similarly to the other embodiments, the voltage at the node α is determined by the ratio between the capacitance of the capacitive element C1 and the capacitance of the capacitive element C2. That is, since the charge is redistributed between the capacitive element C1 and the capacitive element C2, the voltage value is lower than that in the conventional case. Thus, the gate voltages of the transistors M5 and M11 can be controlled by adjusting the capacitances of the capacitive elements C1 and C2, particularly the capacitive element C2.

  In each of the above-described embodiments, an N-channel transistor is used. However, a P-channel transistor may be used. Further, it is possible to make modifications such as adding a bidirectional function and a reset function, or making part of the circuit dual gated in order to increase leakage resistance.

<5. Electro-optical device>
Next, an electro-optical device using the above-described shift registers 1 to 3 in a drive circuit will be described. FIG. 14 is a block diagram showing an electrical configuration of the electro-optical device 500 according to the present invention. The electro-optical device 500 uses liquid crystal as an electro-optical material. The electro-optical device 500 includes a liquid crystal panel AA as a main part. The liquid crystal panel AA is bonded to an element substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element and a counter substrate with the electrode formation surfaces facing each other and maintaining a certain gap. However, liquid crystal is sandwiched between the gaps.

  The electro-optical device 500 includes a liquid crystal panel AA, a timing generation circuit 300, and an image processing circuit 400. The liquid crystal panel AA includes an image display area A, a scanning line driving circuit 100, a data line driving circuit 200, a sampling circuit 240, and an image signal supply line L on the element substrate. The input image data D supplied to the electro-optical device 500 is, for example, 6-bit RGB data given in a parallel format. The timing generation circuit 300 is synchronized with the input image data D, and includes a first Y clock signal YCK1, a second Y clock signal YCK2, a first X clock signal XCK1, a second X clock signal XCK2, a Y transfer start pulse DY, and an X transfer start pulse DX. Is supplied to the scanning line driving circuit 100 and the data line driving circuit 200. The timing generation circuit 300 generates various timing signals for controlling the image processing circuit 400 and outputs them. The Y transfer start pulse DY is a pulse for instructing the start of selection of the scanning line 52, while the X transfer start pulse DX is a pulse for instructing the start of selection of the data line 53.

  Next, the image processing circuit 400 performs gamma correction and the like on the input image data D in consideration of the light transmission characteristics of the liquid crystal panel, and then D / A converts the RGB image data to generate an image signal VID. And supplied to the liquid crystal panel AA.

  Next, in the image display area A, as shown in FIG. 14, m (m is a natural number of 2 or more) scanning lines 52 are formed in parallel along the X direction, while n (N is a natural number greater than or equal to 2) The data lines 53 are formed in parallel along the Y direction. In the vicinity of the intersection of the scanning line 52 and the data line 53, the gate of the TFT 50 is connected to the scanning line 52, while the source of the TFT 50 is connected to the data line 53 and the drain of the TFT 50 is connected to the pixel electrode 56. Connected. Each pixel includes a pixel electrode 56, a counter electrode formed on a counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, the pixels are arranged in a matrix corresponding to each intersection of the scanning line 52 and the data line 53.

  Further, scanning signals G1, G2,..., Gm are applied to each scanning line 52 to which the gate of the TFT 50 is connected in a pulse-like manner in a line sequential manner. For this reason, when a scanning signal is supplied to a certain scanning line 52, the TFT 50 connected to the scanning line is turned on, so that the image signals X1, X2,. After being written in order to the corresponding pixels, they are held for a predetermined period.

  In the above configuration, the shift registers 1 to 3 described in the first to fourth embodiments can be used for the scanning line driving circuit 100 and the data line driving circuit 200. When applied to the scanning line driving circuit 100, the first Y clock signal YCK1 and the second Y clock signal YCK2 are used as the first clock signal CK1 and the second clock signal CK2, and the Y transfer start pulse DY is used as the start pulse STV. Good. When applied to the data line driving circuit 200, the first X clock signal XCK1 and the second X clock signal XCK2 are used as the first clock signal CK1 and the second clock signal CK2, and the X transfer start pulse DX is used as the start pulse STV. Use it.

Note that the above-described electro-optical device 500 is a liquid crystal display device using liquid crystal as an electro-optical material, and this liquid crystal display device can be applied to any of a transmissive type, a reflective type, and a transflective type. Further, the present invention can also be applied to a passive matrix system in which only the active matrix system is used. Furthermore, the electro-optical device can be applied to various devices such as an organic EL device, a fluorescent display tube, a plasma display panel, and a digital mirror device.
<6. Electronic equipment>
Next, some electronic apparatuses using the electro-optical device according to the above-described embodiment will be described.

  FIG. 15 shows a configuration of a mobile personal computer to which the electro-optical device 500 is applied. The personal computer 1000 includes an electro-optical device 500 as a display unit and a main body 1010. The main body 1010 is provided with a power switch 1001 and a keyboard 1002.

  FIG. 16 shows a configuration of a projector using the electro-optical device 500. As shown in this figure, a projector 2000 is provided with a lamp unit 2002 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2002 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2006 and two dichroic mirrors 2008 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Here, the light valves 100R, 100G, and 100B are basically the same as the electro-optical device 500 according to the above-described embodiment, that is, the transmissive liquid crystal display device. That is, each of the light valves 100R, 100G, and 100B functions as an optical modulator that generates RGB primary color images. Further, since the light path of B light is longer than that of other R and G lights, in order to prevent loss thereof, light is guided through a relay lens system 2021 including an incident lens 2022, a relay lens 2023, and an exit lens 2024. It is burned. The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2012 from three directions. In the dichroic prism 2012, R and B light is refracted at 90 degrees, while G light goes straight. As a result, a color image obtained by combining the primary color images is projected onto the screen 2020 via the projection lens 2014.

  FIG. 17 shows a configuration of a video camera using the electro-optical device 500. As shown in this figure, the main body of the video camera 3000 is provided with an optical system 3012 in addition to the electro-optical device 500 used as the monitor 510. Here, the electro-optical device 500 is rotatably attached to a hinge 3016 about a shaft 3024, and the hinge 3016 is configured to open and close with respect to the main body 3010 about the shaft 3022. Yes.

  Note that electronic devices to which the electro-optical device 500 is applied include, in addition to those shown in FIGS. 15 to 17, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, Examples include electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices equipped with touch panels.

It is a block diagram which shows the structure of the shift register 1 which concerns on 1st Embodiment. 3 is a circuit diagram showing a configuration of a unit circuit Ua used in the shift register 1. FIG. 4 is a timing chart of the shift register 1 using the same circuit. It is a circuit diagram which shows the structure of the unit circuit Ub. It is a circuit diagram which shows the structure of the unit circuit Uc. It is a circuit diagram which shows the structure of the unit circuit Ud. It is a block diagram which shows the structure of the shift register 2 which concerns on 3rd Embodiment. It is a circuit diagram which shows the structure of the unit circuit Ue. It is a circuit diagram which shows the structure of the unit circuit Uf. It is a block diagram which shows the structure of the shift register 2 which concerns on 4th Embodiment. 3 is a circuit diagram showing a configuration of a unit circuit Ug used for the shift register 3. FIG. 4 is a timing chart of the shift register 3 using the same circuit. It is a circuit diagram which shows the structure of the unit circuit Uh. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. It is a perspective view which shows the structure of the personal computer which is an example of the electronic device to which the same apparatus is applied. It is a block diagram of the projector which is an example of the electronic device to which the apparatus is applied. It is a block diagram of the video camera which is an example of the electronic device to which the same apparatus is applied. It is a block diagram which shows an example of the conventional shift register. It is a timing chart which shows operation | movement of the conventional shift register. It is a circuit diagram of the inverter comprised by the single channel.

Explanation of symbols

  1, 2, 3... Shift register, CK1... First clock signal, CK2... Second clock signal, Ua to Uh... Unit circuit, Y1 to Yn ... output signal, STV ... start pulse, 11. DESCRIPTION OF SYMBOLS 1 gate signal generation part, 13 ... 2nd gate signal generation part, M1-M6, M8 ... Transistor, C1, C2 ... Capacitance element, 100 ... Scanning line drive circuit, 200 ... Data line drive circuit, 500 ... Electro-optical apparatus.

Claims (13)

A pulse output circuit comprising a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, and an output terminal for outputting an output pulse based on the start pulse in synchronization with the clock,
A first transistor functioning as a switch for outputting a voltage based on a clock input from the clock input terminal to the output terminal; and a first transistor provided between the gate electrode of the first transistor and the output terminal. And an output section including a second transistor having the same conductivity type as the first transistor, which functions as a switch for supplying a ground potential to the output terminal,
A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor;
A second gate signal generation unit that supplies a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the second transistor in a phase opposite to that of the first gate signal generation unit;
The first gate signal generator is
A third transistor and a fourth transistor, each having a gate electrode connected to the start pulse input terminal, are connected in series, and the voltage at the connection location is supplied to the first transistor. A pulse output circuit characterized in that an electrode at one end is grounded. A pulse output circuit comprising a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, and an output terminal for outputting an output pulse based on the start pulse in synchronization with the clock,
A first transistor functioning as a switch for outputting a voltage based on a clock input from the clock input terminal to the output terminal; and a first transistor provided between the gate electrode of the first transistor and the output terminal. And an output section including a second transistor having the same conductivity type as the first transistor, which functions as a switch for supplying a ground potential to the output terminal,
A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor;
A second gate signal generation unit that supplies a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the second transistor in a phase opposite to that of the first gate signal generation unit;
The pulse output circuit, wherein the output section includes a second capacitor element between a gate electrode of the first transistor and a grounded portion. A pulse output circuit comprising a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, and an output terminal for outputting an output pulse based on the start pulse in synchronization with the clock,
A first transistor functioning as a switch for outputting a voltage based on a clock input from the clock input terminal to the output terminal; and a first transistor provided between the gate electrode of the first transistor and the output terminal. And an output section including a second transistor having the same conductivity type as the first transistor, which functions as a switch for supplying a ground potential to the output terminal,
A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor;
A second gate signal generator that supplies a voltage based on the output pulse output from the output terminal to the gate electrode of the second transistor in a phase opposite to that of the output pulse;
The first gate signal generator is
A third transistor and a fourth transistor, each having a gate electrode connected to the start pulse input terminal, are connected in series, and the voltage at the connection location is supplied to the first transistor. A pulse output circuit characterized in that an electrode at one end is grounded. A pulse output circuit comprising a clock input terminal for inputting a clock, a start pulse input terminal for inputting a start pulse, and an output terminal for outputting an output pulse based on the start pulse in synchronization with the clock,
A first transistor functioning as a switch for outputting a voltage based on a clock input from the clock input terminal to the output terminal; and a first transistor provided between the gate electrode of the first transistor and the output terminal. And an output section including a second transistor having the same conductivity type as the first transistor, which functions as a switch for supplying a ground potential to the output terminal,
A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor;
A second gate signal generator that supplies a voltage based on the output pulse output from the output terminal to the gate electrode of the second transistor in a phase opposite to that of the output pulse;
The pulse output circuit, wherein the output section includes a second capacitor element between a gate electrode of the first transistor and a grounded portion. A first clock input terminal for inputting a first clock, a second clock input terminal for inputting a second clock having a phase opposite to that of the first clock, a start pulse input terminal for inputting a start pulse, and an output based on the start pulse A pulse output circuit comprising an output terminal for outputting a pulse in synchronization with the first clock,
Provided between the first transistor functioning as a switch for outputting a voltage based on the clock input from the first clock input terminal to the output terminal, and between the gate electrode of the first transistor and the output terminal An output unit including a first capacitor, and a second transistor having the same conductivity type as the first transistor, which functions as a switch for supplying a ground potential to the output terminal;
A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor;
A second gate signal generation unit configured to supply a voltage based on the second clock input to the second clock input terminal to the gate electrode of the second transistor based on an output pulse output from the output terminal; ,
The first gate signal generator is
A third transistor and a fourth transistor, each having a gate electrode connected to the start pulse input terminal, are connected in series, and the voltage at the connection location is supplied to the first transistor. A pulse output circuit characterized in that an electrode at one end is grounded. A first clock input terminal for inputting a first clock, a second clock input terminal for inputting a second clock having a phase opposite to that of the first clock, a start pulse input terminal for inputting a start pulse, and an output based on the start pulse A pulse output circuit comprising an output terminal for outputting a pulse in synchronization with the first clock,
Provided between the first transistor functioning as a switch for outputting a voltage based on the first clock input from the first clock input terminal to the output terminal, and between the gate electrode of the first transistor and the output terminal An output unit including the first capacitor element and a second transistor having the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the output terminal;
A first gate signal generator for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the first transistor;
A second gate signal generation unit configured to supply a voltage based on the second clock input to the second clock input terminal to the gate electrode of the second transistor based on an output pulse output from the output terminal; ,
The pulse output circuit, wherein the output section includes a second capacitor element between a gate electrode of the first transistor and a grounded portion. A first clock input terminal for inputting a first clock; a third clock input terminal for inputting a third clock maskable in phase with the first clock; a start pulse input terminal for inputting a start pulse; A pulse output circuit including a transfer terminal that outputs an output pulse based on the first clock in synchronization with an output terminal that outputs an output pulse based on a start pulse in synchronization with the third clock,
A first transistor functioning as a switch for outputting a voltage based on the first clock input from the first clock input terminal to the transfer terminal; and a voltage based on the third clock input from the third clock input terminal. A fifth transistor that functions as a switch that outputs to the output terminal; a gate electrode of the first transistor; a first capacitor element provided between the gate electrode of the fifth transistor and the transfer terminal; The second transistor having the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the transfer terminal, and the same as the fifth transistor functioning as a switch for supplying a ground potential to the output terminal. An output unit comprising a sixth transistor of conductive type;
A first gate signal generator for supplying a voltage based on a start pulse input to the start pulse input terminal to the gate electrode of the first transistor and the gate electrode of the fifth transistor;
A second voltage for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the second transistor and the gate electrode of the sixth transistor in a phase opposite to that of the first gate signal generator; A gate signal generator,
The first gate signal generator is
A third transistor and a fourth transistor, each having a gate electrode connected to the start pulse input terminal, are connected in series, and the voltage at the connection location is supplied to the first transistor. A pulse output circuit characterized in that an electrode at one end is grounded. A first clock input terminal for inputting a first clock; a third clock input terminal for inputting a third clock maskable in phase with the first clock; a start pulse input terminal for inputting a start pulse; A pulse output circuit including a transfer terminal that outputs an output pulse based on the first clock in synchronization with an output terminal that outputs an output pulse based on a start pulse in synchronization with the third clock,
A first transistor functioning as a switch for outputting a voltage based on the first clock input from the first clock input terminal to the transfer terminal; and a voltage based on the third clock input from the third clock input terminal. A fifth transistor that functions as a switch that outputs to the output terminal; a gate electrode of the first transistor; a first capacitor element provided between the gate electrode of the fifth transistor and the transfer terminal; The second transistor having the same conductivity type as the first transistor functioning as a switch for supplying a ground potential to the transfer terminal, and the same as the fifth transistor functioning as a switch for supplying a ground potential to the output terminal. An output unit comprising a sixth transistor of conductive type;
A first gate signal generator for supplying a voltage based on a start pulse input to the start pulse input terminal to the gate electrode of the first transistor and the gate electrode of the fifth transistor;
A second voltage for supplying a voltage based on the start pulse input to the start pulse input terminal to the gate electrode of the second transistor and the gate electrode of the sixth transistor in a phase opposite to that of the first gate signal generator; A gate signal generator,
The pulse output circuit, wherein the output section includes a second capacitor element between a gate electrode of the first transistor and a gate electrode of the fifth transistor and a grounded portion.   9. A shift register in which the pulse output circuit according to claim 1 is connected in multiple stages so that the output terminal of the previous stage is connected to the start pulse input terminal of the next stage. A scanning line driving circuit used in an electro-optical device including a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines,
A shift register according to claim 9,
Based on a plurality of output signals generated by transferring an input signal using the shift register, a plurality of scanning signals for exclusively sequentially selecting the plurality of scanning lines are generated.
Scan line driving circuit. A data line driving circuit used in an electro-optical device including a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines,
A shift register according to claim 9,
Based on a plurality of output signals generated by transferring an input signal using the shift register, a plurality of data line selection signals for exclusively sequentially selecting the plurality of data lines are generated.
Data line drive circuit. A plurality of scan lines;
Multiple data lines,
An electro-optic element provided corresponding to the intersection of the scanning line and the data line;
A scanning line driving circuit according to claim 10 or a data line driving circuit according to claim 11,
An electro-optical device comprising: An electronic apparatus comprising the electro-optical device according to claim 12.

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