JP2008270364A - Nonvolatile semiconductor memory element - Google Patents

Abstract

Provided is a nonvolatile semiconductor memory element that is less likely to cause a hole trap or a gate oxide film defect in a memory cell by a data erasing operation, and that stabilizes the operation by suppressing fluctuations in element characteristics.
A non-volatile semiconductor memory element having a cross-sectional structure having a single polysilicon layer includes a memory cell portion a, a data erasing portion b, and a control gate portion c that are isolated from each other. The memory cell part a and the data erasing part b are composed of MOS transistors, and the control gate part c is composed of a MOS capacitor. These three parts have a common floating gate composed of the single polysilicon layer. By controlling the potential of the floating gate 6c to turn on the memory cell a, data is written to the floating gate 6a, and by controlling the potential of the floating gate 6c to turn on the data erasing portion b, the floating gate 6b is turned on. Erase data through.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory element having a cross-sectional structure having a single gate semiconductor layer.

  Conventionally, an EEPROM (Electrically Erasable and Programmable Read Only Memory) cell having a single-layer gate semiconductor layer has been developed. Since such an EEPROM requires only a single gate semiconductor layer, it does not require a complicated manufacturing process, can be easily manufactured by a general CMOS (Complementary Metal Oxide Silicon) process, and has operations such as data erasing. Since it is the same as a general stack type EEPROM or flash memory, it is widely used as a storage device for trimming in an analog circuit or a radio frequency (RF) tag (for example, see Patent Document 1).

  For such data write operation in the EEPROM, a channel hot electron injection method in which hot electrons generated in the channel region are injected into the floating gate, or an electric field of 5 to 10 MV / cm is applied to the gate oxide film of the memory cell, An FN (Folower Nordheim) writing method in which electrons are injected (tunneled) into the floating gate by a tunnel phenomenon is used.

On the other hand, in the data erasing operation, an electric field is applied in the direction opposite to that at the time of writing, and an FN erasing method in which electrons are extracted from the floating gate using a tunnel phenomenon, An avalanche hot hole injection method is used in which weak avalanche breakdown is generated, hot holes generated at this time are injected into the floating gate, and neutralized with electrons to erase data.
Japanese Patent No. 2596695

  By the way, the avalanche hot hole injection method in the data erasing operation is realized with a lower voltage than the FN erasing method, and thus has an advantage that the peripheral circuit can be simplified.

  However, holes are easily trapped in the gate oxide film of the memory cell, which may cause variations in device characteristics such as the operating voltage and conductance of the transistor, and repetitive rewrite characteristics are significantly lower than those of the FN erase method. There was a drawback.

  In addition, there is a possibility that a leak current is generated between the floating gate and the substrate (P well) due to the trap level generated by the trapped holes. Such a leak current is called SILC (Stress Induced Leakage Current) and may cause a serious problem on the characteristics of the memory cell.

  In addition, the avalanche hot hole injection method performed in the memory cell has many holes injected near the edge of the gate where the breakdown voltage tends to be low because of its structural reason, and the hole current is concentrated near this edge. As a result, there is a drawback that defects in the hole trap and the gate oxide film are likely to occur.

  Therefore, the present invention is a non-volatile semiconductor memory element having a cross-sectional structure having a single gate semiconductor layer, and it is difficult to cause a hole trap or a gate oxide film defect in a memory cell by a data erasing operation. An object of the present invention is to provide a non-volatile semiconductor memory element whose operation is stabilized by suppressing fluctuations.

  A nonvolatile semiconductor memory element according to one aspect of the present invention includes a first element including a MOS transistor having a first floating gate formed on a semiconductor layer region of a first conductivity type via a first insulating layer; A second element composed of a MOS transistor having a second floating gate formed on a second conductive type semiconductor layer region through a second insulating layer; and a first conductive type or second conductive type semiconductor layer region And a third element having a coupling layer capacitively coupled to the semiconductor layer, the first element, the second element, and a semiconductor region layer of the third element Are separated from each other in a common semiconductor layer in plan view, and the first floating gate, the second floating gate, and the coupling layer are formed of a common semiconductor layer, and By controlling the potential of the layers, turn on the first element writes data to the first floating gate, erasing the data through the second floating gate by turning on the second element.

  The data writing may be performed by injecting hot electrons generated in the semiconductor layer of the first element into the first floating gate through the first insulating layer, or in the semiconductor layer of the first element. The data is erased by injecting hot holes generated in the semiconductor layer of the second element into the second floating gate through the second insulating layer by tunneling holes through the first insulating layer. A channel hot hole injection method may be used.

  According to the present invention, it is possible to suppress the occurrence of hole traps and defects in the gate oxide film in the memory element without requiring a complicated manufacturing process, and to suppress fluctuations in element characteristics such as operating voltage and conductance, thereby stabilizing the operation. Thus, a unique effect that a nonvolatile semiconductor memory element can be provided can be obtained.

  Embodiments to which the nonvolatile semiconductor memory element of the present invention is applied will be described below.

[Embodiment 1]
FIG. 1 is a plan view showing the configuration of the nonvolatile semiconductor element of the first embodiment. FIG. 2 is a diagram showing a cross-sectional structure of the nonvolatile semiconductor element shown in FIG.

  As shown in FIG. 1, the nonvolatile semiconductor memory element of the present embodiment includes three parts, a memory cell part a, a data erasing part b, and a control gate part c. The cross-sectional structures of these three parts (ac) are as shown in FIGS. 2 (a), 2 (b) and 2 (c), respectively.

  As shown in FIGS. 2A to 2C, each part is formed on the P-type semiconductor layer 1. The semiconductor layer 1 may be a silicon layer whose conductivity type is changed to P-type by implanting impurities (typically boron (B)). For example, the semiconductor layer 1 is illustrated in a semiconductor substrate having an SOI (Silicon On Insulator) structure. It can be composed of a silicon crystal layer overlying the insulating layer.

  Further, as shown in FIG. 1, each portion includes a P well layer 2 for a memory cell (hereinafter referred to as a P well layer 2) and an N well layer 22 for a data erasing part (hereinafter referred to as a “well portion”). N well layer 22) and control gate N well layer 32 (hereinafter referred to as N well layer 32). The P well layer 2, the N well layer 22, and the N well layer 32 are semiconductor region layers formed in a common semiconductor layer and separated from each other in plan view, and are insulated and separated from each other.

"Memory cell part"
As shown in FIGS. 1 and 2A, the memory cell portion a is formed in a P well layer 2 formed on the semiconductor layer 1, and includes a source N + layer 3, a drain N + layer 4, a gate oxide film. 5a, floating gate 6a, sidewall 7a, LDD (Lightly Doped Drain) / N layer 8, P + layer 9 for well contact, and field oxide film 10a.

  The source N + layer 3 and the drain N + layer 4 are formed on the surface of the P well layer 2 so as to be separated from each other. These layers are made N + type by injecting impurities (typically phosphine (P)) from the surface of the P well layer 2.

  The gate oxide film 5 a is formed of a silicon oxide film formed between the source N + layer 3 and the drain N + layer 4 on the surface of the P well layer 2 via a pair of LDD / N layers 8. The gate oxide film 5a can be formed by, for example, a thermal oxidation method.

  The floating gate 6a is formed on the gate oxide film 5a and is composed of, for example, a polysilicon layer. This polysilicon layer can be formed by, for example, a CVD method.

  A pair of sidewalls 7 a is formed in a region extending from both sides of the floating gate 6 a to the upper surface of the LDD / N layer 8. The sidewall 7a is made of a silicon oxide film, and may be made of the same material as the gate insulating film 5a. Further, for example, after forming the floating gate 6a, the sidewall 7a is formed by forming a silicon oxide film in a region extending over the upper surface and both side surfaces of the floating gate 6a and the surface of the LDD / N layer 8, and then forming the floating gate 6a. The silicon oxide film is formed by etching until the upper surface of the floating gate 6a is exposed.

  The well contact P + layer 9 is formed by implanting impurities (typically boron (B)) from the surface of the P well layer 2 to form a P + type.

  The field oxide film 10a is an oxide film formed for element isolation. For example, the field oxide film 10a is formed by a local oxidation method (LOCOS) (that is, the source N + layer 3 and the drain N + layer 4 in the region indicated by the one-dot chain line). The gate oxide film 5a, the floating gate 6a, the sidewall 7a, the LDD / N layer 8, and the well contact P + layer 9 may be formed in a region other than the region to be formed later).

  The field oxide film 10a is integrally formed in a region other than the region where the P well layer 2, the N well layer 22, and the N well layer 32 are formed by a one-dot chain line in FIG. It may be formed integrally with the field oxide films 10b and 10c.

  As described above, the memory cell portion a has the same configuration as a general N-type MOS transistor.

"Data erasure part"
As shown in FIGS. 1 and 2B, the data erasing part b is formed in an N well layer 22 formed on the semiconductor layer 1 common to the memory cell part a, and includes a source P + layer 23, a drain P + layer 24, gate oxide film 5b, floating gate 6b, sidewall 7b, well contact N + layer 29, and field oxide film 10b are provided.

  The source P + layer 23 and the drain P + layer 24 are formed on the surface of the N well layer 22 so as to be separated from each other. These layers are made P + type by injecting impurities (typically boron (B)) from the surface of the N-well layer 22.

  Gate oxide film 5 b is formed of a silicon oxide film formed between source P + layer 23 and drain P + layer 24 on the surface of N well layer 22. The gate oxide film 5b can be formed by, for example, a thermal oxidation method.

  The floating gate 6b is formed on the gate oxide film 5b and is formed of, for example, a polysilicon layer. As shown in FIG. 1, the floating gate 6b is formed integrally with the floating gate 6a of the memory cell portion a over the P well layer 2 and the N well layer 22.

  A pair of sidewalls 7 b is formed in a region extending from both sides of the floating gate 6 b to a part of the upper surface of the source P + layer 23 and the drain P + layer 24. The sidewall 7b is made of a silicon oxide film and may be made of the same material as the gate insulating film 5b. Further, the side wall 7b is formed, for example, in a region covering the upper surface and both side surfaces of the floating gate 6b and a part of the upper surfaces of the source P + layer 23 and the drain P + layer 24 after forming the floating gate 6b. Then, the formed silicon oxide film is etched until the upper surface of the floating gate 6b is exposed.

  An impurity (typically phosphine (P)) is implanted from the surfaces of the well contact N + layer 29 and the N well layer 22 to form an N + type.

  The field oxide film 10b is an oxide film formed for element isolation. For example, the field oxide film 10b is formed by a local oxidation method (LOCOS) (that is, in the region indicated by the alternate long and short dash line indicated by reference numeral 22, the source P + layer 23, The drain P + layer 24, the gate oxide film 5b, the floating gate 6b, the sidewall 7b, and the well contact N + layer 29 may be formed in a region other than a region to be formed later).

  The field oxide film 10b is integrally formed in a region other than the region where the P well layer 2, the N well layer 22, and the N well layer 32 are formed as indicated by a one-dot chain line in FIG. It may be formed integrally with the oxide films 10a and 10c.

  As described above, the data erasing unit b has the same configuration as that of a general P-type MOS transistor.

"Control gate part"
As shown in FIGS. 1 and 2C, the control gate portion c is formed in an N well layer 32 formed on the semiconductor layer 1 common to the memory cell portion a and the data erasing portion b. A gate P + layer 33, a well contact N + layer 34, a gate oxide film 5c, a floating gate 6c, a sidewall 7c, and a field oxide film 10c are provided.

  The gate oxide film 5c, the floating gate 6c, the sidewall 7c, and the field oxide film 10c are the gate oxide films 5a and 5b of the memory cell portion a and the data erasing portion b, the floating gates 6a and 6b, the sidewalls 7a and 7b, and the field oxidation. Each of the films 10a and 10b is composed of the same film. Among these, as shown in FIG. 1, the floating gate 6c is formed integrally with the floating gate 6a of the memory cell portion a and the floating gate 6b of the data erasing portion b. In the field oxide film 10c, a control gate P + layer 33, a well contact N + layer 34, a gate oxide film 5c, a floating gate 6c, and a sidewall 7c are formed in the region indicated by the alternate long and short dash line indicated by reference numeral 32. It may be formed so as to cover the P well layer 32 outside the region.

  The field oxide film 10c is integrally formed in a region other than the region where the P-well layer 2, the N-well layer 22, and the N-well layer 32 are formed by the one-dot chain line in FIG. It may be formed integrally with the membranes 10a and 10b.

  The control gate P + layer 33 is formed on the surface of the N well layer 32 on both sides of the gate oxide film 5c. For example, the control gate P + layer 33 is formed by implanting impurities (typically boron (B)) from the surface of the N well layer 32. Is done.

  Well contact N + layer 34 is formed by implanting impurities (typically phosphine (P)) into the surface of N well layer 32 between one control gate P + layer 33 and field oxide film 10c. The

  As described above, the control gate portion c has the same configuration as a general P-type MOS capacitor.

"Equivalent circuit"
FIG. 3 is a diagram showing an equivalent circuit of the nonvolatile semiconductor memory element of this embodiment. As shown in the transparent circuit diagram, the non-volatile semiconductor memory element includes the memory cell portion a, the data erasing portion b, and the floating gates 6a, 6b, and 6c of the control gate portion c. In this configuration, an NMOS transistor that configures the data, a PMOS transistor that configures the data erasing unit b, and a PMOS capacitor that configures the control gate unit c are connected. The potentials of the floating gates 6a, 6b, and 6c are controlled by controlling the potential of the floating gate 6c in the control gate portion c. The floating gates 6a, 6b, and 6c are referred to as a floating gate 6 when they are represented as a unit.

  The potential of each of the floating gates 6a, 6b, and 6c is a capacitance between the P well layer 2 and the floating gate 6a (hereinafter referred to as a first capacitance) between the N well layer 22 and the floating gate 6b. , And the ratio of the capacitance between the N-well layer 32 and the floating gate 6c (hereinafter referred to as the third capacitance).

  Here, by making the value of the third capacitance sufficiently larger than the combined capacitance of the first capacitance and the second capacitance (for example, 9: 1), the potential of the floating gate 6 becomes the floating gate. The potential of the floating gates 6a and 6b is easily controlled.

"Operation"
Table 1 shows the potential applied to each element when the nonvolatile semiconductor memory element of this embodiment is operated.

データを書き込む際は、コントロールゲート部ｃのＮウェル層３２と、メモリセル部ａのドレインＮ＋層４とに５（Ｖ）を印加するとともに、メモリセル部ａのソースＮ＋層３を０（Ｖ）に設定する。このとき、Ｎウェル層３２に５（Ｖ）を印加することにより、メモリセル部ａのフローティングゲート６ａには所定の正の電位が生じる。これにより、メモリセル部ａのソースＮ＋層３とドレインＮ＋層４との間のＰウェル層２内（いわゆるチャネル領域内）に十分な電子電流が通流し、ドレインＮ＋層４付近のチャネル領域内でインパクトイオン化現象が発生し、ホットエレクトロンとホットホールの対が発生する。このホットエレクトロンは、所定の正電位に保持されたフローティングゲート６ａに注入され、注入される電子が所定量以上になり、メモリセル部ａの読み出し時におけるゲート電圧より高くなると、フローティングゲート６ａにデータが保持される。

When writing data, 5 (V) is applied to the N well layer 32 of the control gate portion c and the drain N + layer 4 of the memory cell portion a, and the source N + layer 3 of the memory cell portion a is set to 0 (V). ). At this time, by applying 5 (V) to the N well layer 32, a predetermined positive potential is generated in the floating gate 6a of the memory cell portion a. Thereby, a sufficient electron current flows in the P well layer 2 (so-called channel region) between the source N + layer 3 and the drain N + layer 4 of the memory cell part a, and in the channel region near the drain N + layer 4. The impact ionization phenomenon occurs, and a pair of hot electrons and hot holes is generated. The hot electrons are injected into the floating gate 6a held at a predetermined positive potential. When the injected electrons exceed a predetermined amount and become higher than the gate voltage at the time of reading from the memory cell portion a, data is transferred to the floating gate 6a. Is retained.

  In this way, data can be written by the channel hot electron injection method, but the writing method is not limited to this, and an FN (Folower Nordheim) writing method in which electrons are injected into the floating gate by a tunnel phenomenon may be used.

  On the other hand, when erasing data, the N well layer 32 of the control gate portion c is set to 0 (V), and 5 (V) is applied to the data erasing N well layer 22 of the data erasing portion b. The drain P + layer 24 is set to 0 (V). At this time, the potential of the floating gate 6b is also 0 (V), and the potential of the N well layer 22 is higher than that of the floating gate 6b in the data erasing portion b.

  As a result, a sufficient hole current flows in the data erasing N well layer 22 (so-called channel region) between the source P + layer 23 and the drain P + layer 24 of the data erasing part b, and the vicinity of the drain P + layer 24 is passed. An impact ionization phenomenon occurs in the channel region, and a pair of hot electrons and hot holes is generated. This hot hole is injected into the floating gate 6b (channel hot hole injection method), whereby the electrons accumulated in the floating gate 6a (and thus 6b and 6c) are neutralized, so that data is erased in the data erasing section b. Erased.

  Thus, by erasing the data written in the floating gate 6 by the channel hot hole injection method, it is possible to suppress the local increase in the hole current density as in the conventional avalanche hot hole injection method. Defect formation of traps and gate oxide films can be reduced.

  As described above, according to the nonvolatile semiconductor memory element of the present embodiment, when erasing data in the nonvolatile semiconductor memory element having a cross-sectional structure having a single polysilicon layer that can simplify the manufacturing process, Since the electrons stored in the floating gate 6 are neutralized by operating the PMOS transistor of the data erasing unit b dedicated to the data erasing operation without operating a, a hole trap or gate in the NMOS transistor of the memory cell unit a It is possible to provide a nonvolatile semiconductor memory element in which the occurrence of oxide film defects is suppressed, and fluctuations in element characteristics such as the operating voltage and conductance of the NMOS transistor in the memory cell portion a are suppressed to stabilize the operation. .

  In the above, the embodiment in which the nonvolatile semiconductor memory element is formed on the SOI substrate has been described. However, the substrate is not limited to the SOI substrate, and may be another configuration as long as the above-described configuration is realized.

[Embodiment 2]
FIG. 4 is a plan view showing the configuration of the nonvolatile semiconductor element of the second embodiment. FIG. 5 is a diagram showing a cross-sectional structure of the nonvolatile semiconductor element shown in FIG.

  As shown in FIG. 4, the nonvolatile semiconductor memory element of the present embodiment includes three parts: a memory cell part a, a data erasing part b, and a control gate part c.

  The nonvolatile semiconductor memory element of the second embodiment is the same as that of the first embodiment except that three parts are formed on an N-type semiconductor substrate and the configuration of the control gate part c is different. It is.

  As shown in FIGS. 5A to 5C, each part is formed on the N-type semiconductor layer 100. The semiconductor layer 1 may be a silicon layer whose conductivity type is made N-type by implantation of impurities (typically phosphine (P)). For example, the semiconductor layer 1 is illustrated in a semiconductor substrate having an SOI (Silicon On Insulator) structure. It can be composed of a silicon crystal layer overlying the insulating layer.

  As described above, the memory cell part a and the data erasing part b are the same as the memory cell part a and the data erasing part b of the nonvolatile semiconductor memory element according to the first embodiment.

  The control gate part c is the same as the control gate part c of the first embodiment except that the control gate part c has a control gate P well layer 132 instead of the N well layer 32, and the same reference numerals are used for corresponding elements. .

  In the nonvolatile semiconductor memory element according to the second embodiment, as in the nonvolatile semiconductor memory element according to the first embodiment, data is written by the channel hot electron injection method or the FN writing method, and channel hot hole injection is performed. By the method, the data written in the floating gate 6 can be erased.

  As described above, according to the nonvolatile semiconductor memory element of this embodiment, even when the N-type semiconductor layer 100 is used, a single-layer polysilicon that can simplify the manufacturing process as in the first embodiment. In a non-volatile semiconductor memory element having a cross-sectional structure having layers, the floating gate 6 is operated by operating the PMOS transistor of the data erasing unit b dedicated to the data erasing operation without operating the memory cell unit a when erasing data. Since the accumulated electrons are neutralized, it is possible to suppress the occurrence of hole traps and defects in the gate oxide film in the NMOS transistor in the memory cell portion a during data erasing, and the operating voltage and conductance of the NMOS transistor in the memory cell portion a. Provided is a non-volatile semiconductor memory device that stabilizes operation by suppressing fluctuations in device characteristics It is possible.

  The nonvolatile semiconductor memory element according to the exemplary embodiment of the present invention has been described above, but the present invention is not limited to the specifically disclosed embodiment and departs from the scope of the claims. Without limitation, various modifications and changes are possible.

3 is a plan view showing the configuration of the nonvolatile semiconductor element of Embodiment 1. FIG. It is a figure which shows the cross-section of the non-volatile semiconductor element shown in FIG. It is a figure which shows the equivalent circuit of the non-volatile semiconductor memory element of this Embodiment. FIG. 6 is a plan view showing a configuration of a nonvolatile semiconductor element according to a second embodiment. It is a figure which shows the cross-section of the non-volatile semiconductor element shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor layer 2 P well layer (P well layer) for memory cells
3 Source N + layer 4 Drain N + layer 5a, 5b, 5c Gate oxide film 6, 6a, 6b, 6c Floating gate 7a, 7b, 7c Side wall 8 LDD / N layer 9 P + layer for well contact 10a, 10b, 10c Field oxidation Film 22 N-well layer for data erasure part (N-well layer)
23 Source P + layer 24 Drain P + layer 29 N + layer for well contact 32 N well layer for control gate (N well layer)
33 Control gate P + layer 34 N + layer for well contact

Claims (2)

A first element composed of a MOS transistor having a first floating gate formed on a semiconductor layer region of a first conductivity type via a first insulating layer;
A second element composed of a MOS transistor having a second floating gate formed on the semiconductor layer region of the second conductivity type via a second insulating layer;
A third element formed on a semiconductor layer region of the first conductivity type or the second conductivity type via a third insulating layer and having a coupling layer capacitively coupled to the semiconductor layer, the first element, The semiconductor region layers of the second element and the third element are separated from each other by being separated in plan view in a common semiconductor layer, and the first floating gate, the second floating gate, and the coupling layer are Formed with a common semiconductor layer,
By controlling the potential of the coupling layer, the first element is turned on to write data to the first floating gate, and the second element is turned on to erase the data through the second floating gate. Semiconductor memory element. The data is written by a hot electron injection method in which hot electrons generated in the semiconductor layer of the first element are injected into the first floating gate through the first insulating layer, or holes in the semiconductor layer of the first element are formed. Performed by a FN writing method of tunneling through the first insulating layer;
2. The nonvolatile semiconductor device according to claim 1, wherein the erasing of data is performed by a channel hot hole injection method in which hot holes generated in the semiconductor layer of the second element are injected into the second floating gate through the second insulating layer. Memory element.

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