JP2008251137A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a semiconductor memory device in which leak defect in a standby state can be suppressed. <P>SOLUTION: The semiconductor memory device is provided with a memory cell array 11 divided into a plurality of column regions, bit lines BL arranged in the column direction of the memory cell array 11, an input/output signal line IOL performing input/output of data from the outside, data lines DL including lines for normal use of the number of lines in accordance with IOL and at least one redundancy line, a multiplexer MUX which selects one line out of a plurality of BL and connects electrically to DL, a redundancy switch SW which connects electrically the data line and either of DL and IOL based on a redundancy control signal excluding DL corresponding to a column region in which a defective cell exists, and a latch circuit 14 holding specific data in which standby leak is not caused in the defective cell, then, data held in the latch circuit 14 through Dl corresponding to a column region in which the defective cell exists, are writen in the defective cell. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device having a defective memory cell relief circuit.

  In general, in a semiconductor memory device, a single bit failure occurs in a memory cell which is a storage unit, which is a first factor in yield reduction. In the case of an SRAM (Static Random Access Memory) in which a unit cell is formed by 6 transistors, one of the elements (transistors) is most often defective. At this time, if the failure is a failure of the gate insulating film of the transistor, a leak current flows there, increasing the amount of current in the standby state. If this value exceeds the specification, the chip itself becomes a defective product. Similarly, when the cause of the failure is due to the drain leak of the transistor, the amount of current in the standby state is increased and a defective product is generated.

  In a conventional semiconductor memory device, a defective cell is replaced by redundancy in which a row (Row) or a column (Column) including a defective memory cell (hereinafter referred to as “defective cell”) is replaced with an alternative row or column. Techniques have been taken to remedy and improve manufacturing yields. For the above-described leakage failure, a method of reducing the leakage current in the defective cell by separating the row or column including the replaced defective cell from the power supply wiring (see, for example, “Patent Document 1”) can be considered. Yes. However, in the case of SRAM, since the power supply wiring is generally laid out in parallel with the bit line, it is shared between adjacent columns, and inserting an element serving as a power switch in the middle leads to increase in chip area and speed reduction. It was very difficult to design side effects to be small.

  On the other hand, there is a so-called shift redundancy method (see, for example, “Patent Document 2”) in which a column region including a defective cell is replaced in IO units. In this method, a column area larger than the number of input / output lines used for data input / output with the outside is prepared in the memory cell array, and when there is a column area including a defective cell, the column area is used as an input / output line. Instead of assigning, the input / output lines and the column areas are sequentially shifted and associated using the redundancy switch. Since the shift redundancy method does not need to perform redundancy-related circuit operations when accessing the memory cell array once the association is completed, the shift redundancy method can operate at a higher speed than the conventional redundancy method by replacing rows or columns. There is an advantage of becoming.

However, this shift redundancy method also has the problem that the read and write functions are relieved, but the leakage failure in the standby state is not relieved, as in the conventional redundancy method based on row or column replacement. For this reason, the conventional semiconductor memory device has a problem that it is difficult to improve the yield reduction due to the leak failure of the memory cell, except for the strict quality control in the manufacturing process.
JP 2001-216799 A JP 2003-157692 A

  The present invention provides a semiconductor memory device that can suppress a leakage failure in a standby state.

  According to one aspect of the present invention, memory cells are arranged in a matrix in the row and column directions, divided into a plurality of column regions, bit lines arranged in the column direction of the memory cell array, An input / output signal line for inputting / outputting data from the outside, and a data line provided corresponding to the column region and including a number of normal lines and at least one redundancy line corresponding to the input / output signal lines; And selecting means for selecting one of the plurality of bit lines based on an address signal and electrically connecting the selected bit line to the data line, and excluding the data line corresponding to the column region where a defective cell exists. A redundancy switch that electrically connects the data line and one of the input / output signal lines based on a redundancy control signal, and a stand-by leak occurs in the defective cell. And holding means for holding such specific data, and writing the data held in the holding means to the defective cell via the data line corresponding to the column region where the defective cell exists. A semiconductor memory device is provided.

  According to the present invention, since the leakage failure in the standby state is effectively suppressed, the manufacturing yield of the semiconductor memory device can be greatly improved.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a semiconductor memory device (hereinafter also referred to as “memory”) according to an embodiment of the present invention. Here, the parts related to shift redundancy and its control are mainly shown.

  A semiconductor memory device according to an embodiment of the present invention includes a memory cell array 11 in which memory cells are arranged in a matrix in rows and columns (in FIG. 1, the horizontal direction in the drawing is the row direction and the vertical direction in the drawing is the column direction). A row decoder 12 for selecting a row (word line) of the cell array 11, bit lines (hereinafter referred to as “BL0a to 3b and SBL0a, 0b”) arranged in the column direction on the memory cell array 11, and two bit lines , A multiplexer (hereinafter referred to as “MUX-0 to 4”), a row decoder 12 and a data decoder (hereinafter referred to as “DL0 to 3 and SDL0”) which are electrically connected to the data lines (hereinafter referred to as “DL0 to 3 and SDL0”). Control circuit 13 for controlling MUX-0 to MUX-3, a redder that electrically connects either DL0-3 or SDL0 and input / output lines (hereinafter referred to as IOL0-3). Dancing switch (hereinafter referred to as “SW-0 to 3”), four latch circuits (hereinafter referred to as “LT-0 to 3”) for holding control signals for controlling SW-0 to 3, external data And an input / output circuit (hereinafter referred to as “IO-0 to 3”), and a latch circuit 14 that holds specific data that does not cause standby leakage in a defective cell replaced by redundancy. ing.

  The first input / output of MUX-0 is connected to one end of BL0a, the second input / output of MUX-0 is connected to one end of BL0b, the third input / output of MUX-0 is connected to DL0, and MUX-0 The first input / output of -1 is connected to one end of BL1a, the second input / output of MUX-1 is connected to one end of BL1b, the third input / output of MUX-1 is connected to DL1, and the MUX- 2 first input / output is connected to one end of BL2a, the second input / output of MUX-2 is connected to one end of BL2b, the third input / output of MUX-2 is connected to DL2, and MUX-3 The first input / output is connected to one end of BL3a, the second input / output of MUX-3 is connected to one end of BL3b, the third input / output of MUX-3 is connected to DL3, and MUX-4 The first input / output is connected to one end of SBL0a, and the second input / output of MUX-4 is connected to SBL0b. Is connected to the end, a third input of the MUX-4 is connected to SDL0.

  The first input / output of SW-0 is connected to DL0, the second input / output of SW-0 is connected to DL1, the third input / output of SW-0 is connected to IOL0, and the first input / output of SW-1 The input / output of 1 is connected to DL1, the second input / output of SW-1 is connected to DL2, the third input / output of SW-1 is connected to IOL1, and the first input / output of SW-2 is Connected to DL2, the second input / output of SW-2 is connected to DL3, the third input / output of SW-2 is connected to IOL3, the first input / output of SW-3 is connected to DL3, The second input / output of SW-3 is connected to SDL0, and the third input / output of SW-3 is connected to IOL3.

  Control data indicating the redundancy IO number is input to each input of LT-0 to LT-3. The output of LT-0 is supplied to the control input of SW-0 as the control signal of SW-0, and the output of LT-1 is output. Is supplied to the control input of SW-1 as a control signal of SW-1, the output of LT-2 is supplied to the control input of SW-2 as a control signal of SW-2, and the output of LT-3 is supplied to SW-3. The control signal is supplied to the control input of SW-3.

  The first input / output of IO-0 is connected to IOL0, the second input / output of IO-0 is connected to the data bus Data0 for data input / output with the outside, and the first input / output of IO-1 is Connected to IOL1, the second input / output of IO-1 is connected to data bus Data1 for data input / output with the outside, the first input / output of IO-2 is connected to IOL2, and the second input / output of IO-2 The input / output of 2 is connected to the data bus Data2 for data input / output with the outside, the first input / output of IO-3 is connected to the IOL3, and the second input / output of IO-3 is the data input to the outside. It is connected to a data bus Data3 that performs output.

  The input of the latch circuit 14 is input redundancy data (hereinafter referred to as “RD data”) that suppresses the leakage of defective cells, and the output of the latch circuit 14 is supplied to the MUX-0 to MUX-3 via DL0-3. ing.

  As shown in FIG. 1, the memory cell array 11 includes five columns (columns 0a and 0b, columns 1a and 1b, columns 2a and 2b, columns 3a and 3b, or spare columns 0a and 0b). The bit lines (BL0a to 3b and SBL0a and 0b) of each column are connected to MUX-0 to 3 corresponding to the respective column regions.

  Spare columns 0a and 0b used for redundancy replacement have different names from other columns for distinction, but their circuit configurations are the same as other columns.

  The MUX-2 corresponding to the column area where the defective cell exists, every time the memory cell array 11 is accessed, the RD data from the latch circuit 14 is defective regardless of whether it is a read operation or a write operation. Operates to write to a cell.

  In the shift redundancy in the semiconductor memory device having such a configuration, the column regions are collectively replaced for each IOL. For example, as shown in FIG. 1, when there is a defective cell in the column 2b, SW-0 to 3 are controlled to skip column regions (columns 2a and 2b) corresponding to DL2, and to IOL0 to 3 DL0, DL1, DL3, and SDL0 are assigned in order.

  This assignment is determined by the data value held by LT-0 to LT-3 of each IO, and is generally sent as data (redundancy IO number) for replacing a defective column area from a fuse element (not shown).

Next, the cause of the standby leak failure will be described using an SRAM cell in which the memory cell is composed of six transistors as an example.
FIG. 2 is a circuit diagram showing a gate leak path in the memory cell of the semiconductor memory device according to the embodiment of the present invention.

  The memory cell of the semiconductor memory device according to the embodiment of the present invention has two n-type MOS transistors (hereinafter referred to as “N1 and N2”) and two p-type MOS transistors (hereinafter referred to as “NP1 and P2”). And a transfer gate composed of two n-type MOS transistors (hereinafter referred to as “N3 and N4”).

  The source of P1 is connected to the power supply voltage (hereinafter referred to as “VDD”), the gate of P1 is connected to the drain of N4 (hereinafter referred to as “node B”), and the drain of P1 is connected to the drain of N3 (hereinafter referred to as “node B”). And the source of P2 is connected to VDD, the gate of P2 is connected to node A, the drain of P2 is connected to node B, the drain of N1 is connected to node A, The gate of N1 is connected to the node B, the source of N1 is connected to the ground potential (hereinafter referred to as “VSS”), the drain of N2 is connected to the node B, the gate of N2 is connected to the node A, and N2 The source of N3 is connected to VSS, the gate of N3 is connected to a word line (hereinafter referred to as “WL”), the source of N3 is connected to the bit line BL, and the gate of N4 is connected to WL. N4 source is connected to the bit line BBL.

  BL and BBL are complementary signal lines, and constitute a pair of BL0a to 3b, SBL0a, or 0b in FIG.

  The data holding unit holds the complementary data written by N3 and N4 in the node A and the node B while N3 and N4 are off.

  As shown in FIG. 2, if the data holding unit holds data such that the node A is “L” and the node B is “H”, the gate leak during standby is mainly , N1 and P2. That is, since no channel is formed in the off transistors N2 to N4 and P1, current leakage is observed as gate edge leakage rather than gate leakage. However, the probability of occurrence is extremely small, and it is the transistor that is turned on and has a channel formed that is observed as a gate leak. Therefore, in the 6Tr cell shown in FIG. 2, N1 and P2 contribute to the standby leak as gate leaks.

  Note that if the data value held by the data holding unit changes, the transistor that contributes to gate leakage changes. That is, when the node A is “H” and the node B is “L”, the transistors contributing to the gate leakage are N2 and P1. In general, except for cases caused by dust or resist collapse, defects in memory cells are most frequently caused by single transistors, so standby leakage may occur depending on the data value written to the defective cells. I do not.

  For example, even if there is a problem with the gate oxide film of N1, if data is written such that the node A is “H” and the node B is “L”, standby leakage due to this gate failure does not occur.

FIG. 3 is a circuit diagram showing a drain leak path in the memory cell of the semiconductor memory device according to the embodiment of the present invention.
Since the configuration and function of the memory cell are the same as those in FIG. 2, the same reference numerals as those in FIG.

A drain leak is a case where a junction is defective in the drain or source of a transistor and a leak current is generated with respect to a reverse potential.
As shown in FIG. 3, if the data holding unit holds data such that the node A is “L” and the node B is “H”, the drain leak during standby is mainly , P1, N2, and N3.

  Similar to the case of the gate leak of FIG. 2, if the data value held by the data holding unit changes, the transistor contributing to the drain leak also changes. That is, when the node A is “H” and the node B is “L”, the transistors contributing to gate leakage are P2, N1, and N4, and standby leakage occurs depending on the data value written in the defective cell. I do not.

  As described above, the standby leak of the semiconductor memory device may or may not appear depending on the data value written to the defective cell, regardless of whether the cause is a gate leak or a drain leak. In order to specify a data value (RD data) that does not cause stand-by leak, the following is performed.

  First, the quality of each memory is determined at the time of chip die sorting, and a column region including a defective cell in which a leakage current is generated during standby is specified. At this time, it is recorded whether there is a change in the leakage current value depending on the data value held by the defective cell.

  Thereafter, the IO corresponding to the column area to be relieved is determined, and a data value (RD data) that reduces the leakage current of the relieved column area is sent to the latch circuit 14.

  While this memory is in operation (reading or writing operation), the repaired defective column is always in a writing operation and continues to write RD data. In a normal system, the entire address space of the memory is tested in the initial operation. Therefore, the write operation is performed also on the repaired defective cell, and a value that reduces the leakage current is written. Therefore, the leakage current is small in the standby state of the system thereafter.

FIG. 4 is a circuit block diagram showing another operation example of the semiconductor memory device according to the embodiment of the present invention.
Here, since the configuration, function, and connection of each circuit block are the same as those in FIG. 1, the same reference numerals as those in FIG.

  The difference from FIG. 1 is that a defective cell exists in the spare column 0a, and no remedy by redundancy is performed. Conventionally, even in such a case, if a defective cell has a stand-by leak, the chip is regarded as a defective product.

  In the semiconductor memory device according to the embodiment of the present invention, as in FIG. 1, the RD data of the latch circuit 14 is written to the defective cell via SDL0, so that the stand-by leak can be prevented.

Next, specific examples of the redundancy switches SW-0 to SW-3 will be described.
FIG. 5 is a circuit diagram showing an example of SW-0 to SW-3 in the semiconductor memory device according to the embodiment of the present invention.

  SW-0 to SW-3 of the semiconductor memory device according to the embodiment of the present invention include two D-latches 51 and 52 for holding RD data from the latch circuit 14, four two-input one-output selectors 53 to 56, and data lines. RS flip-flop 57 (hereinafter referred to as “RS-FF57”) that holds (ReadT and ReadC) data, D-latch 58 that holds write data to DL0 to DL3 and SDL0, and D that holds bit mask data -NAND circuit 60 (hereinafter referred to as "NAND60") for controlling the latch 59, selectors 53, 54 and 56, NOR circuit 61 (hereinafter referred to as "NOR61") for controlling the bit mask function, and read data IOL0 -3 to 3-state buffer 62 (hereinafter referred to as "BUF62"), and seven inverters Data 63 to 69 (hereinafter referred to as. "INV63~69") is equipped with a.

  DL0-3 and SDL0 are each composed of a pair of complementary signal lines, ReadT and ReadC are connected to the respective signal lines, and the write data (WriteData) is converted into a pair of complementary signals. It is connected to DL0-3 and SDL0.

  The RD data (RDDATA_N) is input to the input D of the D-latch 51, the redundancy control signal RDIN_N is input to the input D of the D-latch 52, and the clock signal RDCLK is input to the clock inputs of the D-latch 51 and 52. The output of INV66 is connected to the first data input A0 of the selector 53, and the read data S_OUTDATA_N + 1 from the SW-0 to SW3 of the next stage is input to the second data input A1 of the selector 53. The output of the NAND 60 is connected to the control input S of 53, the output Q of the selector 53 is connected to the input of the INV 64, the output of the INV 64 is connected to the input of the BUF 62, and the output state of the BUF 62 is connected to the control input of the BUF 62 The signal OUTENABLE for controlling the signal is input, and the output of the BUF 62 is OUTDATA_N. Is output Te to IOL0~3.

  The redundancy signal RDB_L from the previous SW-0 to SW-3 is input to the first input of the NAND 60, the output Q of the D-latch 52 is connected to the second input of the NAND 60, and the output of the NAND 60 is the input of the INV 69. The output of INV69 is output as the redundancy signal RDB_R to the next SW-0 to SW-3, the output of INV67 is connected to the first data input A0 of the selector 54, and the second data input of the selector 54 is connected. The write data S_INDATA_N-1 from the previous SW-0 to SW-3 is input to A1, the output of the NAND 60 is connected to the control input S of the selector 54, and the input data INDATA_N from the IOLs 0 to 3 is input to the INV67. Have been entered.

  ReadT is connected to the first input of RS-FF57, ReadC is input to the second input of RS-FF57, the output of RS-FF57 is connected to the input of INV66, and INV66 is input to the input of INV65. The output of INV65 is output as read data S_OUTDATA_N to SW-0 to SW-3 in the previous stage.

  The output Q of the D-latch 52 is connected to the input of the INV 63, the output Q of the selector 54 is connected to the first data input A0 of the selector 55, and the D-latch is connected to the second data input A1 of the selector 55. The output Q of 51 is connected, the control input S2 of the selector 55 is connected to the output of INV63, the output D of the selector 55 is connected to the input D of the D-latch 58, and the clock input of the D-latch 58 is clocked. The signal DATAACLK is input and the output Q of the D-latch 58 is output as WriteData.

  The output of INV68 is connected to the first data input A0 of the selector 56, the bit mask data BITMASK_N is input to the input of INV68, and the second data input A1 of the selector 56 is input from the previous SW-0 to SW-3. Bit mask data S_BITMASK_N−1 is input, the output of the NAND 60 is connected to the control input S of the selector 57, the output of the INV 63 is connected to the first input of the NOR 61, and the selector 62 is connected to the second input of the NOR 61. 56 outputs Q are connected, NOR 61 output is connected to the input D of the D-latch 59, DATAACLK is input to the clock input of the D-latch 59, and the output Q of the D-latch 59 controls the bit mask. Is output as a signal BitMask.

  The D-latch 51 holds RD data, and the RD data is written to the defective cell via the selector 55 every time the memory cell array 11 is accessed.

  The D-latch 52 holds the redundancy relief position, and the D-latch 52 of the relief position SW-2 holds “L”. This controls selectors 53, 54, and 56, and SW-2 connects DL3 to IOL2. Further, by generating RDB_R to the next stage by NAND 60 from the output of the D-latch 52 and RDB_L from the previous stage, the SW-3 in the subsequent stage connects SDL0 to IOL3 in the same manner as SW-2. .

  Further, the bit mask at the relief position (MUX-2) is released by the NOR 61, and RD data is written to the defective cell in the column area at the relief position even in the read operation from the memory cell array 11.

  The circuit scale of the semiconductor memory device described above is almost the same as that of a conventional circuit using shift redundancy, and an increase in area can be absorbed by adjusting the layout. Further, the writing speed and the reading speed can be substantially the same as those of the conventional circuit.

  According to the above embodiment, RD data corresponding to the leakage state of the defective cell can be written to the defective cell every time the memory cell array 11 is accessed, and the leakage failure in the standby state can be effectively suppressed. The production yield of the storage device can be greatly improved.

  Further, according to the above-described embodiment, even if the function does not require replacement by redundancy, it effectively suppresses the standby leak failure caused by the defective cell in the spare column area, which could not be remedied conventionally. Therefore, the manufacturing yield of the semiconductor memory device can be greatly improved.

  In the above-described embodiment, an SRAM having 6 transistors as a memory cell has been described as an example. However, the present invention is not limited to this, and shift redundancy is employed and the leakage current depends on the data value of the memory cell. For example, the present invention can be applied in principle to a DRAM (Dynamic Random Access Memory) or the like.

  In the above-described embodiment, the cell array is configured by five column regions including two columns, but the present invention is not limited to this. In addition, although there is one spare column area, it can be easily applied to the memory cell array 11 having two or more spare column areas.

  Further, in the above-described embodiment, the number of the memory cell arrays 11 is one. However, the present invention is not limited to this, and can be applied to a semiconductor memory device having a plurality of memory cell arrays 11. In this case, for example, standby leak measurement may be simultaneously performed on a plurality of memory cell arrays 11, and the RD data may be reduced to one. In this way, the test time can be shortened and the latch circuit 14 holding RD data can be shared by the plurality of memory cell arrays 11.

  Furthermore, in the above-described embodiment, there is one latch circuit 14, but the present invention is not limited to this. For example, a latch circuit 14 corresponding to each of a plurality of columns may be provided to hold RD data corresponding to each of a plurality of defective cells.

1 is a circuit block diagram showing a semiconductor memory device according to an embodiment of the present invention. 1 is a circuit diagram showing a path of a gate leak in a memory cell of a semiconductor memory device according to an embodiment of the present invention. 1 is a circuit diagram showing a path of drain leak in a memory cell of a semiconductor memory device according to an embodiment of the present invention. FIG. 6 is a circuit block diagram showing another operation example of the semiconductor memory device according to the embodiment of the present invention. 4 is a circuit diagram showing an example of SW-0 to SW-3 in the semiconductor memory device according to the embodiment of the invention. FIG.

Explanation of symbols

11 memory cell array 12 row decoder 13 control circuit 14, LT-0-3 latch circuits BL0a-3b, SBL0a, SBL0b bit lines MUX-0-4 multiplexers DL0-3, SDL0 data lines SW-0-3 redundancy switches IOL0-3 I / O lines IO-0 to 3

Claims (5)

A memory cell array in which memory cells are arranged in a matrix in the row and column directions and divided into a plurality of column regions;
Bit lines arranged in a column direction of the memory cell array;
I / O signal lines for inputting and outputting data from the outside,
A data line arranged corresponding to the column region and including at least one normal line and at least one redundancy line corresponding to the input / output signal line;
Selection means for selecting one of the plurality of bit lines based on an address signal and electrically connecting to the data line;
A redundancy switch that electrically connects the data line and any of the input / output signal lines based on a redundancy control signal, except for the data line corresponding to the column region where a defective cell exists,
Holding means for holding specific data that does not cause stand-by leak in the defective cell,
A semiconductor memory device, wherein the data held in the holding means is written into the defective cell via the data line corresponding to a column region where the defective cell exists.   The semiconductor memory device according to claim 1, wherein the data held in the holding unit is written to the defective cell each time a read operation is performed from the memory cell array.   2. The semiconductor memory device according to claim 1, wherein in the case of a write operation to the memory cell array, the data held in the holding unit is written to the defective cell by stopping a bit mask function each time.   2. The semiconductor memory device according to claim 1, further comprising: the holding unit that corresponds to the plurality of defective cells on a one-to-one basis when a plurality of the defective cells exist in the column region.   2. The semiconductor memory device according to claim 1, wherein when there are a plurality of the defective cells in the column region, the holding unit holds specific data that reduces the standby leak.

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