JP2008244435A - Method and structure using selected implant angle using linear accelerator process for manufacture of free-standing film of material - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and a system, which use a linear accelerator process for manufacture of free-standing layers of materials. <P>SOLUTION: The method includes subjecting a surface region of a semiconductor substrate to first multiple high energy particles generated using a linear accelerator and provided at a first implant angle to form a region of multiple gettering sites within a cleave region, the cleave region being provided beneath the surface region to define a material layer to be detached, and the semiconductor substrate being maintained at a first temperature. The method includes subjecting the surface region of the semiconductor substrate to second multiple high energy particles generated using the linear accelerator and provided at a second angle, the second multiple high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level. The second multiple high energy particles are provided at the second implant angle. The semiconductor substrate is maintained at a second temperature higher than the first temperature. Subsequently, the detachable material layer is freed using a cleaving process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

(Cross-reference of related applications)
This application claims priority from US Provisional Patent Application No. 60 / 887,086, filed Jan. 29, 2007, which is incorporated herein by reference in its entirety for all purposes.

  The present invention relates generally to techniques including methods and structures for forming substrates using layer transfer techniques. More particularly, the present methods and systems provide methods and systems for manufacturing free standing semiconductor thick films using a linear accelerator process for various applications including solar cells. However, it will be appreciated that embodiments of the present invention have a wider range of applicability. 3D packaging of integrated semiconductor elements, optical or optoelectronic elements, piezoelectric elements, flat panel displays, microelectromechanical systems (MEMS), nanotechnology structures, sensors, actuators, integrated circuits, biological and biomedical devices, etc. It can also be applied to other applications.

  Since ancient times, humans have relied on the "sun" to obtain almost all the useful energy. Such energy comes from petroleum, light, wood, and various forms of thermal energy. Just as an example, humans rely heavily on petroleum resources such as coal and gas for most of their demand. Unfortunately, these oil resources are depleting and causing other problems. As an alternative, solar energy has been proposed in part to reduce dependence on petroleum resources. By way of example only, solar energy can be obtained by “solar cells” that are typically made from silicon.

  Silicon solar cells generate electricity when exposed to sunlight. Solar radiation interacts with silicon atoms and moves to the p and n doped regions of silicon to form electrons and holes that generate potential differences and currents between the doped regions. Depending on the application, solar cells integrate light collecting elements to improve efficiency. As an example, sunlight is collected and focused using a light collecting element that directs solar radiation to one or more portions of the active photovoltaic material. Although efficient, these solar cells still have many limitations.

  By way of example only, solar cells rely on starting materials such as silicon. Such silicon is often made using polysilicon (ie, polycrystalline silicon) and / or single crystal silicon materials. These materials are often difficult to manufacture. Polysilicon batteries are usually formed by manufacturing polysilicon plates. While these plates can be formed efficiently, they do not have optimal properties for high efficiency solar cells. Single crystal silicon exhibits properties suitable for high-quality solar cells. However, such single crystal silicon is expensive and difficult to use in applications that utilize sunlight in an efficient and cost effective manner. In addition, both polysilicon and single crystal silicon materials suffer from material loss during conventional manufacturing called “kerfloss”, which is as much as 40% of the starting material from the cast or grown boule in the cutting process and Even up to 60% is removed, breaking the material into wafer shape elements. This is a very inefficient way of preparing a thin polysilicon or single crystal silicon plate for use in solar cells.

  In general, thin film solar cells are less expensive by using less silicon material, but these amorphous or polycrystal structures are less efficient than more expensive bulk silicon cells made from single crystal silicon substrates. These and other limitations can be found throughout the present specification and in more detail below.

  From the above, it can be seen that a technique for forming a suitable substrate material with high quality and low cost is highly desired.

  In accordance with the present invention, techniques including methods and structures for forming a substrate using layer transfer techniques are provided. More particularly, the method and system provide a method and system that uses a linear accelerator process to produce free-standing semiconductor thick films for various applications including solar cells. However, it will be appreciated that embodiments of the present invention have a wider range of applicability. 3D packaging of integrated semiconductor elements, optical or optoelectronic elements, piezoelectric elements, flat panel displays, microelectromechanical systems (MEMS), nanotechnology structures, sensors, actuators, integrated circuits, biological and biomedical devices, etc. It can also be applied to other applications.

  In a specific embodiment, the present invention uses one or more semiconductor substrates, such as single crystal silicon, polycrystal silicon, polysilicon, silicon germanium, germanium, silicon carbide, gallium nitride, III / IV group materials, etc. Providing a method for manufacturing a layer of free-standing material. In a specific embodiment, the method includes providing a semiconductor substrate having a surface region and a thickness. The method includes applying a surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a plurality of gettering site regions within a cleavage region. The cleaving region is provided below the surface region to define a layer of material to be separated, and the semiconductor substrate is maintained at a first temperature. The first plurality of high energy particles are provided at a first implantation angle. In a specific embodiment, the method includes exposing a surface region of the semiconductor substrate to a second plurality of high energy particles generated using the linear accelerator, wherein the second plurality of high energy particles is a first number. It is provided to increase the stress level of the cleavage region from a stress level of one to a second stress level. The second plurality of high energy particles is provided at a second implantation angle. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature that is higher than the first temperature. This method removes a layer of pre-separable recording material using a cleaving process, such as a controlled cleaving process. The terms “first” and “second” are not intended to be limiting and should be construed in their ordinary sense, and may be different or the same, depending on the specific embodiment.

  In an alternative embodiment, the present invention provides a method of forming a free-standing layer of layer transfer material, such as, for example, single crystal silicon, polysilicon, polysilicon, silicon germanium, silicon carbide, gallium nitride, germanium, III / IV group materials I will provide a. Single crystal silicon can be at a solar cell, semiconductor, or metal grade purity level due to tradeoffs required between factors such as efficiency, cost, and post processing such as impurity gettering. Any single crystal material can be cut in a specific orientation with advantages such as ease of cleavage and preferred device operation. For example, silicon solar cells can be cut to have a (100), (110), or (111) surface orientation primarily to make this type of free-standing substrate. Of course, a starting material having an orientation plane intentionally miscut from the main crystal orientation can be prepared. Of course, there can be other variations, modifications, and alternatives. The method includes providing a crystalline substrate material having a surface region. The method includes a first dose from a surface region of the crystalline substrate material to a storage region to form an implantation characteristic having a peak concentration and a bottom that are spatially arranged within a range to form the storage region. Introducing a plurality of first particles within a range and within a first temperature range. The plurality of first particles are provided at a first implantation angle. In a specific embodiment, the first dose range is greater than an amount sufficient to cause a plurality of particles to be permanently placed in the storage region of the crystalline substrate material to form a cleavage region. Few. In a specific embodiment, the first particles cause a plurality of defects in a cleavage region of the crystalline substrate material, the cleavage region preferably having a depth greater than about 10 microns below the surface region, the cleavage region and the Defined by slices of crystalline material separated between surface regions.

  In an optional specific embodiment, the method includes the step of causing the formation of a plurality of substantially permanent defects that are quenched in the crystalline substrate material from the first particles in the accumulation region. Performing a processing step on the substrate material. The method also includes a plurality of second particles in a second dose range and a second temperature range to increase internal stress in the storage region so that a portion of the storage region can be cleaved. Introducing into the storage area. The plurality of second particles are provided at a second implantation angle. In a specific embodiment, the method includes forming a free-standing layer of crystalline material by separating the layer of crystalline material from the rest of the crystalline substrate material.

  Furthermore, the present invention provides a method for producing a layer of free-standing material using one or more semiconductor substrates. In a preferred embodiment, the method uses one or more pattern areas to facilitate the initiation of the cleaving operation. In a specific embodiment, the method provides a semiconductor substrate having a surface region and a thickness. The method includes exposing a surface region of the semiconductor substrate to a first plurality of high energy particles generated by a linear accelerator to form a pattern region of a plurality of gettering sites in the cleavage region. In a preferred embodiment, a cleave region is provided below the surface region to define a layer of material to be separated. The semiconductor substrate is maintained at a first temperature. In a specific embodiment, the first plurality of high energy particles is provided at a first implantation angle. The method also includes subjecting the semiconductor substrate to a processing step, such as a heat treatment. The method includes exposing the surface region of the semiconductor substrate to a second plurality of high energy particles, which results in increasing the stress level of the cleaved region from a first stress level to a second stress level. In a specific embodiment, the semiconductor substrate is maintained at a second temperature and the second plurality of particles is provided at a second implantation angle. This method results in a cleaving operation in selected regions of the pattern region to separate a portion of the separable material layer by cleaving and removing the separable material layer using a cleaving step. Including.

  In yet another specific embodiment, the present invention provides a method for forming a film of material from a bulk semiconductor substrate, such as single crystal silicon, polysilicon, or the like. In a specific embodiment, the substrate may have various shapes such as a square, a square shape, a circle, a ring, and a rectangle. Depending on the embodiment, the substrate may also be a metal, an insulator, or a combination of these materials. In this method, a semiconductor substrate having a surface region and a thickness is prepared, and the thickness is the thickness of the entire semiconductor substrate. The method includes exposing a surface region of the semiconductor substrate to a plurality of particles to form a cleave region (eg, a plurality of particles are embedded by single or multiple implantation and / or diffusion), wherein the cleave region is Defined as being below the surface region to form a stressed region and to define a layer of material to be separated. Depending on the specific embodiment, the layer of material has a thickness of about 20 microns or more, or may be slightly thinner if it is self-supporting, for example without self-supporting, stiffeners or the like. . In a specific embodiment, the method uses a cleaving step to remove the layer of separable material while yielding a layer of the material characterized by a deformed shape, eg bent at the end or end region. Holding the portion of the stress region attached to the layer of material. In a specific embodiment, the method comprises removing a portion of the stress region attached to the layer of material so that the deformed shape is removed, resulting in a substantially flat or similar, substantially planar shape. Including.

  Preferred embodiments include one or more techniques for removing portions of the stressed region that cause deformation of the layer of material. In a specific embodiment, removal includes etching the stressed region portion, which causes the material layer to deform. That is, etching can be selectively performed to remove the stressed region, which can be an implanted damage region and / or a region having a higher concentration of hydrogen and / or similar impurities. In a specific embodiment, the etching can be a wet and / or dry etching process or the like. In a specific embodiment, the removal can also occur using a heat treatment of the separated layer of material to release the stressed region. Also, depending on the embodiment, there may be a combination of etching and / or heat treatment.

  In addition, the present invention provides a method of forming a film of material from a bulk semiconductor substrate, which takes advantage of the inherent bending properties of the material cleaved to facilitate separation from the remaining bulk substrate portion. In a specific embodiment, the method provides a semiconductor substrate having a surface region and a thickness. The method includes exposing a surface region of the semiconductor substrate to a plurality of particles to form a cleave region, the cleave region forming a stressed region and defining a layer of material to be separated. Defined as being under the area. In a specific embodiment, the layer of material has a thickness of about 20 microns or more, but may be slightly thinner if it is self-supporting. In a specific embodiment, the method uses the selective energy placement in a spatial region within the vicinity of the cleaved region to form a separated portion of a layer of material having the stressed region portion. Including causing separation of the portion of the layer of material that is separated in the end region of the cleavage region. In a specific embodiment, the method is such that the separated portion of the layer of material is bent away from the spatial region and is separated from the remaining substrate portion to facilitate removal of the layer of material. Generating a deformed shape in the layer of material. In specific embodiments, the energy is a light source, laser source, heat source, radiation source, mechanical source, chemical source, gravity source, or fluid source such as, for example, a gas, liquid, vapor, or combination, One or more sources can be selected. Of course, there can be other variations, modifications, and alternatives.

  In a further embodiment, the present invention provides yet another method for manufacturing a free-standing layer of material using one or more semiconductor substrates. In a specific embodiment, the method includes providing a semiconductor substrate having a surface region and a thickness. The method exposes the surface region of the semiconductor substrate to a first plurality of high energy particles including D + species generated using a linear accelerator to form a plurality of gettering sites in the cleavage region. The cleaved region is provided below the surface region to define a layer of material to be separated. The method also includes subjecting the semiconductor substrate to a processing step according to a specific embodiment. The method includes exposing a surface region of the semiconductor substrate to a second plurality of high energy particles including H2 + species generated using a linear accelerator, wherein the linear accelerator provides the D + species. The same linear accelerator is desirable. In a specific embodiment, the second plurality of particles results in increasing the stress level of the cleave region from a first stress level to a second stress level. The method includes initiating a cleaving operation in selected regions of the cleaved region to separate portions of the separable material layer using a cleaving step. The method includes removing the layer of separable material.

  The embodiments of the present invention can be used to obtain many advantages over existing technologies. In particular, embodiments of the present invention employ a cost effective linear accelerator and method for providing a high energy implantation process for layer transfer technology. Such linear accelerator devices include drift tube technology, a high frequency quadrupole type commonly referred to as RFQ, or combinations thereof (eg, drift tube linac or RFI (RF-Focused Interdigital)) linear accelerators and Including, but not limited to, combined RFQ), DC accelerators, and other suitable technologies. In a preferred embodiment, the linear accelerator provides a layer of transferable material defined by the cleaved surface of the donor substrate. This layer of transferable material can be used in photovoltaic devices, 3D MEMS or integrated circuits, IC packaging, semiconductor devices, silicon carbide and gallium nitride films for semiconductor and optoelectronic applications, any combination thereof, etc. It is further processed to provide high quality semiconductor material for the application. In a preferred embodiment, the method provides single crystal silicon for particularly high efficiency photovoltaic cells. In a preferred embodiment, this method and structure uses a low initial dose of energetic particles, which allows the process to be cost effective and efficient. In addition, the method and structure allow for the production of large area substrates. The present invention can be applied to making a thin silicon material plate having a desired shape (for example, a polysilicon plate having a thickness of 50 μm-200 μm and a size of 12.5 cm × 12.5 cm to 1 m × 1 m or more). You will understand. In an alternative preferred embodiment, embodiments of the present invention can provide a seed layer that can further provide a stack of heterostructure epitaxial processes. The heterostructure epitaxial process can be used to form particularly thin multi-junction photovoltaic cells. By way of example only, GaAs and GaInP layers can be deposited heteroepitaxially on a germanium seed layer, which is a transferred layer formed using the implantation process of an embodiment of the present invention. In a specific embodiment, the method is applicable to cleaving multiple slices sequentially from a single ingot, eg, silicon boule. That is, according to a specific embodiment, the method can be repeated to continuously cleave the slices (similar to slicing a slice from a lump of baked bread). Of course, there can be other variations, modifications, and alternatives.

  Depending on the embodiment, one or more of these advantages can be obtained. These and other advantages are described in more detail below through this embodiment.

  According to embodiments of the present invention, techniques including methods for forming a substrate are provided. More particularly, embodiments according to the present invention provide a method for forming a free-standing layer of material from a semiconductor material. In a specific embodiment, a self-supporting layer of material is provided using a plurality of high energy particles so as to produce a cleavage plane in the semiconductor substrate. The method according to the present invention can be used for various applications including, but not limited to, semiconductor device packaging, photovoltaic cells, MEMS devices, and the like.

In a specific embodiment, a method of manufacturing a self-supporting layer of material using one or more semiconductor substrates is performed as follows.
1. A semiconductor substrate having a surface region and a thickness is prepared.
2. Exposing the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator, wherein the first plurality of high energy particles is defined by the direction and surface region of the first plurality of high energy particles. Provided at a first angle.
3. A plurality of gettering site regions are formed within the cleavage region, the cleavage region being provided below the surface region to define a layer of material to be separated, while the cleavage region is maintained at a first temperature.
4). Optionally, a heat treatment process is performed on the semiconductor substrate to further form a plurality of gettering sites in the cleavage region.
5. Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles generated using a linear accelerator, wherein the second plurality of high energy particles is defined by the direction and surface region of the second plurality of high energy particles. Provided at a second angle.
6). The second plurality of high energy particles increases the stress level in the cleave region from the first stress level to the second stress level, while maintaining the semiconductor substrate at the second temperature.
7). A cleaving process is used to remove the free-standing layer of separable material, while the separable material has no overlying support member or the like.
8). The separated layer of material is placed on the support member.
9. One or more processes are performed on the separated layers of material.
10. Optionally, one or more processes are performed on the semiconductor substrate prior to exposing the surface region of step (2) to the first plurality of high energy particles.
11. Perform other steps as required.

  The above sequence of steps provides a method of forming a substrate using a linear accelerator process according to an embodiment of the present invention. As indicated, the method includes using a co-implantation step to remove a film of material, preferably free standing. Other alternatives are also possible, where steps are added, one or more steps are removed, or one or more steps are provided in a different order without departing from the scope of the claims. obtain. For example, step 5 of high energy implantation is optional, and thermally activated liquid according to a specific embodiment, plasma hydrogenation step, low energy implantation and diffusion or hydrogen is introduced and diffused into the gettering site It can be replaced with any combination or single process including other processes that allow accumulation, but is not limited thereto. Further details of the method can be found throughout the present specification and more particularly below.

  2-8 are schematic diagrams illustrating a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. These diagrams are merely examples and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, modifications, and alternatives. As shown, the method begins by providing a semiconductor substrate 200 having a surface region 201, a back surface 203, and a thickness. Such thickness can be the entire ingot or sliced from a larger ingot or equivalent. In a specific embodiment, the semiconductor substrate is a single crystal silicon wafer, a polysilicon cast wafer, a tile or substrate, a silicon germanium wafer, a germanium wafer, silicon carbide, a III / V material, a II / VI material, gallium nitride, And so on. In a preferred embodiment, the substrate can be a photosensitive material. Of course, there can be other variations, modifications, and alternatives.

  Referring to FIG. 3, the method includes exposing a surface region of a semiconductor substrate to a first plurality of high energy particles 301 generated using a linear accelerator. In a specific embodiment, the particles cause the formation of a plurality of gettering sites or accumulation regions within the cleave region 401, and the cleave region defines a layer of material 405 to be separated, as shown schematically in FIG. Is provided below the surface region. Preferably, the first plurality of high energy particles provides an injection characteristic having a peak concentration and a bottom spatially disposed within a depth of the substrate material. Preferably, the bottom has a width of about 2 Rp or less, where “Rp” is commonly referred to as “a struggle” and is often used to characterize the width of the implant depth characteristic. In a preferred embodiment, the cleave region is maintained at a first temperature 305, which can be provided directly or indirectly. That is, this temperature may be provided by convection, heat conduction, radiation, or a combination of these techniques, depending on the specific embodiment. In a specific embodiment, the temperature can be applied using rapid thermal processing before, after, or during a portion of the time that the particles are introduced. The rapid thermal processing can be uniform or patterned or a combination of these techniques. By way of example only, rapid thermal processing provides to achieve optimized stress properties of displaced silicon atoms within the implant end-of-range layer, where the stress is maximized. However, the selection of rapid thermal processing conditions does not heat the layer to such an extent that hydrogen can escape and reduce getter efficiency. In the present invention, heating refers to a combination of temperature and time that develops the getter layer beyond an optimized effectiveness point. Of course, there can be other variations, modifications, and alternatives.

  In addition, the high energy particle beam can also supply a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. That is, the high energy particle beam can provide direct generation of energy that is converted to thermal energy that raises the temperature of the substrate. In a specific embodiment, the particles convert kinetic energy into thermal energy to increase the temperature of the substrate by a predetermined or desired amount. The particle beam can have scan speed and spatial characteristics. Beam expansion from the original beam size can occur by fast electromagnetic scanning, but can also occur through beam drift beyond the distance that the beam naturally extends to the desired beam diameter and spatial distribution of the beam bundle. Of course, there can be other variations, modifications, and alternatives.

  Depending on the application, according to the preferred embodiment, smaller mass particles generally reduce the energy requirement for implantation of the material to the desired depth and reduce the possibility of damage to the material region. To be selected. That is, smaller mass particles easily move to a selected depth through the substrate material without substantially damaging the material region through which the particles travel. For example, smaller mass particles (or energetic particles) can be most (eg, positive or negative) charged and / or neutral atoms or molecules, or electrons, and the like. In a specific embodiment, depending on the embodiment, the particle can be a neutral or charged particle comprising ions of hydrogen and its isotopes, rare gas ions such as helium and its isotopes, and ions such as neon. . The particles can also be generated from gaseous compounds such as, for example, hydrogen gas, water vapor, methane, and hydrogen compounds, and other light atomic mass particles. Also, the particles can be any combination of the above-described particles and / or ions, and / or molecular species, and / or atomic species. The particles typically have sufficient kinetic energy that can penetrate the surface to a selected depth below the surface.

As an example, using hydrogen as a seed to be implanted into a silicon wafer, the implantation process is performed using a specific set of conditions. The implantation dose is from about 1 × 10 ¹⁵ to about 1 × 10 ¹⁶ atoms / cm ² , and preferably the dose is less than about 5 × 10 ¹⁶ atoms / cm ² . The implantation energy is from about 1 MeV to about 2 MeV or more for the formation of thick films useful for power generation applications. The implantation temperature is from about −50 ° C. to about + 50 ° C. and is preferably less than about 450 ° C. to avoid the possibility of hydrogen ions diffusing out of the implanted silicon wafer. Hydrogen ions can be selectively introduced at selected depths of the silicon wafer with an accuracy of about ± 0.03 to ± 1.5 microns. Of course, the type of ions used and the process conditions depend on the application.

  For higher implantation energies, it is particularly advantageous to perform substantially pure (eg positively or negatively charged) proton implantation in order to take into account the maximum extent of the cleavage plane within the reusable substrate. It is. Using silicon as an example, the number of encapsulated photovoltaic absorbers that can greatly increase the energy width of the implant and require subsequent epitaxial growth to maximize light absorption efficiency KeV ranges from several MeV to produce a substrate with a thickness of several hundred microns used as a starting material for solar cell wafers. The approximate width of implantation depth as a function of implantation energy can be calculated using, for example, SRIM2003 (Stopping Range In Matter) or a Monte Carlo simulation program (http://www.srim.org/). In a specific embodiment, proton implantation energy of about 2 MeV to about 5 MeV is used for a silicon film having a thickness of about 50 μm to about 200 μm. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, a silicon film about 50 μm to about 200 μm thick can be formed using proton implantation with an energy of about 2.1 MeV to about 5 MeV. This width of silicon film thickness allows separation of layers equivalent to a single crystal silicon substrate that can be used as a free-standing silicon substrate. Single crystal silicon substrates in the thickness range of 50 μm to 200 μm can be used to replace current methods using wafer cutting, etching, and polishing processes. In contrast to about 50% kerfloss in current technology (kerfloss is defined as material loss during cutting and wafering operations), implantation cleaving technology is virtually kerfless, resulting in substantial cost savings. And the material utilization efficiency is improved. Energy higher than 5 MeV can be used to process alternative substrate materials to make semiconductors, but in the manufacture of solar cells, 200 μm or less is less than the thickness of the silicon solar cell material for bulk silicon solar cell formation. desired. As a result, there is no particular commercial interest in thicker silicon substrates for solar cell manufacturing according to specific embodiments.

  By way of example, MeV region implantation conditions have been disclosed by Reutov et al. (VF Reutov and Sh. Sh. Ibragimov, name “Method for Fabricating Thin Silicon Wafers”, Soviet Union Inventor's Certificate No. 13857. December 30), which is incorporated herein by reference. V. G. Reutov and Sh. Sh. Ibragimov discloses the use of proton implantation up to 7 MeV with optional heating during implantation and heating of the reusable substrate after implantation to produce isolated silicon wafers up to 350 μm thick. Yes. Thermal cleavage of a 16 micron silicon film using 1 MeV hydrogen implantation is K. Weldon & al. "On the Mechanism of Hydrogen-Induced Exfoliation of Silicon", J. et al. Vac. Sci. Technol. B15 (4), July / August 1997, which is hereby incorporated by reference. “Isolated” or “transferred silicon layer” in this context can be released to a free-standing state or released to a permanent substrate or consequently a temporary substrate used as a free-standing substrate, or as a result on a permanent substrate It refers to a silicon film layer formed by implanted ion regions that can be attached. In a preferred embodiment, the silicon material is thick enough that there is no handle substrate that serves as a support member. Of course, the specific process for handling and processing the membrane will depend on the specific process and application.

  Referring to FIG. 5, the method performs a heat treatment step 503 on the semiconductor substrate to further form a plurality of gettering sites in the cleavage region. That is, in the heat treatment step, the cleavage region is annealed out and / or rapidly cooled in order to fix 501 the plurality of first particles at a predetermined position. The heat treatment provides a fixed network of defects that can act as an efficient site for gettering and accumulating particles in a combination of subsequent implantation or hydrogenation or implantation and / or diffusion steps. In a specific embodiment, the elevated temperature is believed to deposit a permanent defect network and trap a significant portion of the hydrogen from the first plurality of particles. A defect layer that is substantially permanent provides a site for efficient collection and trapping of particles in subsequent implantation and / or diffusion steps, which are described in detail throughout the present specification, particularly as described below. Described. In a preferred embodiment, the heat treatment can occur using heat conduction, convection, radiation, or any combination of these techniques. The high energy particle beam can also supply a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, as schematically illustrated in FIG. 6, the method includes exposing a surface region of a semiconductor substrate to a second plurality of high energy particles generated using a linear accelerator. As shown, the method includes a second plurality of high energy particles 605 that are provided to a semiconductor substrate. The second particles are introduced into the cleavage region 607 and the second plurality of high energy particles increase the stress level in the cleavage region from the first stress level to the second stress level. In a specific embodiment, the second stress level is suitable for subsequent cleavage steps. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature 601 that is higher than the first temperature.

As an example, using hydrogen as a seed to be implanted into a silicon wafer, the implantation process is performed using a specific set of conditions. The implantation dose is about 5 × 10 ¹⁵ to about 5 × 10 ¹⁶ atoms / cm ² , and preferably the dose is less than about 1-5 × 10 ¹⁷ atoms / cm ² . The implantation energy is from about 1 MeV to about 2 MeV or more for the formation of thick films useful for power generation applications. The implant dose rate can be supplied from 500 microamps to 50 milliamps, and the total dose rate can be calculated by integrating the implant rate over the expanded beam area. The injection temperature is from about −50 ° C. to about 550 ° C. and is preferably greater than about 350 ° C. for the accumulation step. Hydrogen ions can be selectively introduced at selected depths of the silicon wafer with an accuracy of about ± 0.03 to ± 1.5 microns. In a specific embodiment, the temperature and dose are selected to allow efficient capture of hydrogen molecules, while there may be some diffusion of monoatomic hydrogen. Of course, the type of ions used and the process conditions depend on the application.

  For the higher implantation energies described above, performing a substantially pure (eg, positively or negatively charged) proton injection to account for the maximum range of cleaved surfaces within the reusable substrate Particularly advantageous. Using silicon as an example, the number of encapsulated photovoltaic absorbers that can greatly increase the energy width of the implant and require subsequent epitaxial growth to maximize light absorption efficiency KeV ranges from several MeV to produce a substrate with a thickness of several hundred microns used as a starting material for solar cell wafers. The approximate width of implantation depth as a function of implantation energy can be calculated using, for example, SRIM2003 (Stopping Range In Matter) or a Monte Carlo simulation program (http://www.srim.org/). In a specific embodiment, a proton implantation energy of about 2 MeV to about 5 MeV is used for a silicon film having a thickness of about 50 μm to about 100 μm or more, for example, 200 μm. Of course, there can be other variations, modifications, and alternatives.

  The implanted particles effectively stress or reduce the fracture energy along a plane parallel to the top surface of the substrate at the selected depth. This energy depends in part on the implant species and conditions. These particles reduce the level of fracture energy of the substrate at the selected depth. This allows for controlled cleaving along the implanted surface at a selected depth. Implantation can occur under conditions where the energy state of the substrate at all internal locations is insufficient to cause irreversible breakdown (ie, separation or cleavage) in the substrate material. However, it is noted that the implant dose generally results in a certain amount of defects (eg, micro-defects) in the substrate that can usually be at least partially repaired by a subsequent heat treatment, such as thermal annealing or rapid thermal annealing. Should.

In a specific embodiment, the method uses a mass-selective high energy implantation technique with an appropriate beam intensity. For cost efficiency, the implantation beam current should be on the order of tens of milliamps H ⁺ or H ⁻ ion beam current (if the system can implant high enough energy, H to achieve a high dose rate). it is also possible to use the ₂ ⁺ ion advantageously). Such devices have recently become available through the use of radio frequency quadrupole accelerators (RFQ-Linac) or drift tube linac (DTL), or RF-focused interdigitated (RFI) technology. . These are available from Accsys Technology Inc. of Pleasanton, California. , NM87109, Albuquerque's Linac Systems, LLC.

In a specific embodiment, these techniques use radio frequency acceleration on the extracted proton beam to increase the total energy of the proton beam from about 20-100 KeV to a range of 0.5 to 7 MeV or more. The output beam is usually on the order of a few millimeters in diameter, and for use in this application, the output flux impinging on the target surface should not be too great, and the target surface should not be heated or damaged as much as possible. Therefore, it is necessary to use a beam expansion of about several hundred millimeters per side to 1 meter or more. The proton current available with these approaches can be up to 100 mA or more. As a specific example, assuming a beam output of 100 kW, a 3.25 MeV RFQ / RFI-Linac produces a proton beam current of 31 mA. By using a dose of about 1 × 10 ¹⁶ H / cm ² and an expanded beam of about 500 mm × 500 mm, the area per hour is about 7 square meters while the output flux is kept at about 13 Watts / cm ² . This combination of parameters makes this approach particularly realistic for cost-effective solar cell manufacturing. Furthermore, electromagnetic scanning can be advantageously used to control effective beam characteristics. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the second plurality of particles can also be introduced using any combination of implantation and / or diffusion. In a specific embodiment, the second plurality of particles can be provided using any of the high energy implantation techniques described and other than those described herein. Such techniques include, among others, ion showers, plasma intrusion ion implantation, and other plasma processing steps. Also, certain low energy techniques, including diffusion, can be used to introduce the second plurality of particles to the gettering site. By way of example only, hydrogen and / or other particles can be diffused to the gettering site using driving forces such as convection, conduction, and / or radiation and / or any combination thereof. Such driving force may be thermal, mechanical, chemical, and / or others, depending on the embodiment. By way of example only, such a second plurality of particles can be introduced using plasma hydrogenation or electrolysis (liquid hydrogenation) means under the conditions of a heated target. Also, the plurality of particles can be introduced using a combination of implantation and / or diffusion, according to a specific embodiment. Of course, there can be other variations, modifications, and alternatives.

  Optionally, the method includes a heat treatment step after the implantation step according to a specific embodiment. In a specific embodiment, the method uses a thermal process from about 450 ° C. to about 600 ° C. for the silicon material. In a preferred embodiment, the heat treatment can occur using conduction, convection, radiation, or any combination of these techniques. In a specific embodiment, the temperature can be applied using rapid thermal processing before, after, or during a portion of the time that the particles are introduced. The rapid thermal processing can be uniform or patterned or a combination of these techniques. By way of example only, rapid thermal processing can be performed on silicon and hydrogen in the end-of-range region where the stress characteristics of the maximum displaced silicon atom distribution are achieved without incurring excessive hydrogen out-diffusion. Can be provided to achieve the desired chemical rearrangement. It is well known that short time annealing has such outdiffusion limiting the benefits of heat treatment. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the high energy particle beam can also provide a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. In a preferred embodiment, the processing step smoothes the cleavage region for subsequent cleavage steps. Of course, there can be other variations, modifications, and alternatives.

  In the specific embodiment, as shown in FIG. 7, the semiconductor substrate is disposed in the tray device 701. A plurality of high energy particles 703 generated by the linear accelerator 704 are introduced into the surface region 705 of the semiconductor substrate 707. FIG. 7 also shows a reference spherical coordinate system (ρ, f, θ). The z-axis is perpendicular to the surface area of the semiconductor substrate, and the surface area defines an xy plane of the Cartesian coordinate system. The origin of the reference spherical coordinates and Cartesian coordinates is a plurality of energetic particle incident points 709 on the surface area of the substrate. The distance from the exit 711 of the plurality of high energy particles from the accelerator to the origin is defined by the radial distance ρ of the spherical coordinates. Also shown is the azimuth angle θ from the positive x-axis. The zenith angle f between the plurality of high energy particles and the z axis defines the injection angle. In a specific embodiment, the tray device is configured taking into account the appropriate injection angle. In particular, the tray device can be tilted using two preset points and may be selected by a controller (eg, a computer) based on a prescription procedure. Of course, there can be other variations, modifications, and alternatives.

  Referring again to the present method of forming a free-standing layer of material, the first high energy particles can be provided at a first implantation angle. The first implantation angle is given from about 0 to about 30 degrees. Such a range of implantation angles allows a high density network of gettering sites near the cleavage plane in the layer of the semiconductor substrate of the specific embodiment. This angle can also be chosen to minimize or otherwise select a channeling implant regime that meets the goal of obtaining an optimized gettersite layer. The second plurality of high energy particles is provided at a second implantation angle. The second implantation angle is provided to allow the channeling and the depth distribution of the second high energy particles to be adapted to produce an optimized stress in the crystal plane near the cleavage region. In a specific embodiment, the second implantation angle is about 0 to about 15 degrees. In an alternative embodiment, the second implantation angle is from about 0 to less than about 8 degrees. By way of example only, the accumulation step can be maximized by adapting the second injection peak concentration to the peak of the getter layer. It is well known that the depth of the defect distribution peak of the getter layer developed by implantation is slightly shallower than the peak of the implanted hydrogen concentration. The use of constant energy implantation can be adapted when the second implantation is performed at an angle from the surface normal that is greater than the first getter layer implantation. Using 2 MeV proton implantation as an example, the first implantation damage peak is approximately 1 μm shallower than its peak hydrogen concentration (using SRIM2003, assuming orthogonal implantation and no channeling, this is roughly About 47 μm). In order to maximize the accumulation of the second implanted hydrogen, an implantation angle of about 12 degrees allows a shallower second accumulation implant to match the hydrogen concentration peak to the gettering layer. Of course, the injection angle used depends on the application, and those skilled in the art will recognize many variations, modifications, and alternatives.

  In a specific embodiment, as shown in FIG. 8, the method includes a 805 step of using a cleaving process along the injection surface 801 to remove a layer of free-standing separable material, while also in FIG. As shown, there is no overlying support member or the like in the separable material. As shown, the separable material 810 is removed from the remaining substrate material portion 815. In a specific embodiment, the removing step can be performed using a controlled cleaving process. The controlled cleavage process provides selected energy to a portion of the donor substrate's cleavage region. By way of example only, a controlled cleaving process is described in US Pat. No. 6,013,563, the title of which is Controlled Cleaving Process, of the same applicant, Silicon Genese Corporation of San Jose, Calif. Incorporated herein by reference for the purpose of. As shown, the method removes the layer of material from the substrate to completely remove the layer of material.

  In a specific embodiment, the cleavage step can be performed by using a heat treatment step 817, as shown in FIG. 8A. In a preferred embodiment, the thermal treatment process imparts a temperature gradient to the layers of the substrate, generating stresses that accumulate particularly in the cleave region 823, which is subjected to implantation or accumulation by a plurality of particles. In a specific embodiment, the temperature gradient can be achieved by applying a first temperature T1 to the surface region 819 of the semiconductor substrate and a second temperature T2 to the back region 821 of the semiconductor substrate. Depending on the embodiment, T1 can be greater than T2, or T2 can be greater than T1. A cleavage region 823 is also illustrated. By way of example only, heating can be performed using a variety of techniques. Such techniques can include conduction, radiation, convection, or any combination thereof. Conduction may include conduction using a hot plate or other contact device or liquid and / or gas, according to a specific embodiment. In an alternative embodiment, radiation can be used. Such radiation may include heating lamps, flash lamps, laser lamps, rapid heating devices, etc., according to specific embodiments. Also, a gas can be flowed over one or both surfaces to create a temperature gradient in the cleavage region. Furthermore, either surface can be cooled to a predetermined temperature to create a temperature gradient across the cleavage region. Cooling can be done using conduction, convection, radiation, or other techniques similar to heating techniques. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the cleaving step can be performed using a laser that provides energy for cleaving. With a laser, according to a specific embodiment, a selected region can be formed to take into account the energy absorbed by the portion of the cleaved region so that the laser can penetrate a portion of the substrate. . That is, the substrate and laser types can be used to efficiently convert electromagnetic radiation to create a temperature gradient in the cleavage region. In other alternative specific embodiments, the cleaving process can be performed using an acoustic process. In an alternative embodiment, the cleaving process may be performed using a mechanical process. In another alternative embodiment, cleaving can occur using any of the above steps or any combination of the above steps. Examples of such cleavage techniques can be found in commonly assigned US Pat. No. 6,013,563, which is incorporated herein by reference for all purposes. Of course, there can be other variations, modifications, and alternatives.

In a preferred embodiment, the present invention uses a high energy light source such as a laser source to initiate cleavage. In a specific embodiment, the laser source may be directed into a selected region of the cleavage region and / or within the vicinity of the cleavage region to provide a temperature gradient or even a temperature gradient that initiates a cleavage operation. The laser is pulsed and / or flashing and / or directed to the spatial region, according to a specific preferred embodiment. By way of example only, the laser can be a Q-switched Nd-YAG laser operating at a fundamental wavelength of 1064 nm, such as HIPPO-106QW manufactured by the company Newport Corporation of California, Irvine. Carbon monoxide (CO), carbon dioxide _{(CO 2), Nd-YLF} , can also be used other types of laser devices, such as a free electron laser, and dye laser. According to embodiments, the advantage of a laser wavelength operated near the band edge of the target material is advantageous because the EOR damage region and the cleaved surface hydrogen concentration become much more absorbing than the bulk material near the band edge wavelength. it is conceivable that. In a specific embodiment, this has the effect of increasing the heating component (eg, peak temperature and temperature gradient) within the cleavage plane region.

In a specific embodiment, Nd-YAG with a wavelength of 1064 nm is one of the laser wavelength choices for silicon. In another embodiment, the 20C absorption coefficient (cm ⁻¹ ) of P-doped 5-10 ohm-cm crystalline single crystal silicon is approximately 50 cm ⁻¹ , while the EOR absorption coefficient for the implantation peak is 1000 − It can be increased to 10,000 cm ⁻¹ or more. This allows most of the laser energy to be stored in the cleavage region, according to a preferred embodiment. Other wavelengths may exhibit similar absorption selectivity. Several specific wavelengths tuned to specific EOR chemical bond absorption peaks (eg, hydrogen-related bond absorption bands at approximately 1800-2200 cm ⁻¹ in silicon) optimize laser energy absorption in the cleavage plane region It can also be used advantageously to achieve this. Such a laser can be, for example, a free electron laser that can be tuned to Si—H bond absorption of about 4.8 μm. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method can perform other steps. For example, the method can place a separated layer of material on the support member that is subsequently processed. In addition or optionally, the method performs one or more processes on the semiconductor substrate prior to exposing the surface region to the first high energy particles. Depending on the embodiment, the process can be for the formation of solar cells, integrated circuits, optical elements, any combination thereof, and the like. Of course, there can be other variations, modifications, and alternatives.

In an alternative specific embodiment, an alternative method of manufacturing a free-standing layer of material using one or more semiconductor substrates is provided as follows.
1. A semiconductor substrate having a surface region and a thickness is prepared.
2. Exposing the surface region of the semiconductor substrate to a first patterned plurality of high energy particles generated using a linear accelerator, the first plurality of high energy particles being in the direction of the first plurality of high energy particles and Provided at a first angle defined by the surface area.
3. A plurality of gettering site pattern regions are formed within the cleavage region, the cleavage region being provided below the surface region to define a layer of material to be separated, while the cleavage region is maintained at a first temperature.
4). Optionally, a heat treatment process is performed on the semiconductor substrate to further form a plurality of patterned gettering sites in the cleavage region.
5. Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles generated using a linear accelerator, wherein the second plurality of high energy particles is defined by the direction and surface region of the second plurality of high energy particles. Provided at a second angle.
6). The second plurality of high energy particles increases the stress level in the cleave region from the first stress level to the second stress level, while maintaining the semiconductor substrate at the second temperature.
7). A cleaving process is used to remove the free-standing layer of separable material, while the separable material does not have an overlying support member or the like.
8). The separated layer of material is placed on the support member.
9. One or more processes are performed on the separated layers of material.
10. Optionally, one or more processes are performed on the semiconductor substrate prior to exposing the surface region of step (2) to the first plurality of high energy particles.
11. Perform other steps as required.

  The above sequence of steps provides a method of forming a substrate using a linear accelerator process and pattern implantation according to embodiments of the invention. As indicated, the method preferably includes using a co-injection step to remove the thick, free-standing material film. Other alternatives are also possible, where steps are added, one or more steps are removed, or one or more steps are provided in a different order without departing from the scope of the claims. obtain. Further details of the method can be found throughout the present specification and more particularly below.

  9-15 are schematic diagrams illustrating a method of forming a substrate using a thick layer transfer process according to an alternative embodiment of the present invention. These diagrams are merely examples and should not unduly limit the scope of the claims set forth herein. Those skilled in the art will recognize many variations, modifications, and alternatives. As shown, the method begins by providing a semiconductor substrate 900 having a surface region 901, a back surface 903, and a thickness. Such thickness can be the entire ingot or sliced from a larger ingot or equivalent. In a specific embodiment, the semiconductor substrate is a single crystal silicon wafer, polysilicon cast wafer, tile or substrate, silicon germanium wafer, germanium wafer, III / V material, II / VI material, silicon carbide, gallium nitride, And so on. In a preferred embodiment, the substrate can be a photosensitive material. Of course, there can be other variations, modifications, and alternatives.

  Referring to FIG. 10, the method includes exposing a surface region of a semiconductor substrate to a first plurality of high energy particles 1001 generated using a linear accelerator. In a specific embodiment, the particles cause the formation of a plurality of gettering sites or accumulation regions within the cleave region 1101, and the cleave region defines a layer of material 1105 to be separated, as shown schematically in FIG. Is provided below the surface region. Preferably, the first plurality of high energy particles provides an injection characteristic having a peak concentration and a bottom spatially disposed within a depth of the substrate material. Preferably, the bottom has a width of about 2 Rp or less. In a preferred embodiment, the cleave region is maintained at a first temperature 1105, which can be provided directly or indirectly. That is, this temperature may be provided by convection, conduction, radiation, or a combination of these techniques, depending on the specific embodiment. In a specific embodiment, the temperature can be applied using rapid thermal processing before, after, or during a portion of the time that the particles are introduced. The rapid thermal treatment can be uniform or patterned or a combination of these techniques. By way of example only, rapid thermal processing provides to achieve optimized stress properties of displaced silicon atoms in the implanted range end layer, where the stress is maximized but the selection of rapid thermal processing conditions is hydrogen. Does not heat the layer so that it can escape and reduce getter efficiency. In the present invention, heating refers to a combination of temperature and time that develops the getter layer beyond an optimized effectiveness point. Of course, there can be other variations, modifications, and alternatives.

  Moreover, the high energy particle beam may also be combined with an external heat source to provide a portion of the thermal energy and achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. That is, the high energy particle beam can provide direct generation of energy that is converted to thermal energy that raises the temperature of the substrate. In a specific embodiment, the particles convert kinetic energy into thermal energy to increase the temperature of the substrate by a predetermined or desired amount. Of course, there can be other variations, modifications, and alternatives.

  Depending on the application, according to the preferred embodiment, smaller mass particles generally reduce the energy requirement for implantation of the material to the desired depth and reduce the possibility of damage to the material region. To be selected. That is, smaller mass particles easily move to a selected depth through the substrate material without substantially damaging the material region through which the particles travel. For example, smaller mass particles (or energetic particles) can be most (eg, positive or negative) charged and / or neutral atoms or molecules, or electrons, and the like. In a specific embodiment, depending on the embodiment, the particle can be a neutral or charged particle comprising ions of hydrogen and its isotopes, rare gas ions such as helium and its isotopes, and ions such as neon. . The particles can also be generated from gaseous compounds such as, for example, hydrogen gas, water vapor, methane, and hydrogen compounds, and other light atomic mass particles. Also, the particles can be any combination of the above-described particles and / or ions, and / or molecular species, and / or atomic species. The particles typically have sufficient kinetic energy that can penetrate the surface to a selected depth below the surface.

As an example, using hydrogen as a seed to be implanted into a silicon wafer, the implantation process is performed using a specific set of conditions. The implantation dose is from about 1 × 10 ¹⁵ to about 1 × 10 ¹⁶ atoms / cm ² , and preferably the dose is less than about 5 × 10 ¹⁶ atoms / cm ² . The implantation energy is from about 1 MeV to about 2 MeV or more for the formation of thick films useful for power generation applications. The implantation temperature is from about −50 ° C. to about + 50 ° C. and is preferably less than about 450 ° C. to avoid the possibility of hydrogen ions diffusing out of the implanted silicon wafer. Hydrogen ions can be selectively introduced at selected depths of the silicon wafer with an accuracy of about ± 0.03 to ± 1.5 microns. Of course, the type of ions used and the process conditions depend on the application.

  For higher implantation energies, it is particularly advantageous to perform substantially pure (eg positively or negatively charged) proton implantation in order to take into account the maximum extent of the cleavage plane within the reusable substrate. It is. Using silicon as an example, the number of encapsulated photovoltaic absorbers that can greatly increase the energy width of the implant and require subsequent epitaxial growth to maximize light absorption efficiency KeV ranges from several MeV to produce a substrate with a thickness of several hundred microns used as a starting material for solar cell wafers. The approximate width of the implantation depth as a function of the implantation energy can be calculated using, for example, SRIM 2003 (Stopping Range In Matter) or a Monte Carlo simulation program. In a specific embodiment, proton implantation energy of about 2 MeV to about 5 MeV is used for a silicon film having a thickness of about 50 μm to about 200 μm. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, a silicon film about 50 μm to about 200 μm thick can be formed using proton implantation with an energy of about 2.1 MeV to about 5 MeV. This width of silicon film thickness allows separation of layers equivalent to a single crystal silicon substrate that can be used as a free-standing silicon substrate. Single crystal silicon substrates in the thickness range of 50 μm to 200 μm can be used to replace current methods using wafer cutting, etching, and polishing processes. In contrast to about 50% kerfloss in current technology (kerfloss is defined as material loss during cutting and wafering operations), implantation cleaving technology is virtually kerfless, resulting in substantial cost savings. And the material utilization efficiency is improved. Energy higher than 5 MeV can be used to process alternative substrate materials to make semiconductors, but in the manufacture of solar cells, 200 μm or less is less than the thickness of the silicon solar cell material for bulk silicon solar cell formation. desired. As a result, there is no particular commercial interest in thicker silicon substrates for solar cell manufacturing according to specific embodiments.

  As an example, MeV region implantation conditions have been disclosed by Reutov et al. (VF Reutov and Sh. Sh. Ibragimov, “Method for Fabricating Thin Silicon Wafers”, Soviet Inventor's Certificate No. 1282857. Month 30), which is incorporated herein by reference. V. G. Reutov and Sh. Sh. Ibragimov discloses the use of proton implantation up to 7 MeV with optional heating during implantation and heating of the reusable substrate after implantation to produce isolated silicon wafers up to 350 μm thick. Yes. Thermal cleavage of a 16 micron silicon film using 1 MeV hydrogen implantation is K. Weldon & al. "On the Mechanism of Hydrogen-Induced Exfoliation of Silicon", J. et al. Vac. Sci. Technol. B15 (4), July / August 1997, which is hereby incorporated by reference. “Isolated” or “transferred silicon layer” in this context can be released to a free-standing state or released to a permanent substrate or consequently a temporary substrate used as a free-standing substrate, or as a result on a permanent substrate It refers to a silicon film layer formed by implanted ion regions that can be attached. In a preferred embodiment, the silicon material is thick enough that there is no handle substrate that serves as a support member. Of course, the specific process for handling and processing the membrane will depend on the specific process and application.

In a specific embodiment, the method performs pattern implantation of the first and / or second plurality of particles. As shown, after pattern implantation, the selected region has a higher dose of impurities to facilitate the initiation of the cleaving operation. That is, as shown in FIG. 12A, the selected region is selected so as to be within the periphery 1201 of the substrate in this example. In a specific embodiment, the higher dose can be 2-5 × 10 ¹⁶ cm ⁻² and the lower dose can be in the range of about 0.5-2 × 10 ¹⁶ cm ⁻² or less. In a specific embodiment, pattern implantation is provided in a spatial manner along the edge region as shown. Also, pattern implantation can be performed along the z-axis direction, which is also illustrated. Of course, there can be other variations, modifications, and alternatives.

  Referring to FIG. 12B, the method performs a heat treatment step 1203 on the semiconductor substrate to further form a plurality of gettering sites in the cleavage region. That is, in the heat treatment step, the cleavage region is annealed out and / or rapidly cooled in order to fix 1201 the plurality of first particles at a predetermined position. The heat treatment provides a fixed network of defects that can act as an efficient site for gettering and accumulating particles in subsequent implantation steps. In a specific embodiment, the elevated temperature is believed to deposit a permanent defect network and trap a significant portion of the hydrogen from the first plurality of particles. A defect layer that is substantially permanent provides a site for efficient collection and trapping of particles in a subsequent implantation and / or diffusion process, which is described in detail throughout the present specification and more particularly below. Described. In a preferred embodiment, the heat treatment can occur using heat conduction, convection, radiation, or any combination of these techniques. The high energy particle beam can also supply a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, as schematically illustrated in FIG. 13, the method includes exposing a surface region of a semiconductor substrate to a second plurality of high energy particles generated using a linear accelerator. As shown, the method includes a second plurality of high energy particles 1305 that are provided to a semiconductor substrate. The second particles are introduced into the cleave region 1307 and the second plurality of high energy particles increase the stress level in the cleave region from the first stress level to the second stress level. In a specific embodiment, the second stress level is suitable for subsequent cleavage steps. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature 1301 that is higher than the first temperature.

As an example, using hydrogen as a seed to be implanted into a silicon wafer, the implantation process is performed using a specific set of conditions. The implantation dose is about 5 × 10 ¹⁵ to about 5 × 10 ¹⁶ atoms / cm ² , and preferably the dose is less than about 1-5 × 10 ¹⁷ atoms / cm ² . The implantation energy is from about 1 MeV to about 2 MeV or more for the formation of thick films useful for power generation applications. The implant dose rate can be supplied from 500 microamps to 50 milliamps, and the total dose rate can be calculated by integrating the implant rate over the expanded beam area. The injection temperature is from about −50 ° C. to about 550 ° C., preferably above about 400 ° C. Hydrogen ions can be selectively introduced at selected depths of the silicon wafer with an accuracy of about ± 0.03 to ± 1.5 microns. In a specific embodiment, the temperature and dose are selected to allow efficient capture of hydrogen molecules, while there may be some diffusion of monoatomic hydrogen. Of course, the type of ions used and the process conditions depend on the application.

  For the higher implantation energies mentioned above, performing a substantially pure (eg, positively or negatively charged) proton injection to account for the maximum extent of the cleavage plane within the reusable substrate Particularly advantageous. Using silicon as an example, the number of encapsulated photovoltaic absorbers that can greatly increase the energy width of the implant and require subsequent epitaxial growth to maximize light absorption efficiency KeV ranges from several MeV to produce a substrate with a thickness of several hundred microns used as a starting material for solar cell wafers. The approximate width of implantation depth as a function of implantation energy can be calculated using, for example, SRIM2003 (Stopping Range In Matter) or a Monte Carlo simulation program (http://www.srim.org/). In a specific embodiment, proton implantation energy of about 2 MeV to about 5 MeV is used for a silicon film having a thickness in the range of about 50 μm to about 100 μm or more, for example, 200 μm. Of course, there can be other variations, modifications, and alternatives.

  The implanted particles effectively stress or reduce the fracture energy along a plane parallel to the top surface of the substrate at the selected depth. This energy depends in part on the implant species and conditions. These particles reduce the level of fracture energy of the substrate at the selected depth. This allows for controlled cleaving along the implanted surface at a selected depth. Implantation can occur under conditions where the energy state of the substrate at all internal locations is insufficient to cause irreversible breakdown (ie, separation or cleavage) in the substrate material. However, it is noted that the implant dose generally results in a certain amount of defects (eg, micro-defects) in the substrate that can usually be at least partially repaired by a subsequent heat treatment, such as thermal annealing or rapid thermal annealing. Should.

In a specific embodiment, the method uses a mass-selective high energy implantation technique with an appropriate beam intensity. For cost efficiency, the implantation beam current should be on the order of tens of milliamps H ⁺ or H ⁻ ion beam current (if the system can implant high enough energy, H to achieve a high dose rate). ²⁺ ions can also be used advantageously). Such devices have recently become available by using radio frequency quadrupole accelerators (RFQ-Linac) or drift tube linac (DTL), or RF focused comb (RFI) technology. These are available from Accsys Technology Inc. of Pleasanton, California. , NM87109, Albuquerque's Linac Systems, LLC.

In a specific embodiment, these techniques use radio frequency acceleration on the extracted proton beam to increase the total energy of the proton beam from about 20-100 KeV to a range of 0.5 to 7 MeV or more. The output beam is usually on the order of a few millimeters in diameter, and for use in this application, the output flux impinging on the target surface should not be too great, and the target surface should not be heated or damaged as much as possible. Therefore, it is necessary to use a beam expansion of about several hundred millimeters per side to 1 meter or more. The proton current available with these approaches can be up to 100 mA or more. As a specific example, assuming a beam output of 100 kW, a 3.25 MeV RFQ / RFI-Linac produces a proton beam current of 31 mA. By using a dose of about 1 × 10 ¹⁶ H / cm ² and an expanded beam of about 500 mm × 500 mm, the area per hour is about 7 square meters while the output flux is kept at about 13 Watts / cm ² . This combination of parameters makes this approach particularly realistic for cost-effective solar cell manufacturing. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the second plurality of particles can also be introduced using any combination of implantation and / or diffusion. In a specific embodiment, the second plurality of particles can be provided using any of the high energy implantation techniques described and other than those described herein. Such techniques include, among others, ion showers, plasma intrusion ion implantation, and other plasma processing steps. Also, certain low energy techniques, including diffusion, can be used to introduce the second plurality of particles to the gettering site. By way of example only, hydrogen and / or other particles can be diffused to the gettering site using driving forces such as convection, conduction, and / or radiation and / or any combination thereof. Such driving force may be thermal, mechanical, chemical, and / or others, depending on the embodiment. By way of example only, such a second plurality of particles may be obtained using plasma hydrogenation or electrolysis (liquid hydrogenation) means or other injection and / or diffusion techniques under the conditions of the heated target. Can be introduced. Of course, there can be other variations, modifications, and alternatives.

  Optionally, the method includes a heat treatment step after the implantation step according to a specific embodiment. In a specific embodiment, the method uses a thermal process from about 450 ° C. to about 600 ° C. for the silicon material. In a preferred embodiment, the heat treatment can occur using conduction, convection, radiation, or any combination of these techniques. In a specific embodiment, the temperature can be applied using rapid thermal processing before, after, or during a portion of the time that the particles are introduced. The rapid thermal treatment can be uniform or patterned or a combination of these techniques. By way of example only, rapid thermal processing provides to achieve optimized stress properties of displaced silicon atoms in the implanted range end layer, where stress is maximized, but the selection of rapid thermal processing conditions is hydrogen. The layer is not heated to such an extent that escape getter efficiency can be reduced. In the present invention, heating refers to a combination of temperature and time that develops the getter layer beyond an optimized effectiveness point. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the high energy particle beam can also provide a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. In a preferred embodiment, the processing step smoothes the cleavage region for subsequent cleavage steps. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, as illustrated in FIG. 14, the semiconductor substrate is disposed in the tray device 1401. A plurality of high energy particles 1403 generated by the linear accelerator 1404 are introduced into the surface region 1405 of the semiconductor substrate 1407. FIG. 14 also shows a reference spherical coordinate system (ρ, f, θ). The z-axis is perpendicular to the surface area of the semiconductor substrate, and the surface area defines an xy plane of the Cartesian coordinate system. The origins of the reference spherical coordinates and Cartesian coordinates are incident points 1409 of a plurality of high energy particles on the surface area of the substrate. The distance from the exit 1411 of the plurality of high energy particles from the accelerator to the origin is defined by the radial distance ρ of the spherical coordinates. Also shown is the azimuth angle θ from the positive x-axis. The zenith angle f between the plurality of high energy particles and the z axis defines the injection angle. In a specific embodiment, the tray device is configured taking into account the appropriate injection angle. In particular, the tray device can be tilted using two preset points and may be selected by a controller (eg, a computer) based on a prescription procedure. Of course, there can be other variations, modifications, and alternatives.

  Referring again to the present method of forming a free-standing layer of material, the first high energy particles can be provided at a first implantation angle. The first implantation angle is given from about 0 to about 30 degrees. Such a range of implantation angles is provided to allow a high density network of gettering sites near the cleavage plane in the layer of the semiconductor substrate of the specific embodiment. The second plurality of high energy particles is provided at a second implantation angle. The second implantation angle is provided to allow channeling of the second high energy particle to produce a stress level at the crystal plane near the cleavage region. In a specific embodiment, the second implantation angle can be about 0 to about 15 degrees. In an alternative embodiment, the second implantation angle can be from about 0 to less than about 8 degrees. Of course, the injection angle used depends on the application, and those skilled in the art will recognize many variations, modifications, and alternatives.

In a specific embodiment, the method performs pattern implantation of a second plurality of particles. After implantation of the second plurality of particles, the selected region has a higher dose of impurities to facilitate the initiation of the cleaving operation. That is, the selected region is selected to be within the periphery of the substrate in a specific embodiment. In a specific embodiment, the higher dose can be 2-5 × 10 ¹⁶ cm ⁻² and the lower dose can be in the range of about 0.5-2 × 10 ¹⁶ cm ⁻² or less. In a specific embodiment, pattern implantation is provided in a spatial manner along the edge region as shown. Also, pattern implantation can be performed along the z-axis direction, which is also illustrated. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, as shown in FIG. 15, the method includes a 1502 step of removing a layer of free-standing separable material using a cleaving process along the injection surface 1504, while also in FIG. As shown, there is no overlying support member or the like in the separable material. As shown, the separable material 1501 is removed from the remaining substrate portion 1505. In a specific embodiment, the removing step can be performed using a controlled cleaving process. The controlled cleavage process provides selected energy to a portion of the donor substrate's cleavage region. By way of example only, a controlled cleaving process is described in US Pat. No. 6,013,563, the title of which is Controlled Cleaving Process, of the same applicant, Silicon Genese Corporation of San Jose, Calif. Incorporated herein by reference for the purpose of. As shown, the method removes the layer of material from the substrate to completely remove the layer of material. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method can perform other steps. For example, the method can place a separated layer of material on the support member that is subsequently processed. In addition or optionally, the method performs one or more processes on the semiconductor substrate prior to exposing the surface region to the first high energy particles. Depending on the embodiment, the process can be for the formation of solar cells, integrated circuits, optical elements, any combination thereof, and the like. Of course, there can be other variations, modifications, and alternatives.

In yet another specific embodiment, an alternative method of manufacturing a free-standing layer of material using one or more semiconductor substrates is provided as follows.
1. A semiconductor substrate having a surface region and a thickness is prepared.
2. Exposing the surface region of the semiconductor substrate to a first patterned plurality of high energy particles generated using a linear accelerator, the first plurality of high energy particles being in the direction of the first plurality of high energy particles and Provided at a first angle defined by the surface area.
3. A plurality of gettering site pattern regions are formed within the cleavage region, the cleavage region being provided below the surface region to define a layer of material to be separated, while the cleavage region is maintained at a first temperature.
4). Optionally, a heat treatment process is performed on the semiconductor substrate to further form a plurality of patterned gettering sites in the cleavage region.
5. Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles generated using a linear accelerator, wherein the second plurality of high energy particles is defined by the direction and surface region of the second plurality of high energy particles. Provided at a second angle.
6). The second plurality of high energy particles increases the stress level in the cleave region from the first stress level to the second stress level, while maintaining the semiconductor substrate at the second temperature.
7). A cleaving process is used to remove the free-standing layer of separable material, while the separable material has no overlying support member or the like and the rest of the stressed material (e.g., Implant damaged material, doped material, hydrogen doped material) are still attached to the material layer even after the material layer is separated.
8). Prepare a layer of separated material that is freestanding and deformed.
9. The separated material is treated to remove the remaining stressed material portion.
10. Produces a layer of substantially flat material that is flat in shape and substantially free of portions of stressed material.
11. A separate layer of material is placed on the support member.
12 One or more processes are performed on the separated layers of material.
13. Optionally, one or more processes are performed on the semiconductor substrate prior to exposing the surface region of step (2) to the first plurality of high energy particles.
14 Perform other steps as required.

  The above sequence of steps provides a method of forming a substrate using a linear accelerator process and pattern implantation according to embodiments of the invention. As indicated, the method includes using a co-injection process to remove a film of preferably thick free-standing material. Other alternatives are also possible, where steps are added, one or more steps are removed, or one or more steps are provided in a different order without departing from the scope of the claims. obtain. Alternatively, the method also provides a technique for removing deformation from a layer of material separated using one or more techniques. Further details of the method can be found throughout the present specification and more particularly below.

  FIGS. 16-20 are schematic diagrams illustrating a method of forming a substrate using a thick layer transfer post-cleavage process according to an embodiment of the present invention. These diagrams are merely examples and should not unduly limit the scope of the claims set forth herein. Those skilled in the art will recognize many variations, modifications, and alternatives. As shown, the method begins by providing a semiconductor substrate 1600 having a surface region 1602, a back surface 1603, and a thickness 1604. Such thickness can be the entire ingot or sliced from a larger ingot or equivalent. In a specific embodiment, the semiconductor substrate is a single crystal silicon wafer, polysilicon cast wafer, tile or substrate, silicon germanium wafer, germanium wafer, III / V material, II / VI material, silicon carbide, gallium nitride, And so on. In a preferred embodiment, the substrate can be a photosensitive material. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method includes exposing a surface region of a semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator. In a specific embodiment, the particles result in the formation of multiple gettering sites or accumulation regions within the cleave region 1601, such that the cleave region defines a layer of material 1607 to be separated, as shown schematically in FIG. Provided below the surface area. Preferably, the first plurality of high energy particles provides an injection characteristic having a peak concentration and a bottom spatially disposed within a depth of the substrate material. Preferably, the bottom has a width of about 2 Rp or less. In a preferred embodiment, the cleavage region is maintained at a first temperature, which can be provided directly or indirectly. That is, this temperature may be provided by convection, conduction, radiation, or a combination of these techniques, depending on the specific embodiment. In a specific embodiment, the temperature can be applied using rapid thermal processing before, after, or during a portion of the time that the particles are introduced. The rapid thermal treatment can be uniform or patterned or a combination of these techniques. By way of example only, rapid thermal processing provides to achieve optimized stress properties of displaced silicon atoms in the implanted range end layer, where stress is maximized, but the selection of rapid thermal processing conditions is hydrogen. The layer is not heated to such an extent that escape getter efficiency can be reduced. In the present invention, heating refers to a combination of temperature and time that develops the getter layer beyond an optimized effectiveness point. Of course, there can be other variations, modifications, and alternatives.

  Moreover, the high energy particle beam may also be combined with an external heat source to provide a portion of the thermal energy and achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. That is, the high energy particle beam can provide direct energy that is converted to thermal energy that raises the temperature of the substrate. In a specific embodiment, the particles convert kinetic energy into thermal energy to increase the temperature of the substrate by a predetermined or desired amount. Of course, there can be other variations, modifications, and alternatives.

  Depending on the application, according to the preferred embodiment, smaller mass particles generally reduce the energy requirement for implantation of the material to the desired depth and reduce the possibility of damage to the material region. To be selected. That is, smaller mass particles easily move to a selected depth through the substrate material without substantially damaging the material region through which the particles travel. For example, smaller mass particles (or energetic particles) can be most (eg, positive or negative) charged and / or neutral atoms or molecules, or electrons, and the like. In a specific embodiment, depending on the embodiment, the particle can be a neutral or charged particle comprising ions of hydrogen and its isotopes, rare gas ions such as helium and its isotopes, and ions such as neon. The particles can also be generated from gaseous compounds such as, for example, hydrogen gas, water vapor, methane, and hydrogen compounds, and other light atomic mass particles. Also, the particles can be any combination of the above-described particles and / or ions, and / or molecular species, and / or atomic species. The particles typically have sufficient kinetic energy that can penetrate the surface to a selected depth below the surface.

As an example, using hydrogen as a seed to be implanted into a silicon wafer, the implantation process is performed using a specific set of conditions. The implantation dose is from about 1 × 10 ¹⁵ to about 1 × 10 ¹⁶ atoms / cm ² , and preferably the dose is less than about 5 × 10 ¹⁶ atoms / cm ² . The implantation energy is from about 1 MeV to about 2 MeV or more for the formation of thick films useful for power generation applications. The implantation temperature is from about −50 ° C. to about + 50 ° C. and is preferably less than about 450 ° C. to avoid the possibility of hydrogen ions diffusing out of the implanted silicon wafer. Hydrogen ions can be selectively introduced at selected depths of the silicon wafer with an accuracy of about ± 0.03 to ± 1.5 microns. Of course, the type of ions used and the process conditions depend on the application.

  For higher implantation energies, it is particularly advantageous to perform substantially pure (eg positively or negatively charged) proton implantation in order to take into account the maximum extent of the cleavage plane within the reusable substrate. It is. Using silicon as an example, the number of encapsulated photovoltaic absorbers that can greatly increase the energy width of the implant and require subsequent epitaxial growth to maximize light absorption efficiency KeV ranges from several MeV to produce a substrate with a thickness of several hundred microns used as a starting material for solar cell wafers. The approximate width of implantation depth as a function of implantation energy can be calculated using, for example, SRIM2003 (Stopping Range In Matter) or a Monte Carlo simulation program (http://www.srim.org/). In a specific embodiment, proton implantation energy of about 2 MeV to about 5 MeV is used for a silicon film having a thickness of about 50 μm to about 200 μm. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, a silicon film about 50 μm to about 200 μm thick can be formed using proton implantation with an energy of about 2.1 MeV to about 5 MeV. This width of silicon film thickness allows separation of layers equivalent to a single crystal silicon substrate that can be used as a free-standing silicon substrate. Single crystal silicon substrates in the thickness range of 50 μm to 200 μm can be used to replace current methods using wafer cutting, etching, and polishing processes. In contrast to about 50% kerfloss in current technology (kerfloss is defined as material loss during cutting and wafering operations), implantation cleaving technology is virtually kerfless, resulting in substantial cost savings. And the material utilization efficiency is improved. Energy higher than 5 MeV can be used to process alternative substrate materials to make semiconductors, but in the manufacture of solar cells, 200 μm or less is less than the thickness of the silicon solar cell material for bulk silicon solar cell formation. desired. As a result, there is no particular commercial interest in thicker silicon substrates for solar cell manufacturing according to specific embodiments.

  As an example, MeV region implantation conditions have been disclosed by Reutov et al. (VF Reutov and Sh. Sh. Ibragimov, “Method for Fabricating Thin Silicon Wafers”, Soviet Inventor's Certificate No. 1282857. Month 30), which is incorporated herein by reference. V. G. Reutov and Sh. Sh. Ibragimov discloses the use of proton implantation up to 7 MeV with optional heating during implantation and heating of the reusable substrate after implantation to produce isolated silicon wafers up to 350 μm thick. Yes. Thermal cleavage of a 16 micron silicon film using 1 MeV hydrogen implantation is K. Weldon & al. "On the Mechanism of Hydrogen-Induced Exfoliation of Silicon", J. et al. Vac. Sci. Technol. B15 (4), July / August 1997, which is hereby incorporated by reference. “Isolated” or “transferred silicon layer” in this context can be released to a free-standing state or released to a permanent substrate or consequently a temporary substrate used as a free-standing substrate, or as a result on a permanent substrate It refers to a silicon film layer formed by implanted ion regions that can be attached. In a preferred embodiment, the silicon material is thick enough that there is no handle substrate that serves as a support member. Of course, the specific process for handling and processing the membrane will depend on the specific process and application.

In a specific embodiment, the method performs pattern implantation of the first and / or second plurality of particles. As shown, after pattern implantation, the selected region has a higher dose of impurities to facilitate the initiation of the cleaving operation. That is, as described above, the selected region is selected so as to be within the periphery of the substrate in this example. In a specific embodiment, the higher dose can be 2-5 × 10 ¹⁶ cm ⁻² and the lower dose can be in the range of about 0.5-2 × 10 ¹⁶ cm ⁻² or less. In a specific embodiment, pattern implantation is provided in a spatial manner along the edge region as shown. Also, pattern implantation can be performed along the z-axis direction, which is also illustrated.

  Certain embodiments of the present invention use one or more pattern regions to facilitate the initiation of a cleaving operation. Such an approach may include exposing a surface region of the semiconductor substrate to a first plurality of high energy particles generated by a linear accelerator to form a patterned region of a plurality of gettering sites within the cleavage region. . In one embodiment of the method according to the invention, the cleavage region is provided below the surface region so as to define a layer of material to be separated. The semiconductor substrate is maintained at a first temperature. The method also includes subjecting the semiconductor substrate to a processing step, such as a heat treatment. The method includes exposing a surface region of the semiconductor substrate to a second plurality of high energy particles, which results in increasing the stress level of the cleaved region from a first stress level to a second stress level. This method results in a cleaving operation in selected areas of the pattern area to separate a portion of the separable material layer using a cleaving process and removal of the separable material layer using a cleaving process. Including. Such pattern implantation sequences expose the surface to dose variations, and the starting region is typically developed using a higher dose and / or thermal budget sequence. Propagation of the cleaving motion to complete the cleaving motion includes (i) additional dosed regions for guiding the propagating cleavage front, (ii) stress control for guiding the depth to be cleaved, and / or Or (iii) by using a natural crystal cleavage plane. Some or most regions can be implanted with less dose (or not implanted at all) depending on the particular cleaving technique used. Such a lower dose area can help to improve the overall productivity of the implantation system by reducing the total dose required to separate each film from the substrate. According to a specific embodiment, the generation of a higher dose start region simultaneously increases the dose of the region while heating the region to prepare the region for local film separation. Can be promoted by use of itself. Separation can be accomplished in situ using another thermal process step during or after the implantation beam process. The use of a sensor to measure and feed back the condition of the starting region allows for precise and controlled local membrane separation and can help to avoid heating or damage to the layer immediately after cleavage occurs . Of course, there can be other variations, modifications, and alternatives.

  As described above again, the method performs a heat treatment process on the semiconductor substrate to further form a plurality of gettering sites in the cleavage region. That is, in the heat treatment step, the cleavage region is annealed out and / or rapidly cooled in order to fix the plurality of first particles in a predetermined position. The heat treatment provides a fixed network of defects that can act as an efficient site for gettering and accumulating particles in subsequent implantation steps. In a specific embodiment, the elevated temperature is believed to deposit a permanent defect network and trap a significant portion of the hydrogen from the first plurality of particles. A defect layer that is substantially permanent provides a site for efficient collection and trapping of particles in a subsequent implantation and / or diffusion process, which is described in detail throughout the present specification and more particularly below. Described. In a preferred embodiment, the heat treatment can occur using heat conduction, convection, radiation, or any combination of these techniques. The high energy particle beam can also supply a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method includes exposing a surface region of the semiconductor substrate to a second plurality of high energy particles generated using a linear accelerator. As shown, the method includes a second plurality of high energy particles supplied to a semiconductor substrate. The second particles are introduced into the cleavage region and the second plurality of high energy particles raises the stress level of the cleavage region from the first stress level to the second stress level. In a specific embodiment, the second stress level is suitable for subsequent cleavage steps. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature that is higher than the first temperature.

As an example, using hydrogen as a seed to be implanted into a silicon wafer, the implantation process is performed using a specific set of conditions. The implantation dose is about 5 × 10 ¹⁵ to about 5 × 10 ¹⁶ atoms / cm ² , and preferably the dose is less than about 1-5 × 10 ¹⁷ atoms / cm ² . The implantation energy is from about 1 MeV to about 2 MeV or more for the formation of thick films useful for power generation applications. The implant dose rate can be supplied from 500 microamps to 50 milliamps, and the total dose rate can be calculated by integrating the implant rate over the expanded beam area. The injection temperature is from about −50 ° C. to about 550 ° C., preferably above about 400 ° C. Hydrogen ions can be selectively introduced at selected depths of the silicon wafer with an accuracy of about ± 0.03 to ± 1.5 microns. In a specific embodiment, the temperature and dose are selected to allow efficient capture of hydrogen molecules, while there may be some diffusion of monoatomic hydrogen. Of course, the type of ions used and the process conditions depend on the application.

  For the higher implantation energies described above, performing a substantially pure (eg, positively or negatively charged) proton injection to account for the maximum range of cleaved surfaces within the reusable substrate Particularly advantageous. Using silicon as an example, the number of encapsulated photovoltaic absorbers that can greatly increase the energy width of the implant and require subsequent epitaxial growth to maximize light absorption efficiency KeV ranges from several MeV to produce a substrate with a thickness of several hundred microns used as a starting material for solar cell wafers. The approximate width of implantation depth as a function of implantation energy can be calculated using, for example, SRIM2003 (Stopping Range In Matter) or a Monte Carlo simulation program (http://www.srim.org/). In a specific embodiment, proton implantation energy of about 2 MeV to about 5 MeV is used for a silicon film having a thickness in the range of about 50 μm to about 100 μm or more, for example, 200 μm. Of course, there can be other variations, modifications, and alternatives.

  The implanted particles effectively stress or reduce the fracture energy along a plane parallel to the top surface of the substrate at the selected depth. This energy depends in part on the implant species and conditions. These particles reduce the level of fracture energy of the substrate at the selected depth. This allows for controlled cleaving along the implanted surface at a selected depth. Implantation can occur under conditions where the energy state of the substrate at all internal locations is insufficient to cause irreversible breakdown (ie, separation or cleavage) in the substrate material. However, it is noted that the implant dose generally results in a certain amount of defects (eg, micro-defects) in the substrate that can usually be at least partially repaired by a subsequent heat treatment, such as thermal annealing or rapid thermal annealing. Should.

In a specific embodiment, the method uses a mass-selective high energy implantation technique with an appropriate beam intensity. For cost efficiency, the implantation beam current should be on the order of tens of milliamps H ⁺ or H ⁻ ion beam current (if the system can implant high enough energy, H to achieve a high dose rate). ²⁺ ions can also be used advantageously). Such devices have recently become available by using radio frequency quadrupole accelerators (RFQ-Linac) or drift tube linac (DTL), or RF focused comb (RFI) technology. These are available from Accsys Technology Inc. of Pleasanton, California. , NM87109, Albuquerque's Linac Systems, LLC.

In a specific embodiment, these techniques use radio frequency acceleration on the extracted proton beam to increase the total energy of the proton beam from about 20-100 KeV to a range of 0.5 to 7 MeV or more. The output beam is usually on the order of a few millimeters in diameter, and for use in this application, the output flux impinging on the target surface should not be too great, and the target surface should not be heated or damaged as much as possible. Therefore, it is necessary to use a beam expansion of about several hundred millimeters per side to 1 meter or more. The proton current available with these approaches can be up to 100 mA or more. As a specific example, assuming a beam output of 100 kW, a 3.25 MeV RFQ / RFI-Linac produces a proton beam current of 31 mA. By using a dose of about 1 × 10 ¹⁶ H / cm ² and an expanded beam of about 500 mm × 500 mm, the area per hour is about 7 square meters while the output flux is kept at about 13 Watts / cm ² . This combination of parameters makes this approach particularly realistic for cost-effective solar cell manufacturing. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the second plurality of particles can also be introduced using any combination of implantation and / or diffusion. In a specific embodiment, the second plurality of particles can be provided using any of the high energy implantation techniques described and other than those described herein. Such techniques include, among others, ion showers, plasma intrusion ion implantation, and other plasma processing steps. Also, certain low energy techniques, including diffusion, can be used to introduce the second plurality of particles to the gettering site. By way of example only, hydrogen and / or other particles can be diffused to the gettering site using driving forces such as convection, conduction, and / or radiation and / or any combination thereof. Such driving force may be thermal, mechanical, chemical, and / or others, depending on the embodiment. By way of example only, such a second plurality of particles may be obtained using plasma hydrogenation or electrolysis (liquid hydrogenation) means or other injection and / or diffusion techniques under the conditions of the heated target. Can be introduced. Of course, there can be other variations, modifications, and alternatives.

  Optionally, the method includes a heat treatment step after the implantation step according to a specific embodiment. In a specific embodiment, the method uses a thermal process from about 450 ° C. to about 600 ° C. for the silicon material. In a preferred embodiment, the heat treatment can occur using conduction, convection, radiation, or any combination of these techniques. In a specific embodiment, the temperature can be applied using rapid thermal processing before, after, or during a portion of the time that the particles are introduced. The rapid thermal processing can be uniform or patterned or a combination of these techniques. By way of example only, rapid thermal processing provides to achieve optimized stress properties of displaced silicon atoms in the implanted range end layer, where stress is maximized, but the selection of rapid thermal processing conditions is hydrogen. The layer is not heated to such an extent that escape getter efficiency can be reduced. In the present invention, heating refers to a combination of temperature and time that develops the getter layer beyond an optimized effectiveness point. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the high energy particle beam can also provide a portion of the thermal energy and be combined with an external heat source to achieve the desired implantation temperature. In certain embodiments, the high energy particle beam alone can provide the total thermal energy required for implantation. In a preferred embodiment, the processing step smoothes the cleavage region for subsequent cleavage steps. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, as described above, the semiconductor substrate is placed in a tray device. A plurality of high-energy particles generated by the linear accelerator are introduced into the surface region of the semiconductor substrate. Depending on the embodiment, a reference spherical coordinate system (ρ, f, θ) can be used. The z-axis is perpendicular to the surface area of the semiconductor substrate, and the surface area defines an xy plane of the Cartesian coordinate system. The origins of the reference spherical coordinates and Cartesian coordinates are incident points of a plurality of high energy particles on the surface area of the substrate. The distance from the exit of the plurality of high energy particles from the accelerator to the origin is defined by the radial distance ρ in spherical coordinates. Also shown is the azimuth angle θ from the positive x-axis. The zenith angle f between the plurality of high energy particles and the z axis defines the injection angle. In a specific embodiment, the tray device is configured taking into account the appropriate injection angle. In particular, the tray device can be tilted using two preset points and may be selected by a controller (eg, a computer) based on a prescription procedure. Of course, there can be other variations, modifications, and alternatives.

  Referring again to the present method of forming a free-standing layer of material, the first high energy particles can be provided at a first implantation angle. The first implantation angle is given from about 0 to about 30 degrees. Such a range of implantation angles allows a high density network of gettering sites near the cleavage plane in the layer of the semiconductor substrate of the specific embodiment. The second plurality of high energy particles is provided at a second implantation angle. The second implantation angle is provided to allow channeling of the second high energy particle to produce a stress level at the crystal plane near the cleavage region. In a specific embodiment, the second implantation angle can be about 0 to about 15 degrees. In an alternative embodiment, the second implantation angle can be from about 0 to less than about 8 degrees. Of course, the injection angle used depends on the application, and those skilled in the art will recognize many variations, modifications, and alternatives.

In a specific embodiment, the method performs pattern implantation of a second plurality of particles. After implantation of the second plurality of particles, the selected region has a higher dose of impurities to facilitate the initiation of the cleaving operation. That is, the selected region is selected to be within the periphery of the substrate in a specific embodiment. In a specific embodiment, the higher dose can be 2-5 × 10 ¹⁶ cm ⁻² and the lower dose can be in the range of about 0.5-2 × 10 ¹⁶ cm ⁻² or less. In a specific embodiment, pattern implantation is provided in a spatial manner along the edge region as shown. Also, pattern implantation can be performed along the z-axis direction, which is also illustrated. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, as shown in FIG. 17, the method includes a 1701 step of using a cleaving process along the injection surface 1703 to remove a layer of free-standing separable material, while also in FIG. As shown, there is no overlying support member or the like in the separable material. As shown, the separable material 1705 is removed from the remaining substrate portion 1709. In a specific embodiment, the removing step can be performed using a controlled cleaving process. The controlled cleavage process provides selected energy 1711, 1713 for a portion of the cleavage region of the donor substrate. By way of example only, a controlled cleaving process is described in US Pat. No. 6,013,563, entitled Controlled Cleaving Process, of the same applicant, Silicon Genese Corporation of San Jose, Calif. Incorporated herein by reference for all purposes. As shown, the method removes the layer of material from the substrate to completely remove the layer of material. Of course, there can be other variations, modifications, and alternatives.

  In a preferred embodiment, cleavage occurs using the properties of the layers of material being separated. That is, the method uses a cleaving process to remove a layer of separable material while attaching to the layer of material to produce a layer of material characterized by a deformed shape, for example bent at the end or end region. Holding a portion 1715 of the stress region. In a further embodiment, the present invention provides a method of forming a film of material from a bulk semiconductor substrate, which utilizes the inherent bending properties of the material cleaved to facilitate separation from the remaining bulk substrate portion, Similarly, it is shown in FIG. In a specific embodiment, the method provides a semiconductor substrate 1701 having a surface region and a thickness. In the present embodiment, similar reference numerals are used, but the scope of the claims is not limited. The method includes exposing a surface region of a semiconductor substrate to a plurality of particles to form a cleave region, the cleave region forming a stressed region and defining a layer of material to be separated. Is defined as In a specific embodiment, the layer of material has a thickness of about 20 microns or more, but may be slightly thinner if it is self-supporting. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method uses selective energy placement 1711, 1703 in a spatial region within the vicinity of the cleaved region to form a portion of the layer of removed material having a stressed region portion. And causing separation of a portion of the layer of material separated at the end region of the cleavage region. In a specific embodiment, the method includes bending the separated portion of the material layer 1715 away from the spatial region and the material separated to facilitate removal of the material layer from the remaining substrate portion. Creating a deformed shape in the layer. In a specific embodiment, the energy is a single source, such as a light source, laser source, heat source, radiation source, mechanical source, chemical source, gravity source, or fluid source such as a gas, liquid, vapor, or combination. One or more sources can be selected. In certain embodiments, the liquid or gas can be a heat source or a cold source (ie, cryogenic) to apply thermal stress to the film in a controlled manner.

  In a specific embodiment, optionally, the method forms an overlying layer (not shown) to further facilitate the bending action to enhance the cleaving action. In a specific embodiment, stress is also applied to the overlying layer, but causes a bending action. Such stress can be compressive according to a specific embodiment. Any suitable material (eg, dielectric, silicon nitride) can be used to provide compressive properties in accordance with embodiments of the present invention. After cleaving, the overlying layer can be removed or left in the surface area. Of course, there can be other variations, modifications, and alternatives. Further details of the method are described throughout the present specification and more particularly below.

  Referring to both FIG. 18 and FIG. 18A, this method produces a deformed shape 1801, which is a first bent end region 1803 opposite the second bent end region 1805 and the first bent. A shaft 1809 lying between the curved end region and the second bent end region. In a specific embodiment, the shaft 1809 connects a fourth end region 1813 opposite the third end region 1811. As illustrated, FIG. 18A is a substrate having a cleavage region prior to a cleavage step according to a specific embodiment. As shown, each end region is identified and corresponds to the schematic side view of FIG. Of course, there can be other variations, modifications, and alternatives.

  Referring to FIGS. 19 and 20, this method produces a deformed shape that is removed and produces a portion 1901 of the stress region attached to the layer of material to produce a substantially flat or similar substantially planar shape 2001. remove. In a preferred embodiment, the method includes one or more techniques 1903 for removing stressed region portions that cause deformation in the layer of material. In a specific embodiment, the removal includes etching of the stressed region portion, which causes the material layer to deform. That is, etching can be selectively performed to remove the stressed region, which can be an implanted damage region and / or a region having a higher concentration of hydrogen and / or similar impurities. In a specific embodiment, the etching can be a wet and / or dry etching process or the like. In a specific embodiment, removal can also occur using heat treatment of layers of material separated to release the stressed region. Also, depending on the embodiment, there may be a combination of etching and / or heat treatment. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method can perform other steps. For example, the method can place a separated layer of material on the support member that is subsequently processed. In addition or optionally, the method performs one or more processes on the semiconductor substrate prior to exposing the surface region to the first high energy particles. Depending on the embodiment, the process can be for the formation of solar cells, integrated circuits, optical elements, any combination thereof, and the like. Of course, there can be other variations, modifications, and alternatives.

  In a specific embodiment, the method uses electromagnetic radiation to perform cleavage of the cleavage region to remove a layer of material. In a preferred embodiment, a laser source can be used. In a specific embodiment, the laser source provides laser processing of the cleavage region to initiate cleavage of the cleavage region. In other embodiments, the laser treatment of the cleavage region provides for treating the cleavage region such that it does not initiate and / or cleave the cleavage region, but simply increases the stress in the cleavage region, and thus the cleavage temperature or dose. Or lower both. Furthermore, as described above, the laser source provides a beam that is selectively provided in the spatial region, which effectively allows the beam to pass through the spatial region and couple to the cleaved region. In a specific embodiment, the upper “cleaved” surface may prevent the laser energy from efficiently coupling into the cleavage region. Thus, the selected spatial region is provided in the side or bottom or end region, which is not damaged or disturbed by cleavage. Further, the cleaved surface may be smoothed, annealed or treated (eg, vapor deposition) to improve bonding to the cleaved region. Of course, there can be other variations, modifications, and alternatives.

In other embodiments, the particles may include deuterium (eg, D ⁺ ) and H ₂ ⁺ as implanted species. That is, such particles may be provided using a single linear accelerator process and / or configuration, according to a specific embodiment. In a specific embodiment, the linear accelerator includes a beamline configuration, which allows at least two species to be implanted. In such an embodiment, the method uses a single linear accelerator with the ability to inject both D ⁺ and H ₂ ⁺ (ie, both mass 2 nucleons). Depending on the embodiment, there are various benefits and / or advantages. In a preferred embodiment, two different types of implantation can be provided using a single beamline. As an example, since D ⁺ generates a displacement damage in approximately 2-3 times greater EOR than H ^+, D ⁺ it may be advantageous to first injection (getter layer formation). This method also uses H ₂ ⁺ as the second implant, resulting in a H implant with a dose rate per unit of twice the beam current.

In one example, the method may include the following prescription procedure or sequence. Of course, there can be other variations, modifications, and alternatives.
1. Deuterium plasma is implanted and D ⁺ is injected into the linear accelerator device for acceleration to the target energy for getter layer formation (eg, about 50-60 μm at 2 MeV).
2. (1) and possibly after a temporary annealing sequence to finish the getter layer, change the ECR source gas to hydrogen, implant hydrogen plasma, and accelerate to the target energy to align this accumulation implant in the getter layer H ₂ ⁺ is injected into the linear accelerator. The method excites the end portion of the linear accelerator in step (2), where the energy is increased appropriately. For example, the H ₂ ⁺ energy must exceed 4 MeV and should be estimated around 4.5-5 MeV.
Of course, there can be other variations, modifications, and alternatives.

  While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. While the above is described using a chosen sequence of steps, any combination of the described steps or others can be used. Moreover, certain steps can be combined and / or removed depending on the embodiment. Furthermore, the hydrogen particles replace the use of co-implantation of helium and hydrogen ions to allow the formation of cleaved surfaces with modified dose and / or cleave characteristics according to alternative embodiments. be able to. Alternatively, deuterium or other similar species can be combined and / or used alone as an implanted species. Of course, there can be other variations, modifications, and alternatives. Therefore, the above description and illustrations should not be construed as limiting the scope of the present invention as defined in the appended claims.

(Example)
Several experiments are conducted to demonstrate the principles and operation of the present invention. These experiments are merely examples and should not unduly limit the scope of the claims set forth herein. Those skilled in the art will recognize many variations, modifications, and alternatives. Further details are described throughout the present specification and more particularly below.

  As an example, silicon wafer samples were prepared with various orientations and impurities. In a specific embodiment, a square sample doped in p-type with orientation <100> was prepared. In an alternative embodiment, a circular sample doped n-type with orientation <111> was prepared. Other variations, modifications, and alternatives can be used depending on the embodiment and experiment. Further, the square and circular shapes provide features that are only used here for classification purposes and do not unduly limit the scope of the claims.

  Such samples were cleaned using conventional SC1 and SC2 chemicals according to a specific embodiment. By way of example, a wafer is subjected to a plurality of implantation steps, which are described herein. In round and square samples, certain experiments were injected with hydrogen particles themselves, and other experiments were co-injected with helium and hydrogen particles. To cleave the sample, a heat transfer / conventional process was used, which resulted in separating the thick film of material as a free-standing material. Of course, there can be other variations, modifications, and alternatives.

  FIG. 21 shows an AFM (ie, atomic force microscope) image of the cleavage plane of the material cleaved from the single crystal silicon substrate. As shown, image 21 is from a cleavage plane of a 16 μm thick film, image 21 is from a cleavage plane of a 47 μm thick film, and image 21 is from a cleavage plane of a 117 μm thick film. It is. For thicker films, the RMS roughness is higher as shown. This is expected to require higher implantation energy to form a thicker film, and higher implantation energy results in more variation of the cleavage region. Of course, there can be other variations, modifications, and alternatives. Further details of these membranes are described below.

  Referring to FIG. 22, the surface roughness of a plurality of continuous cleavage cleavage surfaces of a single crystal silicon film is given. As shown, the surface roughness of the first silicon film 22 cleaved from the single crystal silicon substrate and the surface roughness of the next silicon film 22 cleaved from the remaining silicon substrate are given. Each film has a thickness of 117 μm. As depicted, the substrate can be cleaved more than once without surface treatment between each subsequent cleaving. Depending on uniformity and roughness, the surface may be treated after multiple cleavages in some embodiments.

  Referring to FIG. 23, a 15 μm thick single crystal silicon film 2301 is cleaved from the single crystal silicon substrate as depicted. The film is self-supporting, and the AFM measurement result of the cleavage plane is also shown. FIG. 24 shows a 15 μm thick single crystal film and a silicon substrate from which the film is cleaved. As shown, a self-supporting membrane that is cleaved is shown. The edge of the square film bends upward based on the stress received in the cleavage region. In an example, the stress can be removed by removing the cleave region using etching and / or heat treatment, according to a specific embodiment. Of course, there can be other variations, modifications, and alternatives.

  FIG. 25 shows the experimental results of a polysilicon film cleaved from a polysilicon substrate according to an embodiment of the present invention. As shown in FIG. 25, a 20 × 20 μm AFM image of the surface of the polysilicon substrate is shown. This AFM image shows an image of the polysilicon film surface as cleaved. As indicated, the method demonstrated the cleavage of the polysilicon film in a specific embodiment. Of course, there can be other variations, modifications, and alternatives.

  While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. While the above is described using a chosen sequence of steps, any combination of the described steps or others can be used. Moreover, certain steps can be combined and / or removed depending on the embodiment. Furthermore, the hydrogen particles replace the use of co-implantation of helium and hydrogen ions to allow the formation of cleaved surfaces with modified dose and / or cleave characteristics according to alternative embodiments. be able to. Alternatively, deuterium or other similar species can be combined and / or used alone as an implanted species. As mentioned above, most forms of energy can be used to initiate and propagate the cleavage, eg, electrical, mechanical, electromagnetic radiation, gravity, chemistry, any combination thereof, acoustic, microwave And radio waves, laser sources, floodlights and the like. Of course, there can be other variations, modifications, and alternatives. Therefore, the above description and illustrations should not be construed as limiting the scope of the present invention as defined in the appended claims.

It is a simplified process flow explaining the method of board | substrate formation using the thick layer transfer process by embodiment of this invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram for explaining a method of forming a substrate using a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram explaining cleavage using a heat treatment process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. It is a simplified diagram illustrating a method of forming a substrate using a pattern injection and a thick layer transfer process according to an embodiment of the present invention. 6 is a simplified diagram illustrating an alternative method of substrate formation using post-cleavage processing of thick layer transfer according to an embodiment of the present invention. FIG. 6 is a simplified diagram illustrating an alternative method of substrate formation using post-cleavage processing of thick layer transfer according to an embodiment of the present invention. FIG. 6 is a simplified diagram illustrating an alternative method of substrate formation using post-cleavage processing of thick layer transfer according to an embodiment of the present invention. FIG. 6 is a simplified diagram illustrating an alternative method of substrate formation using post-cleavage processing of thick layer transfer according to an embodiment of the present invention. FIG. 6 is a simplified diagram illustrating an alternative method of substrate formation using post-cleavage processing of thick layer transfer according to an embodiment of the present invention. FIG. 6 is a simplified diagram illustrating an alternative method of substrate formation using post-cleavage processing of thick layer transfer according to an embodiment of the present invention. FIG. It is a simplified diagram explaining the experimental result by embodiment of this invention. It is a simplified diagram explaining the experimental result by embodiment of this invention. It is a simplified diagram explaining the experimental result by embodiment of this invention. It is a simplified diagram explaining the experimental result by embodiment of this invention. It is a simplified diagram explaining the experimental result by embodiment of this invention.

Claims (82)

A method of manufacturing a free-standing layer of material using one or more semiconductor substrates, the method comprising:
Preparing a semiconductor substrate having a surface area and a thickness;
Exposing the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a plurality of gettering site regions within the cleavage region, wherein the cleavage region is made of a material to be separated. Provided below the surface region to define a layer, the semiconductor substrate is maintained at a first temperature, and the first plurality of high energy particles is provided at a first implantation angle;
Subjecting the semiconductor substrate to a processing step,
Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles generated using the linear accelerator, wherein the second plurality of high energy particles is from a first stress level to a second stress level. Provided to increase the stress level of the cleavage region, the semiconductor substrate is maintained at a second temperature, and the second plurality of high energy particles is provided at a second implantation angle;
Removing the separable layer of material using a cleavage step.   The method of claim 1, wherein the semiconductor substrate comprises single crystal silicon.   The method of claim 1, wherein the semiconductor substrate comprises polysilicon.   The method of claim 1, wherein the first plurality of high energy particles includes a hydrogen species. The method according to claim 4, wherein the hydrogen species is provided at a dose of 2 × 10 ¹⁶ / cm ² or less. The method according to claim 4, wherein the hydrogen species is provided at a dose of 5 × 10 ¹⁵ / cm ² or less.   The method of claim 1, wherein the first plurality of high energy particles comprises a helium species.   The method according to claim 1, wherein the semiconductor substrate is provided in a tray apparatus.   9. The method of claim 8, wherein the tray device provides the first injection angle and the second injection.   The method of claim 1, wherein the first implantation angle is from about 0 degrees to about 30 degrees.   The method of claim 1, wherein the first implantation angle is from about 0 degrees to about 25 degrees.   The method of claim 1, wherein the second plurality of high energy particles includes a hydrogen species. The method according to claim 12, wherein the hydrogen species has a dose of 5 × 10 ¹⁶ / cm ² or less. The method according to claim 12, wherein the hydrogen species has a dose of 5 × 10 ¹⁵ / cm ² or less.   The method of claim 1, wherein the second plurality of energetic particles comprises a helium species or a combination of helium and hydrogen species generated in a remote plasma system.   The method of claim 1, wherein the second implantation angle is from about 0 degrees to about 15 degrees.   The method of claim 1, wherein the second implantation angle is from about 0 degrees to about 7 degrees.   The method of claim 1, wherein the linear accelerator includes a radio frequency quadrupole (RFQ).   The method of claim 1, wherein the linear accelerator comprises a drift tube linear accelerator (DTL).   The method of claim 1, wherein the linear accelerator comprises an RF focusing comb linear accelerator (RFI).   The method of claim 1, wherein the first plurality of high energy particles are supplied with energy ranging from 1 MeV to 5 MeV.   The method according to claim 1, wherein the gettering site includes a minute defect region in the vicinity of the cleavage region.   The method according to claim 1, wherein the minute defect region includes a plurality of voids provided between specific crystal planes of the semiconductor substrate.   2. The heat treatment according to claim 1, wherein the treatment step is a heat treatment provided at a temperature of 400 ° C. or more so as to stabilize the minute defect region by bringing the minute defect region close to the cleavage region. Method.   The method of claim 1, wherein the first temperature ranges from about -100C to about 250C.   The method of claim 1, wherein the first temperature is less than about 250 degrees Celsius.   The method of claim 1, wherein the second temperature is greater than about 250 ° C and less than or equal to 550 ° C.   The method of claim 1, wherein the layer of separable material has a thickness greater than about 50 μm.   The method of claim 1, wherein the layer of separable material has a thickness greater than about 80 μm.   The method of claim 1, wherein the layer of separable material has a thickness greater than about 100 μm.   The method of claim 1, wherein the cleaving step is a controlled cleaving step.   The method according to claim 1, wherein the cleaving step is a heat treatment.   The method of claim 1, wherein the second temperature ranges from about 20 ° C to about 450 ° C.   The method of claim 1, wherein the first high energy particles and the second high energy particles are provided from a linear accelerator in an expanded beam.   The method of claim 34, wherein the expanded beam has a dimension of about 500 mm in diameter at a surface region of the semiconductor substrate.   The method of claim 1, wherein the linear accelerator comprises a DC accelerator. A method of forming a self-supporting layer of layer transferred material, the method comprising:
Preparing a crystal substrate material having a surface region;
A plurality of first particles are introduced at a first angle within a first dose range and a first temperature range, wherein the first dose range is permanent in the accumulation region of the plurality of particles in the crystalline substrate material. Spatially within a range to form the storage region through a surface region of the crystalline substrate material to a storage region to form implantation characteristics that are less than an amount sufficient to cause a placement Having a peak concentration and a bottom disposed, wherein the first particles cause a plurality of defects in the accumulation region in the crystalline material, the accumulation region having a depth greater than about 20 microns below the surface region. Defined by a slice of crystalline material separated between the accumulation region and the surface region;
Performing a processing step on the crystal substrate material to cause formation of a plurality of substantially permanent defects quenched in the crystal substrate material from the first particles in the accumulation region;
The accumulation of a plurality of second particles to increase internal stress in the accumulation region such that a portion of the accumulation region can be cleaved at a second angle within a second dose range and a second temperature range. Introduced into the area,
Forming a free-standing layer of crystalline material by separating the layer of crystalline material from the rest of the crystalline substrate material.   38. The method of claim 37, wherein the crystalline substrate material is single crystal silicon.   38. The method of claim 37, wherein the crystalline substrate material is polycrystalline silicon.   38. The method of claim 37, wherein the crystalline substrate material is a silicon ingot, such as a silicon boule.   38. The method of claim 37, wherein the plurality of first particles in the accumulation region are in a metastable state prior to the processing step. 38. The method of claim 37, wherein the first dose range is about 2 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² .   38. The method of claim 37, wherein the plurality of first particles are introduced while the crystalline substrate material is maintained at a temperature in the range of about −50 to 100 degrees Celsius.   The method of claim 37, wherein the plurality of first particles are introduced while the crystalline substrate material is maintained at a temperature in the range of about -100 to + 250 ° C.   38. The method of claim 37, wherein the first temperature and the first dose cause a partially amorphized region in the accumulation region.   38. The method of claim 37, wherein the first temperature is less than about 200 degrees Celsius.   38. The method of claim 37, wherein the processing step is a heat treatment step.   48. The method of claim 47, wherein the thermal treatment step is a thermal annealing step that produces a permanent defect network in the accumulation region.   38. The method of claim 37, wherein the first plurality of particles is provided by a first beam.   38. The method of claim 37, wherein the crystalline substrate material is provided in a tray apparatus.   51. The method of claim 50, wherein the tray device provides the first angle and the second angle.   38. The method of claim 37, wherein the first angle is about 0 to about 30 degrees.   38. The method of claim 37, wherein the first angle is from about 0 to about 25 degrees.   38. The method of claim 37, wherein the first plurality of particles comprises hydrogen.   38. The method of claim 37, wherein the second plurality of particles is provided by a second beam.   38. The method of claim 37, wherein the second angle is from about 0 to about 15 degrees.   38. The method of claim 37, wherein the second angle is about 0 to about 7 degrees.   38. The method of claim 37, wherein the first plurality of particles and the second plurality of particles comprise the same particle.   38. The method of claim 37, wherein the first temperature is raised to the second temperature.   38. The method of claim 37, wherein the second dose is provided continuously after the first dose.   38. The method of claim 37, wherein the second dose is provided after the first dose.   38. The method of claim 37, wherein the first dose rate is provided at about 500 [mu] A to 50 mA, and the total dose rate is calculated by integrating an implantation flux rate over the expanded beam area.   38. The method of claim 37, wherein the surface region becomes substantially flat after the second dose.   38. The method of claim 37, wherein the bottom has a width of about 2 Rp or less.   38. The method of claim 37, wherein the second plurality of particles is provided by exposing the surface region to a hydrogen generating environment.   The second plurality of particles is selected to be sufficient to allow diffusion and accumulation of the plurality of particles within the accumulation region defined by the first plurality of particles. 66. The method of claim 65, wherein the method is provided while the layer of material is maintained in a temperature range.   66. The method of claim 65, wherein the hydrogen generation environment is selected from a hydrogen plasma, a hydrogen atmosphere, a hydrogen rich spin-on material, or a hydrogen ion rich liquid such as an acid. A method for producing a self-supporting layer of material using one or more semiconductor substrates,
Preparing a semiconductor substrate having a surface area and a thickness;
Exposing the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a patterned region of a plurality of gettering sites within the cleavage region, the cleavage region being separated Provided below the surface region to define a layer of material, the semiconductor substrate is maintained at a first temperature, the first plurality of high energy particles is provided at a first implantation angle, and the pattern region Is provided to cause the start of the cleavage operation,
Subjecting the semiconductor substrate to a processing step,
Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles such that the second plurality of high energy particles increases the stress level of the cleavage region from a first stress level to a second stress level. Wherein the semiconductor substrate is maintained at a second temperature, and the second plurality of high energy particles are provided at a second implantation angle;
Causing the cleaving operation to occur in selected areas of the pattern area to separate portions of the layer of material that can be separated using a cleaving step;
Removing the separable layer of material using a cleavage step.   69. The method of claim 68, wherein the pattern region is provided in a peripheral region of the semiconductor substrate.   69. The method of claim 68, wherein the pattern region is provided in az direction from the surface region to the gettering site.   69. The method of claim 68, wherein the pattern region is provided in the gettering site. A method of forming a film of material from a bulk semiconductor substrate, the method comprising:
Preparing a semiconductor substrate having a surface area and a thickness;
Exposing the semiconductor substrate to a plurality of particles to form a cleave region, wherein the cleave region is formed under the surface region to form a stressed region and to define a layer of material to be separated; The layer has a thickness of about 20 microns or more;
Removing the separable layer of material using a cleaving step while retaining a portion of the stress region attached to the layer of material to yield a layer of material characterized by a deformed shape;
Removing the portion of the stress region attached to the layer of material such that the deformed shape is removed to produce a substantially planar shape.   75. The method of claim 72, wherein the stressed region includes a plurality of particles embedded therein.   The method of claim 72, wherein the removing comprises etching a portion of the stressed region.   The method of claim 72, wherein the removing comprises heat treating the separated layer of material to release the stressed region.   The method of claim 72, wherein the separated layer of material comprises single crystal silicon or polysilicon.   The method of claim 72, wherein the semiconductor substrate is square.   The deformed shape includes a first bent end region opposite the second bent end region, an axis between the first bent end region and the second bent end region. 78. The method of claim 77, wherein the shaft connects a fourth end region opposite the third end region. The formation of the cleavage region is as follows:
Exposing a surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a patterned region of a plurality of gettering sites within the cleavage region, the semiconductor substrate comprising: Maintained at a temperature, the first plurality of energetic particles provided at a first implantation angle;
Subjecting the semiconductor substrate to a processing step,
Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles such that the second plurality of high energy particles increases the stress level of the cleavage region from a first stress level to a second stress level. 79. The method of claim 78, wherein the semiconductor substrate is maintained at a second temperature and the second plurality of particles is provided at a second implantation angle. A method of forming a film of material from a bulk semiconductor substrate, the method comprising:
Preparing a semiconductor substrate having a surface area and a thickness;
Exposing the semiconductor substrate to a plurality of particles to form a cleave region, wherein the cleave region is defined below the surface region to form a stressed region and to define a layer of material to be separated; The layer has a thickness of about 20 microns or more;
Separated at the end region of the cleaved region using a selective energy arrangement in a spatial region within the vicinity of the cleaved region to form a separated portion of the layer of material having a portion of the stressed region. Causing separation of the layer portion of the material
Bending the separated portion of the layer of material away from the spatial region and creating a deformed shape in the layer of material so as to be separated from the remaining substrate portion to facilitate removal of the layer of material A method characterized by that.   81. The method of claim 80, wherein the energy is selected from a light source, laser source, heat source, radiation source, mechanical source, chemical source, gravity source, or fluid source. A method for producing a self-supporting layer of material using one or more semiconductor substrates,
Preparing a semiconductor substrate having a surface area and a thickness;
Exposing the surface region of the semiconductor substrate to a first plurality of high energy particles including D + species generated using a linear accelerator to form a plurality of gettering sites in the cleavage region, wherein the cleavage region is separated Provided below the surface region to define a layer of material to be
Subjecting the semiconductor substrate to a processing step,
Exposing the surface region of the semiconductor substrate to a second plurality of high energy particles comprising H2 + species using the linear accelerator, the second plurality of high energy particles from a first stress level to a second stress level. Provided to increase the stress level of the cleavage region;
Causing the cleavage operation in selected regions of the cleavage region to separate portions of the separable layer using a cleavage step;
Removing the separable layer.