JP2008244094A - High-frequency power amplifier and portable wireless terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency power amplifier, along with a portable wireless terminal, whose output drops less during operation, effect of thermal noise is less, and high frequency operation is stable, with excellent reliability. <P>SOLUTION: The amplifier includes a plurality of MOS transistors which are arranged parallel on a semiconductor substrate and each of which includes a source electrode, gate electrode, and drain electrode, and a closed loop consisting of a short-circuited conductor provided between adjacent MOS transistors among the plurality of MOS transistors. The source electrode, gate electrode, and drain electrode of the plurality of MOS transistors are connected in parallel. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high-frequency power amplifier and a portable wireless terminal.

  Conventionally, a high-frequency power amplifier having a transistor using a compound semiconductor as a final amplification stage is often used in a transmission circuit of a portable wireless terminal. However, with the progress of miniaturization of the CMOS process, efforts are being made to realize not only digital circuits in the baseband part but also high-frequency analog circuits in the front end part with CMOS, and some of them have already been commercialized. ing. Compared with the compound semiconductor process and the Si-Ge process, the standard CMOS integrated circuit process originally used for the logic circuit is characterized by being relatively inexpensive per unit area.

  When an attempt is made to construct a high-frequency power amplifier with an inexpensive MOS field effect transistor, a new problem arises in that it is not a problem with compound semiconductors. This is caused by the fact that the influence of heat generation becomes more prominent than before due to the high-density arrangement of transistors that has become possible for the first time by the progress of the miniaturization process of MOS transistors on a Si substrate. In particular, when a high-frequency signal is amplified to a large signal, the power consumed by the transistor also increases, resulting in an increase in the amount of heat generated per unit time.

  When a MOS transistor arranged in an extremely small area generates heat by utilizing the miniaturization process, the channel temperature of the transistor rises, the output power of the transistor is lowered, and the reliability is greatly deteriorated. In general, an increase in channel temperature is not a problem limited to MOS transistors. In particular, MOS transistors are most easily manifested by the progress of process miniaturization.

  In a transistor having a large channel width, a large amount of current flows, so that the amount of heat generated in the channel is large. As a result, the channel temperature of the transistor is significantly increased. Incidentally, it is known that the mobility and saturation speed of electrons which are carriers of an N-type MOS transistor become smaller as the temperature rises.

Conventionally, in a field effect transistor having a large channel width used for a power amplifier, for example, as shown in FIG. 2 of Patent Document 1, a gate electrode is often arranged in a comb shape. By disposing the gate electrodes in a comb shape, the layout area of the field effect transistor can be reduced. On the other hand, when the transistor is divided into a plurality of parts in order to avoid the temperature rise caused by the heat generation of the transistor, a closed loop is formed between the plurality of gate electrodes and the drain electrodes as described in Patent Document 1 above. It is known that oscillation may occur.
JP 2001-274415 A

  As described above, when a high frequency power amplifier is constituted by MOS transistors, as a problem peculiar to a MOS transistor produced by a fine process, the channel temperature is significantly increased, resulting in a decrease in output power. An increase in channel temperature also accelerates transistor degradation and impairs reliability.

  In order to avoid the above problem, if the transistor is divided into a plurality of parts and the arrangement is sparse and connected in parallel, a closed loop is formed between the transistors, which causes electromagnetic noise due to a high-frequency magnetic field generated by an external circuit and parasitic oscillation. .

  The present invention has been made in consideration of the above-described circumstances, and has a low output reduction during operation, little influence of thermal noise, stable high frequency operation, and excellent reliability. An object is to provide a wireless terminal.

  A high-frequency power amplifier according to an aspect of the present invention includes a plurality of MOS transistors arranged in parallel on a semiconductor substrate, each having a source electrode, a gate electrode, and a drain electrode, and adjacent MOS transistors among the plurality of MOS transistors And a closed loop made of a short-circuited conductor provided therebetween, wherein the source electrode, the gate electrode, and the drain electrode of the plurality of MOS transistors are respectively connected in parallel.

  According to the present invention, it is possible to provide a high-frequency power amplifier and a portable wireless terminal that are less likely to reduce output during operation, less affected by thermal noise, stable in high-frequency operation, and excellent in reliability.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
A high frequency power amplifier according to a first embodiment of the present invention will be described with reference to FIGS. The high-frequency power amplifier according to this embodiment includes a plurality of N-type MOS transistors 1, and the layout of these transistors 1 is shown in FIG. 2 is a cross-sectional view taken along the cutting line AA shown in FIG. 1, and FIG. 3 is a diagram showing an equivalent circuit of these transistors 1 shown in FIG.

  These transistors 1 are formed on a P-type semiconductor substrate, for example, a P-type silicon substrate 2. As shown in the equivalent circuit of FIG. 3, the high-frequency power amplifier of this embodiment is configured by connecting a plurality of transistors 1 in parallel so that a large drain current can flow. Each transistor 1 is formed in an element region 4 separated by an element isolation region 3. Each transistor 1 includes an N-type source region 6 and drain region 5 that are formed apart from the element region 4, and gate insulation formed on the element region 4 between the source region 6 and the drain region 5. A film 7, a gate electrode 12 formed on the gate insulating film 7, and a source electrode 14 and a drain electrode 13 connected to the source region 6 and the drain region 5, respectively. The gate electrode 12, the drain electrode 13, and the source electrode 14 of each transistor 1 are respectively connected to a gate electrode wiring 12A, a drain electrode wiring 13A, and a source electrode wiring 14A that extend in the direction in which the plurality of transistors are arranged. Yes.

In a MOS transistor, since the resistance of a gate electrode is generally high, it is disadvantageous to make one gate electrode long, particularly when operating at high speed. Therefore, in order to realize a transistor having a large channel width W, it is necessary to divide the gate electrode and connect a plurality of transistors in parallel. In the present embodiment, in order to suppress the influence of heat generation, individual transistors connected in parallel are separated from adjacent transistors by a device isolation region 3 at a constant interval. The element isolation region 3 is formed by an insulating film provided on the semiconductor substrate 2. In general, silicon dioxide (SiO ₂ ) is used as the material of the insulating film.

  In this embodiment, a short-circuited closed loop 17 formed of at least one of the same material layer and metal wiring layer as the gate electrode is disposed on the element isolation region 3 that separates the transistors disposed adjacent to each other. ing. This closed loop 17 is preferably arranged as close to the transistor as possible. The closed loop 17 is connected to a constant voltage source via a resistor 20. In the present embodiment, the P-type substrate 2 is connected via the contact 18. Here, the contact resistance of the contact portion 18 and the substrate resistance of the P-type substrate 2 are used. In the present embodiment, in the transistors arranged adjacent to each other with the closed loop 17 interposed therebetween, the electrodes closest to the closed loop 17 are different electrodes. That is, as the electrode closest to the closed loop 17, if one of the adjacently arranged transistors is a drain electrode, it is a source electrode in the other transistor. If it is a source electrode, it is also a drain electrode in the other transistor. However, in a transistor arranged adjacent to the closed loop 17, the electrode closest to the closed loop 17 may be the same type of electrode.

  Next, a high-frequency power amplifier according to a comparative example of the present embodiment is shown in FIGS. 4 is a plan view of a MOS transistor of a high-frequency power amplifier according to a comparative example, and FIG. 5 is a cross-sectional view taken along the cutting line BB in FIG. FIG. 6 is an equivalent circuit of the transistor shown in FIG.

  The high-frequency power amplifier of this comparative example also has a plurality of N-type MOS transistors. These transistors are also formed on the P-type silicon substrate 2. Further, as shown in the equivalent circuit of FIG. 6, it is the same as in the first embodiment in that it is connected in parallel so that a large drain current can flow. Each transistor is formed in the element region 4. Each transistor includes an N-type source region 6 and a drain region 5 formed apart from the element region 4, and a gate insulating film formed on the element region 4 between the source region 6 and the drain region 5. 7, a gate electrode 12 formed on the gate insulating film 7, and a source electrode 14 and a drain electrode 13 connected to the source region 6 and the drain region 5, respectively. The gate electrode 12, the drain electrode 13, and the source electrode 14 of each transistor are connected to a gate electrode wiring 12A, a drain electrode wiring 13A, and a source electrode soldier 14A that extend in the direction in which the plurality of transistors are arranged. .

  In the comparative example, adjacently arranged transistors share either the source region or the drain region. Therefore, unlike the present embodiment, the transistors are not separated by the element isolation region. Therefore, there is no room for providing the closed loop of the first embodiment. Such a layout arrangement is generally used in a conventional high-frequency CMOS, and has an advantage that an installation area of a transistor can be saved.

Next, the operating temperature and output characteristics of the transistors of this embodiment and the comparative example are compared. Here, it is assumed that the total channel width W is about 3000 μm, and that the transistor consumes about 4 W of power Q ₀ at room temperature T ₀ . Since this power consumption is converted into thermal energy, the temperature of the transistor rises. When the temperature increases, for example, the mobility of electrons decreases, so that the output of the transistor decreases.

Here, when the heat generation amount per unit time in the transistor is Q, the temperature dependence of Q can be expressed by the following equation.

Here, I _D is a drain current and a function of temperature, and V _D is a drain voltage and does not depend on temperature. Further, it is assumed that the drain current _ID is proportional to the mobility μ, and the cause of the temperature change of the drain current _ID is mainly caused by the temperature change of the mobility μ. It is known that the mobility μ varies with temperature as follows.

The temperature dependence of the calorific value Q is shown in FIG. Here, the constant μ _TE representing the temperature dependence was set to −1.335. Even if the heat generation amount Q ₀ at room temperature is about 4 W, as the temperature rises, the mobility μ decreases, so the drain current _ID decreases and the heat generation amount Q also decreases. As long as the same process is used, the calorific value Q depends only on the channel width W of the transistor and does not depend on the layout density. Therefore, the curve showing the temperature dependence of the calorific value shown in FIG. This is considered to be common with the comparative example.

Next, the exhaust heat characteristics are examined. The heat generated by the transistor is mainly discharged through the silicon substrate. It is known that the thermal conductivity λ of silicon is 148 W / mK. In the case of the comparative example, when transistors with a channel width W = 3000 μm are densely arranged as shown in FIGS. 4 and 5, the transistors can be laid out in an area A of about 8900 μm ² . The thickness d of the silicon substrate is 0.5 mm. Using these values, the thermal resistance _RT can be estimated by the following equation.

  In the case of the comparative example, a value of about 380 K / W is obtained for the thermal resistance. Using this thermal resistance, FIG. 7 shows the exhaust heat characteristics of the comparative example. It is considered that the steady state is reached at the point where the calorific value and the exhaust heat amount are just balanced. In the case of the comparative example, at about 465 ° C., the power consumption at this time is about 1.15 W.

On the other hand, in the first embodiment, transistors having the same channel width W can be laid out in an area of 68000 μm ² by the arrangement as shown in FIGS. Using the same formula as in the comparative example, the thermal resistance of this embodiment is estimated to be about 50 K / W. FIG. 7 also shows the exhaust heat characteristics in this embodiment. In a steady state in which the amount of heat generation and the amount of exhaust heat are just balanced, in this embodiment, the power consumption is about 150 ° C., and the power consumption of the transistor is about 2.46 W.

To summarize the above results, there is a difference between the first embodiment and the comparative example as shown in Table 1 below, even though the transistors have the same channel width W.

  From this table, the present embodiment has a disadvantage that the layout area is large, but the operating temperature is low and the power consumption is large. The comparative example has a feature that the layout area is small, but the operating temperature is high and the power consumption is small. It is known that the operating temperature is a factor that governs the reliability of the transistor, and the higher the operating temperature, the shorter the breakdown time. Therefore, the operating temperature is preferably low from the viewpoint of transistor reliability. Therefore, it is considered that a certain layout area or more is necessary from the viewpoint of ensuring reliability. Further, when the channel temperature of the transistor is high, thermal noise is generated. In order to increase the ratio of signal to noise, it is preferable that the operating temperature of the transistor be low.

  In the high frequency power amplifier, power added efficiency is defined by the ratio of the sum of the power input from the DC voltage source and the high frequency input power and the high frequency output power. In portable devices, a high frequency power amplifier with high power added efficiency is required because a battery is used as a power source. The power added efficiency is mainly governed by the circuit type, and most of the unused power is consumed in the transistor. If it is assumed that an amplifier with a constant power efficiency is used, high frequency output power can be increased by using a transistor with high power consumption for the amplifier.

  As described above, the transistor according to this embodiment is superior in reliability, low noise, and output power when used for a high-frequency power amplifier as compared with the transistor according to the comparative example.

  By the way, it is known that when a transistor divided into a plurality as shown in the present embodiment is used for a high frequency power amplifier, an unexpected parasitic oscillation occurs at a high frequency. For example, in Japanese Patent Application Laid-Open No. 2004-336445, as a problem to be solved in a high output power amplifier transistor, when many transistors are coupled in parallel, parasitic oscillation (closed loop oscillation) generated by many closed loops formed between the transistors is disclosed. ) Occurs. Also in this embodiment, since a plurality of transistors are arranged apart from each other and a large number of closed loops are formed between the transistors, unexpected parasitic oscillation may occur in a high frequency band.

  However, in the present embodiment, for the purpose of suppressing such parasitic oscillation, as shown in FIGS. 1 and 2, a short-circuited closed loop 17 is disposed between adjacent transistors. ing. The short-circuited closed loop 17 is preferably connected to a constant voltage via a resistor from at least one place in order to prevent a DC floating potential.

  In the short-circuited closed loop 17, when a magnetic flux tries to penetrate therethrough for some reason, a closed loop current flows so as to cancel the magnetic flux, thereby canceling the magnetic flux. Therefore, it is possible to weaken the coupling via magnetic flux with the external circuit or other parts of the transistor constituting the amplifier, and to prevent noise and unexpected parasitic oscillation via the magnetic coupling. .

  Next, the difference caused by the presence or absence of the shorted closed loop 17 will be described with reference to FIGS. FIG. 8 is a diagram showing a layout and loop current when the short-circuit closed loop 17 is arranged between adjacent transistors as in the present embodiment, and FIG. 9 is a cross-sectional view taken along the section line CC shown in FIG. It is. FIG. 10 is a diagram showing a layout and a loop current when the shorted closed loop is not arranged, and FIG. 11 is a cross-sectional view taken along the cutting line DD shown in FIG.

First, as shown in FIG. 10, when the closed loop 17 that is short-circuited is not provided, when a loop current 21 flows between adjacent transistors, the magnetic flux 23 is caused to flow in the direction indicated by the arrow in FIG. appear. The electromotive force V ₁ generated by the loop current 21 can be expressed by the following equation, where L ₁ is the self-inductance of the loop and I ₁ is the value of the loop current 21.

Next, as shown in FIG. 8, when provided with a closed loop 17 which is short-circuited between the transistors adjacent the loop of the self-inductance of the transistor is formed as L _1, the self-inductance of the loop 17, which is an inductance short L _If the mutual inductance between these two loops is M, the following relational expression is established between them.

Here, k is a coupling coefficient indicating the strength of magnetic coupling between the two loops. The back electromotive force V ₂ generated when the loop current 22 flows through the shorted closed loop 17 is the value of the loop current 21 flowing through the loop formed by the transistor I ₁ and the value of the current 22 flowing through the closed loop 17. Assuming I ₂ , it is expressed by the following formula.

If the loop resistance of the shorted closed loop 17 is sufficiently small and the generated back electromotive force can be regarded as V ₂ = 0, the following relationship is obtained.

Therefore, the back electromotive force V ₁ generated in the loop formed between the adjacent transistors is expressed by the following equation by the loop current 21 flowing in this loop.

In this expression, the magnitude of the back electromotive force V ₂ generated by the time change of the same loop current I ₁ is (1−k ² ) times when the shorted closed loop 17 is provided and when it is not provided. It is shown that. Therefore, it can be seen that the larger the mutual inductance M between the two loops, in other words, the stronger the coupling between the two loops, the greater the effect of suppressing the occurrence of back electromotive force. This is because when a loop current 21 flows in a loop formed by adjacent transistors, a magnetic flux 23 is generated in the direction indicated by the solid arrow in FIG. 9, but an induced current 22 is generated in the closed loop 17 that is short-circuited at the same time. This is because the magnetic flux 24 is generated in the direction indicated by the one-dot chain line arrow in FIG.

  As described above, according to the present embodiment, the channel temperature rises in order to efficiently discharge the heat generated in the channel when large power is applied to the MOS transistor formed on the silicon substrate to the outside. Can be suppressed, the output can be prevented from decreasing, and the influence of thermal noise can be suppressed. Further, it is possible to obtain a high-frequency power amplifier that operates stably and has excellent reliability by suppressing back electromotive force and parasitic oscillation induced in a closed loop formed between adjacent transistors.

(Second Embodiment)
Next, a high frequency power amplifier according to a second embodiment of the present invention will be described with reference to FIGS. The high-frequency power amplifier of this embodiment includes a plurality of N-type MOS transistors 40, and the layout of these transistors 40 is shown in FIG. 13 is a cross-sectional view taken along the cutting line AA shown in FIG. 12, and FIG. 14 is a diagram showing an equivalent circuit of these transistors 40 shown in FIGS.

  The N-type MOS transistor 40 according to the present embodiment is formed on a P-type semiconductor substrate, for example, a P-type silicon substrate 2, as in the first embodiment. A plurality of transistors 40 are connected in parallel so that a large drain current can flow. Each transistor 40 is formed in the element region 4 separated by the element isolation region 3. Each transistor 40 includes an N-type source region 6 and drain region 5 that are formed apart from the device region 4, and gate insulation formed on the device region 4 between the source region 6 and the drain region 5. A film 7, a gate electrode 12 formed on the gate insulating film 7, and a source electrode 14 and a drain electrode 13 connected to the source region 6 and the drain region 5, respectively. The gate electrode 12, the drain electrode 13, and the source electrode 14 of each transistor 40 are respectively connected to a gate electrode wiring 12A, a drain electrode wiring 13A, and a source electrode wiring 14A that extend in the direction in which the plurality of transistors are arranged. Yes.

  Also in the second embodiment, in order to suppress the influence of heat generation, individual transistors 40 connected in parallel are separated from adjacent transistors by a device isolation region 3 at a constant interval.

  Also in the second embodiment, a short-circuited closed loop 17 is disposed between adjacent transistors. The difference from the first embodiment is that the shorted closed loop 17 is formed by the same wiring layer as the gate electrode 12. The closed loop 17 is once connected to another wiring layer via the via 25 and further connected to the P-type substrate 2 via the contact 18.

  In the present embodiment, in the transistors arranged adjacent to each other with the closed loop 17 interposed therebetween, unlike the first embodiment, the electrode closest to the closed loop 17 is the same type of electrode. That is, as an electrode closest to the closed loop 17, if one of the adjacent transistors is a drain electrode, the other transistor is also a drain electrode. If it is a source electrode, it is also a source electrode in the other transistor. However, as in the first embodiment, in a transistor arranged adjacent to the closed loop 17, the electrode closest to the closed loop 17 may be a different type of electrode.

  In the second embodiment, the shorted closed loop 17 is formed using the same wiring layer as the gate electrode 12, so that a part of the closed loop 17 is parallel to the drain electrode 13 or the source electrode 14. 4 is formed. For this reason, the closed loop 17 can be arranged as close to the transistor as possible. Thereby, the mutual inductance M between the shorted closed loop 17 and the loop formed between adjacent transistors can be increased, and the magnetic coupling coefficient k can be increased. Therefore, the counter electromotive force generated when the loop current flows in the closed loop can be greatly reduced.

  Further, in comparison with the first embodiment, in the second embodiment, the channel portion of the transistor can be arranged away from the element isolation region 3. Thereby, the influence which the stress which arises in the element region 4 in the process of forming the element isolation region 3 has on the transistor characteristics can be reduced.

  When attention is paid to one short-circuited closed loop 17 in the second embodiment, the transistors are arranged so as to be in contact with the sources or drains of the transistors arranged on both sides thereof. FIGS. 14A and 14B are equivalent circuits showing the effects of the layout arrangement of the second embodiment. FIG. 14A shows a case where the short-circuited closed loop 17 is arranged so as to be close to only the sources of the transistors arranged on both sides by the layout arrangement of the second embodiment, and FIG. Unlike the arrangement of the configuration, the shorted closed loop 17 is an equivalent circuit in the case where one of the transistors arranged on both sides thereof is arranged close to the source and the other is arranged close to the drain. In both cases, the short-circuited closed loop 17 is connected to the ground potential via a resistor 20. In the arrangement shown in FIG. 14B, when the drain potential of one transistor fluctuates at a high speed due to a high-frequency signal, the influence may be transmitted to the source potential of an adjacent transistor through a parasitic capacitance. On the other hand, in the case of the arrangement of the second embodiment shown in FIG. 14A, the coupling via the parasitic capacitance connects the sources or drains of adjacent transistors, so that the high frequency signal is used. Less susceptible to potential fluctuations.

  Similarly to the first embodiment, this embodiment also increases the channel temperature in order to efficiently discharge the heat generated in the channel when a large amount of power is applied to the MOS transistor formed on the silicon substrate. It is possible to suppress, prevent a decrease in output, and suppress the influence of thermal noise. Further, it is possible to obtain a high-frequency power amplifier that operates stably and has excellent reliability by suppressing back electromotive force and parasitic oscillation induced in a closed loop formed between adjacent transistors.

(Third embodiment)
Next, a high frequency power amplifier according to a third embodiment of the present invention will be described with reference to FIGS. The high-frequency power amplifier of this embodiment includes a plurality of N-type MOS transistors 50, and the layout of these transistors 50 is shown in FIG. 16 is a cross-sectional view taken along the cutting line AA shown in FIG.

  The N-type MOS transistor 50 according to the present embodiment is formed on a P-type semiconductor substrate, for example, a P-type silicon substrate 2, as in the first embodiment. A plurality of transistors 50 are connected in parallel so that a large drain current can flow. Each transistor 50 is formed in the element region 4. Each transistor 1 includes an N-type source region 6 and drain region 5 that are formed apart from the element region 4, and gate insulation formed on the element region 4 between the source region 6 and the drain region 5. A film 7, a gate electrode 12 formed on the gate insulating film 7, and a source electrode 14 and a drain electrode 13 connected to the source region 6 and the drain region 5, respectively. The gate electrode 12, the drain electrode 13, and the source electrode 14 of each transistor 50 are respectively connected to a gate electrode wiring 12A, a drain electrode wiring 13A, and a source electrode wiring 14A that extend in the direction in which the plurality of transistors are arranged. Yes.

  Also in the third embodiment, in order to suppress the influence of heat generation, the individual transistors 50 connected in parallel are separated from the adjacent transistors at a constant interval, and the closed loop 17 short-circuited between the adjacent transistors. Is provided. In the first and second embodiments, an element isolation region is provided between adjacent transistors and is electrically isolated. In the third embodiment, however, the shorted closed loop 17 is a dummy gate. It consists of electrodes and is separated only by this dummy gate electrode 17. The dummy gate electrode 17 is formed of the same layer as the gate electrode 12 and is kept at a constant potential so that the channel is not turned on. As a result, adjacent transistors are electrically isolated although no element isolation region is provided.

  In the present embodiment, in the transistors arranged adjacent to each other with the closed loop 17 interposed therebetween, the electrode closest to the closed loop 17 is the same type of electrode as in the second embodiment. That is, as an electrode closest to the closed loop 17, if one of the adjacent transistors is a drain electrode, the other transistor is also a drain electrode. If it is a source electrode, it is also a source electrode in the other transistor. However, in the transistors arranged adjacent to each other with the closed loop 17 interposed therebetween, as in the first embodiment, the electrode closest to the closed loop 17 may be a different type of electrode.

In general, SiO ₂ is used as the material of the element isolation region, but the thermal conductivity of SiO ₂ is 1/100 or less compared to a silicon single crystal. For this reason, it is better from the viewpoint of heat dissipation not to provide an element isolation region made of SiO ₂ . Therefore, the transistor according to the third embodiment is expected to be further superior in reliability, low noise, and output power as the transistor of the high-frequency power amplifier than the transistors according to the first and second embodiments.

  Also in the third embodiment, a short-circuited closed loop is disposed between adjacent transistors, but the difference in configuration from the second embodiment is that the short-circuited closed loop has an element. It also serves as a dummy gate electrode 17 provided for separation. A plurality of in-loop contacts 27 connected to an N-type diffusion layer 29 provided immediately below the closed loop 17 are provided. A metal wiring is connected to the contact 27 in the loop, and heat generated from the transistor via the metal wiring is easily released to the outside through the diffusion layer 29. A constant potential is applied to the in-loop contacts 27, and the in-loop contacts 27 are arranged in a lattice pattern.

  Similarly to the first embodiment, this embodiment also increases the channel temperature in order to efficiently discharge the heat generated in the channel when a large amount of power is applied to the MOS transistor formed on the silicon substrate. It is possible to suppress, prevent a decrease in output, and suppress the influence of thermal noise. Further, it is possible to obtain a high-frequency power amplifier that operates stably and has excellent reliability by suppressing back electromotive force and parasitic oscillation induced in a closed loop formed between adjacent transistors.

(Fourth embodiment)
Next, FIG. 17 shows a block diagram of a transmission circuit of a portable wireless terminal according to the fourth embodiment of the present invention. The portable wireless terminal of this embodiment includes any one of the power amplifiers of the first to third embodiments. In this transmission circuit, orthogonal digital signals I and Q are received from a baseband circuit (not shown), and modulated by a high-frequency signal so that the phases differ by 90 degrees in the mixers MIX1 and MIX2 of the local oscillator LO. The modulated signal is added by the adder AD, and then passes through the band pass filter BPF. The signal that has passed through the bandpass filter BPF is amplified by the power amplifier PA and radiated as an electromagnetic wave from the antenna ANT. The power amplifier of any one of the first to third embodiments is used as the power amplifier PA.

  As described above, by using the high-frequency power amplifier according to any one of the first to third embodiments, a portable wireless terminal that is less affected by thermal noise, stable in high-frequency operation, and excellent in reliability is obtained. be able to.

The figure which shows the layout of the MOS transistor which concerns on the high frequency power amplifier by 1st Embodiment. Sectional drawing of the MOS transistor which concerns on the high frequency power amplifier by 1st Embodiment. The equivalent circuit schematic of the MOS transistor which concerns on the high frequency power amplifier by 1st Embodiment. The figure which shows the layout of the MOS transistor which concerns on the comparative example of 1st Embodiment. Sectional drawing of the MOS transistor which concerns on a comparative example. The equivalent circuit schematic of the MOS transistor which concerns on a comparative example. The figure which shows the relationship between the heat balance and output power in 1st Embodiment and a comparative example. The figure which shows a layout and loop current in case there exists a shorted closed loop. The figure which shows the magnetic flux produced | generated in the cross section cut | disconnected by the cutting line CC shown in FIG. The figure which shows a layout and loop current when there is no shorted closed loop. The figure which shows the magnetic flux produced | generated in the cross section cut | disconnected by the cutting line DD shown in FIG. The figure which shows the layout of the MOS transistor which concerns on the high frequency power amplifier by 2nd Embodiment. Sectional drawing of the MOS transistor which concerns on the high frequency power amplifier by 2nd Embodiment. The equivalent circuit schematic of the MOS transistor which concerns on the high frequency power amplifier by 2nd Embodiment. The figure which shows the layout of the MOS transistor which concerns on the high frequency power amplifier by 3rd Embodiment. Sectional drawing of the MOS transistor which concerns on the high frequency power amplifier by 3rd Embodiment. The block diagram of the transmission circuit of the portable radio | wireless terminal by 4th Embodiment.

Explanation of symbols

1 N-type MOS transistor 2 P-type semiconductor substrate 3 Element isolation region 4 Element region 5 Drain region 6 Source region 7 Gate insulating film 12 Gate electrode 13 Drain electrode 14 Source electrode 17 Shorted closed loop 18 Substrate contact 20 Resistance 21 Between adjacent transistors Loop current 22 flowing through the short-circuited closed loop 23 magnetic flux generated by the loop current flowing between adjacent transistors 24 magnetic flux generated by the loop current flowing through the short-circuited closed loop 25 Connecting the short-circuited closed loop and the substrate contact Wiring via 26 for parasitic capacitance 27 between shorted closed loop and source, or between shorted closed loop and drain 27 In-loop contact

Claims (8)

A plurality of MOS transistors arranged in parallel on a semiconductor substrate, each having a source electrode, a gate electrode, and a drain electrode;
A closed loop comprising a short-circuited conductor provided between adjacent MOS transistors of the plurality of MOS transistors;
And a source electrode, a gate electrode, and a drain electrode of the plurality of MOS transistors are connected in parallel, respectively.   2. The high frequency power amplifier according to claim 1, wherein the closed loop is connected to a constant voltage source via a resistor.   3. The high-frequency power amplifier according to claim 1, wherein the plurality of MOS transistors are formed in element regions separated by element isolation regions, and the closed loop is formed in the element isolation region.   The plurality of MOS transistors are each formed in an element region separated by an element isolation region, and a part of the closed loop is formed in the element region and the remaining part is formed in the element isolation region. Item 3. The high frequency power amplifier according to Item 1 or 2.   3. The high frequency power amplifier according to claim 1, wherein the plurality of MOS transistors are formed in the same element region, and a part of the closed loop is a dummy gate electrode.   6. The high frequency power amplifier according to claim 4, wherein at least a part of the closed loop is formed of the same wiring layer as the gate electrodes of the plurality of MOS transistors.   7. The high-frequency power amplifier according to claim 1, wherein an electrode of an adjacent MOS transistor disposed closest to the closed loop is a source electrode or a drain electrode.   A portable wireless terminal comprising the transmission circuit including the power amplifier according to claim 1.

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