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JP2008235627A - Bga semiconductor component and printed circuit board for mounting the same - Google Patents

Bga semiconductor component and printed circuit board for mounting the same Download PDF

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JP2008235627A
JP2008235627A JP2007074027A JP2007074027A JP2008235627A JP 2008235627 A JP2008235627 A JP 2008235627A JP 2007074027 A JP2007074027 A JP 2007074027A JP 2007074027 A JP2007074027 A JP 2007074027A JP 2008235627 A JP2008235627 A JP 2008235627A
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bga
conductor pattern
square
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semiconductor component
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Teruyuki Ozaki
輝行 尾崎
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Kenwood KK
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed circuit board for mounting a BGA semiconductor component thereon on which the BGA semiconductor component having pins arranged in 5 rows from its outside can be mounted and which can has a low manufacturing cost. <P>SOLUTION: In the printed circuit board for mounting thereon the BGA semiconductor component having BGA connection pads 1a formed at respective lattice points, an inner layer conductor pattern 2, single-layer through via holes 13, BGA connection pads, and a surface layer conductor pattern 1 are sequentially laminated, full-layer through via holes 18 are formed in the laminate, the BGA connection pads arranged in first and second rows are connected with the outside of a region via the surface layer conductor pattern, the BGA connection pads arranged in third and fourth rows are connected with the outside of the region through the surface layer conductor pattern, the single-layer through via holes and the inner layer conductor pattern, and the BGA connection pads arranged in a fifth row are connected with the outside of the region through the surface layer conductor pattern and the full-layer through via holes and through the inner layer conductor pattern or a back-layer conductor pattern as their lower layers. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明はBGA半導体部品実装用プリント基板に係わり、特に、5列に形成された端子を有するBGA半導体部品が実装可能であり、しかも製造コストの安いBGA半導体部品実装用プリント基板に関する。   The present invention relates to a printed circuit board for mounting a BGA semiconductor component, and more particularly to a printed circuit board for mounting a BGA semiconductor component on which BGA semiconductor components having terminals formed in five rows can be mounted and whose manufacturing cost is low.

BGA(ボールグリッドアレイ)半導体部品はパッケージの裏面に格子状に配列されたボール状半田(BGA)が回路接続用に設けられている。プリント基板のBGA接続用パッドにクリーム半田が塗られてその上にBGA半導体部品のボール状半田を合わせてリフロー炉を通すことによりBGA接続用パッドがBGA半導体部品の端子と電気的に接続される。   BGA (Ball Grid Array) semiconductor components are provided with ball solder (BGA) arranged in a grid on the back of the package for circuit connection. Cream solder is applied to the BGA connection pads on the printed circuit board, and the ball-shaped solder of the BGA semiconductor component is put on it and passed through a reflow furnace, whereby the BGA connection pads are electrically connected to the terminals of the BGA semiconductor component. .

図3にBGA半導体部品実装用プリント基板のBGA接続用パッドの例を示す。このプリント基板には内側正方形と外側正方形とで囲まれたロ字型領域の表面に外側から内側に向けて5列に形成された各格子点に夫々BGA接続用パッド1aが形成されている。BGA接続用パッド1a、1a…のピッチは500μmである。   FIG. 3 shows an example of a BGA connection pad of a printed circuit board for mounting a BGA semiconductor component. On this printed circuit board, BGA connection pads 1a are formed at the respective lattice points formed in five rows from the outside to the inside on the surface of the square-shaped region surrounded by the inner square and the outer square. The pitch of the BGA connection pads 1a, 1a... Is 500 μm.

ところで、プリント基板の配線パターンの間隔(ピッチ)は250μmより小さくすることは困難である。そこで、BGA半導体部品のICで図3に示すようにピンピッチが500μmと狭く、外側から内側に向けて5列に配列されたピン数の多いものを実装するプリント基板には図4に示すうな2段のビルドアップ基板が用いられていた。   Incidentally, it is difficult to make the interval (pitch) between the wiring patterns of the printed circuit board smaller than 250 μm. Therefore, the BGA semiconductor component IC has a pin pitch as narrow as 500 μm as shown in FIG. 3 and a printed circuit board on which a large number of pins arranged in five rows from the outside to the inside are mounted as shown in FIG. A staged build-up board was used.

図4に示す2段のビルドアップ基板の製造方法を説明する。図4に示す絶縁層7はコア層を構成している。この絶縁層7の表面(上面)および裏面(下面)に導体膜を施し、感光・エッチングにより配線パターン3および4が形成される。さらに、その両面に感光性樹脂を積層して、ビルドバイアホール(VIA)15、16(単層貫通バイアホール)を形成する位置に感光・エッチングにより孔を形成する。   A method for manufacturing the two-stage buildup substrate shown in FIG. 4 will be described. The insulating layer 7 shown in FIG. 4 constitutes a core layer. Conductive films are applied to the front surface (upper surface) and back surface (lower surface) of the insulating layer 7, and the wiring patterns 3 and 4 are formed by photosensitizing and etching. Further, a photosensitive resin is laminated on both surfaces, and holes are formed by photosensitizing and etching at positions where build via holes (VIA) 15 and 16 (single layer through via holes) are formed.

この感光性樹脂は硬化することにより絶縁層8および10となる。この絶縁層8および10の上に導体膜を施し、感光・エッチングにより配線パターン2、ビルドバイアホール15および配線パターン5、ビルドバイアホール16が夫々形成される。   This photosensitive resin becomes insulating layers 8 and 10 by curing. A conductor film is applied on the insulating layers 8 and 10, and the wiring pattern 2, the build via hole 15, the wiring pattern 5, and the build via hole 16 are formed by photosensitive and etching.

さらに、この絶縁層8および10の上に感光性樹脂を積層してビルドバイアホール13、14を形成する位置に感光・エッチングにより孔を形成する。この感光性樹脂は硬化することにより絶縁層9および11となる。この絶縁層9および11の上に導体膜を施し、感光・エッチングにより配線パターン1、BGA接続用パッド1a、ビルドバイアホール13および配線パターン6、ビルドバイアホール14が夫々形成される。   Further, a photosensitive resin is laminated on the insulating layers 8 and 10 to form holes at the positions where the build via holes 13 and 14 are formed by photosensitizing and etching. This photosensitive resin becomes insulating layers 9 and 11 by curing. A conductor film is applied on the insulating layers 9 and 11, and the wiring pattern 1, the BGA connection pad 1a, the build via hole 13, the wiring pattern 6, and the build via hole 14 are formed by photosensitizing and etching.

このように積層された基板にドリルにより孔が開けられ全層貫通ホール(スルーホール)18が形成される。上記したプリント基板はビルドバイアホール(単層貫通バイアホール)が表裏各2段に形成されているので、2段ビルドアップ基板と呼ばれている。   Holes are drilled in the thus-laminated substrates by drills, and all layer through holes (through holes) 18 are formed. The above-described printed circuit board is called a two-stage build-up board because build via holes (single layer through via holes) are formed in two stages on each side.

この2段ビルドアップ基板を上記した外側から5列に配列されたピンを有するBGA半導体部品を実装する場合、外側2列のBGA接続用パッド1aは表面の配線パターン1により外側に接続される。この配線パターンのピッチは250μとなる。   When the BGA semiconductor component having the pins arranged in five rows from the outside described above is mounted on the two-stage buildup board, the BGA connection pads 1a in the two outside rows are connected to the outside by the wiring pattern 1 on the surface. The pitch of this wiring pattern is 250 μm.

外側から3列目および4列目のBGA接続用パッド1aは配線パターン1、ビルドバイアホール13を介して配線パターン2に接続され、表面から2層目の配線パターン2により外側に接続される。この配線パターンのピッチは250μとなる。   The BGA connection pads 1a in the third and fourth rows from the outside are connected to the wiring pattern 2 via the wiring pattern 1 and the build via hole 13, and are connected to the outside by the second wiring pattern 2 from the surface. The pitch of this wiring pattern is 250 μm.

外側から5列目のBGA接続用パッド1aは配線パターン1、ビルドバイアホール13、配線パターン2、ビルドバイアホール15を介して表面から3層目の配線パターン3により外側に接続される。この配線パターンのピッチは500μとなる。   The BGA connection pads 1a in the fifth row from the outside are connected to the outside by the third wiring pattern 3 from the surface through the wiring pattern 1, the build via hole 13, the wiring pattern 2, and the build via hole 15. The pitch of this wiring pattern is 500 μm.

このように、従来の外側から5列に形成された端子を有するBGA半導体部品は2段のビルドアップ基板により実装されていたが、2段のビルドアップ基板はビルドバイアホールを2段に形成するために、絶縁層に2回に亙り孔を形成しなければならず製造コストが高くなるという問題があった。   Thus, the conventional BGA semiconductor component having terminals formed in five rows from the outside is mounted by a two-stage buildup board, but the two-stage buildup board forms a build via hole in two stages. For this reason, there has been a problem in that the manufacturing cost is increased because holes must be formed twice in the insulating layer.

特開平10−284846号公報に提案されたボールグリッドアレイパッケージ型半導体部品の実装構造では、1段ビルドアップ基板が用いられている。しかしながらこのボールグリッドアレイパッケージ型半導体部品の実装構造は外側から4列に配列されたピンを有するBGA半導体部品を実装するものであり、外側から5列に配列されたピンを有するBGA半導体部品を実装することができない。
特開平10−284846号公報、段落0018〜段落0023、図1〜図3
In the ball grid array package type semiconductor component mounting structure proposed in Japanese Patent Laid-Open No. 10-284846, a one-stage build-up substrate is used. However, this ball grid array package type semiconductor component mounting structure is for mounting BGA semiconductor components having pins arranged in four rows from the outside, and mounting BGA semiconductor components having pins arranged in five rows from the outside. Can not do it.
JP-A-10-284846, paragraphs 0018 to 0023, FIGS. 1 to 3

この発明は上記した点に鑑みてなされたものであって、その目的とするところは、外側から5列に配列されたピンを有するBGA半導体部品を実装することができ、しかも、製造コストの安いBGA半導体部品実装用プリント基板を提供することにある。   The present invention has been made in view of the above points. The object of the present invention is to mount BGA semiconductor components having pins arranged in five rows from the outside, and at a low manufacturing cost. It is to provide a printed circuit board for mounting a BGA semiconductor component.

この発明のBGA(ボールグリッドアレイ)半導体部品は、底面の内側正方形と外側正方形とで囲まれたロ字型領域の表面に前記外側正方形の夫々の辺に近接する第1列から内側に向けて第5列まで5列に形成された各格子点に夫々BGA接続端子を形成したBGA半導体部品において、前記外側正方形の夫々の辺に近接する外側から内側に向かって第5列の前記各格子点のBGA接続端子にはGND端子、電源端子またはNC端子のいずれかが配置されるものである。   The BGA (Ball Grid Array) semiconductor component according to the present invention is directed from the first row adjacent to each side of the outer square toward the inside on the surface of the square-shaped region surrounded by the inner square and the outer square on the bottom surface. In a BGA semiconductor component in which a BGA connection terminal is formed at each of the lattice points formed in five rows up to the fifth row, each of the lattice points in the fifth row from the outer side close to the respective sides of the outer square toward the inner side Any of a GND terminal, a power supply terminal, and an NC terminal is disposed on the BGA connection terminal.

また、この発明のBGA半導体部品実装用プリント基板は、内側正方形と外側正方形とで囲まれたロ字型領域の表面に前記外側正方形の夫々の辺に近接する第1列から内側に向けて第5列まで5列に形成された各格子点に夫々BGA接続用パッドを形成したBGA半導体部品実装用プリント基板において、ベース基板の表面側に内層導体パターン、表面側絶縁層、単層貫通バイアホールとBGA接続用パッドと表層導体パターンとが順次積層されており、さらに、前記内側正方形の内部に全層貫通バイアホールが形成されており、第1列および第2列のBGA接続用パッドは表層導体パターンを介して前記ロ字型領域外に接続され、第3列および第4列のBGA接続用パッドは表層導体パターン、単層貫通バイアホールおよび内層導体パターンを介して前記ロ字型領域外に接続され、第5列のBGA接続用パッドは表層導体パターン、全層貫通バイアホールおよび前記内層導体パターンより下層の内層導体パターンまたは裏層導体パターンを介して前記ロ字型領域外に接続されているものである。   Also, the printed circuit board for mounting a BGA semiconductor component according to the present invention has a first surface inward from the first row adjacent to each side of the outer square on the surface of the square-shaped region surrounded by the inner square and the outer square. In a printed circuit board for mounting BGA semiconductor components, in which BGA connection pads are formed at each lattice point formed in 5 rows up to 5 rows, an inner layer conductor pattern, a surface side insulating layer, a single layer through via hole on the surface side of the base substrate , BGA connection pads, and surface layer conductor patterns are sequentially laminated, and all layer through via holes are formed in the inner square, and the BGA connection pads in the first and second rows are formed on the surface layer. The BGA connection pads in the third row and the fourth row are connected to the outside of the square-shaped region through the conductor pattern, and the surface layer conductor pattern, the single layer through via hole, and the inner layer conductor pattern The BGA connection pads in the fifth row are connected to the outside of the square-shaped region through the surface layer conductor pattern, all-layer through via holes, and the inner layer conductor pattern or the back layer conductor pattern below the inner layer conductor pattern. It is connected outside the square-shaped region.

また、前記BGA半導体部品実装用プリント基板において、前記第5列のBGA接続用パッドにはBGA半導体部品のGND端子、電源端子またはNC端子のいずれかが接続されるものである。   In the printed circuit board for mounting a BGA semiconductor component, any of the GND terminal, the power supply terminal, or the NC terminal of the BGA semiconductor component is connected to the BGA connection pad in the fifth row.

この発明のBGA半導体部品およびBGA半導体部品実装用プリント基板によれば、外側から5列に配列されたピンを有するBGA半導体部品を実装することができる。しかも、1段ビルドアップ基板であるため、プリント基板の製造コストが安い。   According to the BGA semiconductor component and the printed circuit board for mounting a BGA semiconductor component according to the present invention, BGA semiconductor components having pins arranged in five rows from the outside can be mounted. Moreover, since it is a one-stage build-up board, the manufacturing cost of the printed board is low.

以下この発明を実施するための最良の形態を実施例に即して説明する。   The best mode for carrying out the present invention will be described below with reference to examples.

図1はこの発明の実施例であるBGA半導体部品実装用プリント基板を示す部分平面図、図2は同BGA半導体部品実装用プリント基板を示す部分断面図である。なお、図2の断面図の断面は階段状であり、図2は各部材の高さ方向位置を示すのみで、平面方向位置は示していない。   FIG. 1 is a partial plan view showing a printed circuit board for mounting a BGA semiconductor component according to an embodiment of the present invention, and FIG. 2 is a partial sectional view showing the printed circuit board for mounting the BGA semiconductor component. The cross section of the cross-sectional view of FIG. 2 is stepped, and FIG. 2 only shows the height direction position of each member, and does not show the planar direction position.

図1に示すBGA接続用パッド1a、1a…は、内側正方形と外側正方形とで囲まれたロ字型領域に外側から内側に向け5列に形成された各格子点に設けられている。すなわち、図1に示すプリント基板のBGA接続用パッド1aの直径は275μm、間隙は225μm、ピッチは500μmである。   The BGA connection pads 1a, 1a,... Shown in FIG. 1 are provided at grid points formed in five rows from the outside to the inside in a square-shaped region surrounded by the inner square and the outer square. That is, the diameter of the BGA connection pad 1a of the printed circuit board shown in FIG.

このプリント基板の製造方法および構造を図2を参照して説明する。図2に示す絶縁層7の表面(上面)および裏面(下面)に導体膜を施し、感光・エッチングにより配線パターン3および配線パターン4が形成される。さらに、その両面に感光性樹脂を積層して硬化することにより絶縁層8および絶縁層10となる。   The manufacturing method and structure of this printed circuit board will be described with reference to FIG. A conductor film is applied to the front surface (upper surface) and back surface (lower surface) of the insulating layer 7 shown in FIG. 2, and the wiring pattern 3 and the wiring pattern 4 are formed by photosensitizing and etching. Furthermore, the insulating layer 8 and the insulating layer 10 are obtained by laminating and curing a photosensitive resin on both surfaces thereof.

この絶縁層7、8および10と配線パターン3および4はコア層12を形成しており、その表面および裏面に配線パターン2および配線パターン5、絶縁層9および絶縁層11、BGA接続用パッド1a、ビルドバイアホール13および配線パターン1およびビルドバイアホール14おび配線パターン6を順次積層形成することにより、1段ビルドのバイアホールにより接続された夫々2層の配線パターンが表面側および裏面側に得られる。   The insulating layers 7, 8 and 10 and the wiring patterns 3 and 4 form a core layer 12. The wiring pattern 2 and the wiring pattern 5, the insulating layer 9 and the insulating layer 11, and the BGA connection pad 1a are formed on the front and back surfaces thereof. Then, the build via hole 13, the wiring pattern 1, the build via hole 14 and the wiring pattern 6 are sequentially laminated to obtain two layers of wiring patterns connected to each other by the one-step build via hole on the front side and the back side. It is done.

すなわち、絶縁層8および10の上に導体膜を施し、感光・エッチングにより配線パターン2および配線パターン5が形成される。さらに、この絶縁層8および10の上に感光性樹脂を積層してビルドバイアホール13、14を形成する位置に感光・エッチングにより孔を形成する。   That is, a conductor film is applied on the insulating layers 8 and 10, and the wiring pattern 2 and the wiring pattern 5 are formed by exposure and etching. Further, a photosensitive resin is laminated on the insulating layers 8 and 10 to form holes at the positions where the build via holes 13 and 14 are formed by photosensitizing and etching.

この感光性樹脂は硬化することにより絶縁層9および11となる。この絶縁層9および11の上に導体膜を施し、感光・エッチングにより配線パターン1、BGA接続用パッド1a、ビルドバイアホール13および配線パターン6、ビルドバイアホール14が形成される。   This photosensitive resin becomes insulating layers 9 and 11 by curing. A conductor film is applied on the insulating layers 9 and 11, and the wiring pattern 1, the BGA connection pad 1a, the build via hole 13, the wiring pattern 6, and the build via hole 14 are formed by photosensitizing and etching.

このように積層された基板にドリルにより孔が開けられ全層貫通ホール(スルーホール)18が形成される。上記したプリント基板はビルドバイアホール(単層貫通バイアホール)が表裏各1段に形成されているので、1段ビルドアップ基板と呼ばれている。   Holes are drilled in the thus-laminated substrates by drills, and all layer through holes (through holes) 18 are formed. The above-mentioned printed circuit board is called a one-stage build-up board because a build via hole (single layer through-hole) is formed in one stage on each side.

この1段ビルドアップ基板を上記した外側から5列に配列されたピンを有するBGA半導体部品を実装する場合、BGA接続用パッド1a、1a…にBGA半導体部品の端子が半田着けされる。そのBGA接続用パッド1a、1a…が外側に接続される状態を図1により説明する。   When the BGA semiconductor component having the pins arranged in five rows from the outside is mounted on the one-stage buildup substrate, the terminals of the BGA semiconductor component are soldered to the BGA connection pads 1a, 1a,. A state where the BGA connection pads 1a, 1a,... Are connected to the outside will be described with reference to FIG.

外側2列のBGA接続用パッド1aとしてA列おびB列を示しているが、このA列おびB列のBGA接続用パッド1aは表面の黒線で示す配線パターン1により外側に接続される。この配線パターン1の幅は75μm、BGA接続用パッド1aの直径は275μm、配線パターン1とBGA接続用パッド1aとの最小間隙は75μmとなる。   The A and B rows are shown as the outer two rows of BGA connection pads 1a. The B and B rows of BGA connection pads 1a are connected to the outside by a wiring pattern 1 indicated by a black line on the surface. The width of the wiring pattern 1 is 75 μm, the diameter of the BGA connection pad 1a is 275 μm, and the minimum gap between the wiring pattern 1 and the BGA connection pad 1a is 75 μm.

外側から3列目および4列目のBGA接続用パッド1aとしてC列おびD列を示しているが、このC列おびD列のBGA接続用パッド1aは配線パターン1、ビルドバイアホール13を介して配線パターン2(内層導体パターン)に接続される。この配線パターン2の幅は75μm、ピッチは250μmとなる。   The C row and the D row are shown as the BGA connection pads 1a in the third row and the fourth row from the outside, and the BGA connection pads 1a in the C row and the D row are connected via the wiring pattern 1 and the build via hole 13. Are connected to the wiring pattern 2 (inner layer conductor pattern). The wiring pattern 2 has a width of 75 μm and a pitch of 250 μm.

外側から5列目のBGA接続用パッド1a(E列)は配線パターン1および全層貫通ホール18を介して裏面の配線パターン6により外側に接続される。外側から5列目の端子はGNDおよびNCであり、共通の配線パターンで接続することができる。このように1段のビルドアップ基板が用いられるので製造コストが安くなる。   The BGA connection pads 1a (E column) in the fifth column from the outside are connected to the outside by the wiring pattern 6 on the back surface through the wiring pattern 1 and the all-layer through hole 18. Terminals in the fifth column from the outside are GND and NC, and can be connected by a common wiring pattern. In this way, since a one-stage build-up substrate is used, the manufacturing cost is reduced.

上記実施例のBGA半導体部品実装用プリント基板に本発明のBGA半導体部品が実装される。すなわち、外側から5列にピンが配列されており、外側から5列目のピンはGND端子およびNC端子のみとなっているBGA半導体部品が実装される。   The BGA semiconductor component of the present invention is mounted on the printed circuit board for mounting the BGA semiconductor component of the above embodiment. That is, BGA semiconductor components in which pins are arranged in five rows from the outside and pins in the fifth row from the outside are only the GND terminal and the NC terminal are mounted.

実施例は以上のように構成されているが発明はこれに限られず、例えば、外側から5列にピンが配列されており、外側から5列目のピンはGND端子、+電源端子およびNC端子のみとなっているBGA半導体部品を、外側から5列目のBGA接続用パッドがGND端子、+電源端子およびNC端子のみ用のBGA接続用パッドとなっており、NC端子、GND端子および電源+端子として2本の配線パターンにより外側に接続したBGA半導体部品実装用プリント基板に実装してもよい。   The embodiment is configured as described above, but the invention is not limited to this. For example, pins are arranged in five rows from the outside, and the pins in the fifth row from the outside are the GND terminal, the + power supply terminal and the NC terminal. The BGA connection pads in the fifth row from the outside are the BGA connection pads only for the GND terminal, + power supply terminal and NC terminal, and the NC terminal, GND terminal and power supply + You may mount in the printed circuit board for BGA semiconductor component mounting connected to the outer side by two wiring patterns as a terminal.

この発明の実施例であるBGA半導体部品実装用プリント基板を示す部分平面図である。It is a fragmentary top view which shows the printed circuit board for BGA semiconductor component mounting which is an Example of this invention. 同BGA半導体部品実装用プリント基板を階段状断面で示す部分断面図である。It is a fragmentary sectional view which shows the printed circuit board for same BGA semiconductor component mounting in a step-like cross section. BGA半導体部品用BGA接続用パッドの例を示す平面図である。It is a top view which shows the example of the BGA connection pad for BGA semiconductor components. 従来のBGA半導体部品実装用プリント基板を階段状断面で示す部分断面図である。It is a fragmentary sectional view which shows the conventional printed circuit board for BGA semiconductor component mounting in a step-like cross section.

符号の説明Explanation of symbols

1 配線パターン、1a BGA接続用パッド
2、3、4、5、6 配線パターン
7、8、9、10、11 絶縁層
12 コア層
13、14、15、16 ビルドバイアホール(VIA)
18 全層貫通ホール(スルーホール)
DESCRIPTION OF SYMBOLS 1 Wiring pattern, 1a BGA connection pad 2, 3, 4, 5, 6 Wiring pattern 7, 8, 9, 10, 11 Insulating layer 12 Core layer 13, 14, 15, 16 Build via hole (VIA)
18 All-layer through-holes (through-holes)

Claims (3)

底面の内側正方形と外側正方形とで囲まれたロ字型領域の表面に前記外側正方形の夫々の辺に近接する第1列から内側に向けて第5列まで5列に形成された各格子点に夫々BGA接続端子を形成したBGA半導体部品において、前記外側正方形の夫々の辺に近接する外側から内側に向かって第5列目の前記各格子点のBGA接続端子にはGND端子、電源端子またはNC端子のいずれかが配置されることを特徴とするBGA半導体部品。 Lattice points formed in five rows from the first row to the inside in the fifth row in the vicinity of each side of the outer square on the surface of the square-shaped region surrounded by the inner square and the outer square on the bottom surface In the BGA semiconductor component in which the BGA connection terminals are respectively formed, the BGA connection terminals at the respective lattice points in the fifth column from the outer side close to the respective sides of the outer square to the inner side include a GND terminal, a power supply terminal, One of NC terminals is arranged, BGA semiconductor component characterized by the above-mentioned. 内側正方形と外側正方形とで囲まれたロ字型領域の表面に前記外側正方形の夫々の辺に近接する第1列から内側に向けて第5列まで5列に形成された各格子点に夫々BGA接続用パッドを形成したBGA半導体部品実装用プリント基板において、ベース基板の表面側に内層導体パターン、表面側絶縁層、単層貫通バイアホールとBGA接続用パッドと表層導体パターンとが順次積層されており、さらに、前記内側正方形の内部に全層貫通バイアホールが形成されており、第1列および第2列のBGA接続用パッドは表層導体パターンを介して前記ロ字型領域外に接続され、第3列および第4列のBGA接続用パッドは表層導体パターン、単層貫通バイアホールおよび内層導体パターンを介して前記ロ字型領域外に接続され、第5列のBGA接続用パッドは表層導体パターン、全層貫通バイアホールおよび前記内層導体パターンより下層の内層導体パターンまたは裏層導体パターンを介して前記ロ字型領域外に接続されていることを特徴とするBGA半導体部品実装用プリント基板。 Each lattice point formed in five rows from the first row in the vicinity of each side of the outer square to the fifth row on the surface of the square-shaped region surrounded by the inner square and the outer square. In a printed circuit board for mounting BGA semiconductor components, on which a BGA connection pad is formed, an inner layer conductor pattern, a surface side insulating layer, a single layer through via hole, a BGA connection pad, and a surface layer conductor pattern are sequentially laminated on the surface side of the base substrate. Furthermore, through-holes are formed in all layers inside the inner square, and the BGA connection pads in the first row and the second row are connected to the outside of the square-shaped region through a surface layer conductor pattern. The BGA connection pads in the third row and the fourth row are connected to the outside of the square-shaped region via the surface layer conductor pattern, the single layer through via hole, and the inner layer conductor pattern, and the BGA contact in the fifth row. The BGA semiconductor component is characterized in that the pad is connected to the outside of the square-shaped region via a surface layer conductor pattern, an all-layer through via hole, and an inner layer conductor pattern or a back layer conductor pattern below the inner layer conductor pattern. Printed circuit board for mounting. 前記第5列のBGA接続用パッドにはBGA半導体部品のGND端子、電源端子またはNC端子のいずれかが接続される請求項2のBGA半導体部品実装用プリント基板。 The printed circuit board for mounting a BGA semiconductor component according to claim 2, wherein a GND terminal, a power supply terminal, or an NC terminal of the BGA semiconductor component is connected to the BGA connection pad in the fifth row.
JP2007074027A 2007-03-22 2007-03-22 Bga semiconductor component and printed circuit board for mounting the same Pending JP2008235627A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012031517A1 (en) * 2010-09-06 2012-03-15 创扬通信技术(深圳)有限公司 Design method of multilayer printed circuit board and multilayer printed circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10303562A (en) * 1997-04-30 1998-11-13 Toshiba Corp Printed wiring board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10303562A (en) * 1997-04-30 1998-11-13 Toshiba Corp Printed wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012031517A1 (en) * 2010-09-06 2012-03-15 创扬通信技术(深圳)有限公司 Design method of multilayer printed circuit board and multilayer printed circuit board

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