JP2008227667A - Variable gain amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain amplifier circuit capable of performing a continuous gain changeover without deteriorating frequency characteristics and gain characteristics. <P>SOLUTION: In accordance with a voltage change of a gain control signal gcnt input as a signal controlling the gain, feedback circuits to a gate voltage Vgate of respective first and second cascode transistors 11 and 21 operate, a sum of each current of the first cascode transistor 11 and a first bypass transistor 14 in a tuning amplifier circuit part 2 is stabilized, a drain voltage of the first input transistor 12 is stabilized irrespective of a voltage Vcont of the gain control signal gcnt, and the first cascode transistor 11, the first input transistor 12, and the first bypass transistor 14 perform operation at an operating point in a desired area. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a variable gain amplifier circuit capable of setting a gain, which constitutes a CMOS analog circuit and amplifies a high frequency input signal.

In the high-frequency circuit of the CMOS process, various methods for switching the gain (gain) have been used.
For example, there is an attenuator unit that performs gain switching by attenuating a signal using a passive element such as a resistor or a capacitor (see, for example, Patent Document 1). By arranging a plurality of attenuators made up of analog switches using resistors and transistors as shown in FIG. 13, the amount of attenuation could be controlled by register settings.
In addition, there has been a variable gain control circuit in which a plurality of transistors are arranged in parallel so that respective drain currents can be summed (see, for example, Patent Document 2). In this case, as shown in FIG. 14, the number of transistors to be operated is controlled by switching on / off of the cascode transistor, thereby controlling the current to be added and switching the gain.

Further, as shown in FIG. 15, when the source of the input stage is not common in a differential amplifier circuit including two input transistors, instead of using a fixed resistor as a resistor connected between the sources of the two input transistors. There is an amplifier that uses a variable resistor that can be controlled by a switch or the like (for example, see Patent Document 3). In FIG. 15, the gain is switched by controlling the mutual conductance of the input stage.
As another method, as shown in FIG. 16, a cascode transistor provided between an input transistor and a tuning element is treated as a switch that can be turned on / off, and each transistor constituting the turned off cascode transistor is treated as a switch. There was a method of switching the gain by limiting the current that flows to the tuning element in the current that is voltage-current converted by the input transistor by turning on the transistors that constitute the bypass transistor without passing through the tuning element by the number of turned off. .
Japanese Patent Laid-Open No. 8-288791 JP 2000-278061 A JP 2000-286653 A

  In the gain switching of the high-frequency amplifier circuit, the above-mentioned method of dividing the resistance by a passive element such as a resistor or a capacitor and switching it by a switch has a relatively simple circuit configuration, and the gain is basically a ratio of the resistance. Therefore, it is easy to control and the number of gain switching stages can be increased. However, in such a method, the number of resistors and transistors is large, and it is easy to be affected by the parasitic capacitances of the resistors and transistors. If the number of gain switching stages increases, the characteristics of the low-pass filter depend on the resistors and the parasitic capacitances. There was a drawback that the effect was noticeable. In the high frequency band, particularly a frequency of several GHz, there is a problem that a desired signal is attenuated because the cutoff frequency of the low-pass filter is not sufficiently high with respect to the pass frequency even with a small parasitic capacitance.

  Further, in the method of switching the gain by changing the number of transistors, the current amount can be controlled by adding the currents of the respective transistors to the number or size ratio of the transistors. However, it is difficult to provide many switches because of the structure, the total area of the drain of the transistor and the gate length with which the drain is in contact are increased, and it is easily affected by the parasitic capacitance of the transistor. there were. Further, in the differential tuned amplifier circuit, the gain switching method for switching the resistance connected between the sources of the input transistors uses an analog switch for switching the resistance. A capacitance is formed. For this reason, the resistor and the parasitic capacitance act as a low-pass filter, causing a problem that the frequency characteristic is deteriorated and the gain characteristic is deteriorated.

Also, in the method of switching the gain by limiting the current flowing through the tuning element using the cascode transistor as an on / off switch, the number of fingers of the cascode transistor needs to be reduced as the number of gain switching stages increases, resulting in a complicated layout. As a result, the source / drain area is increased and the frequency characteristics and gain characteristics are deteriorated.
In addition, since each of the methods as described above cannot perform continuous gain switching, it cannot be used as a gain amplifier for analog AGC operation.

  The present invention has been made to solve such problems, and it is an object of the present invention to obtain a variable gain amplifier circuit capable of performing continuous gain switching without causing deterioration of frequency characteristics and gain characteristics. Objective.

A variable gain amplifier circuit according to the present invention is a variable gain amplifier circuit that varies a gain according to a gain control signal input from the outside, amplifies an input high frequency input signal, and outputs the amplified high frequency input signal.
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor, a first input transistor in which the high-frequency input signal is input to a control electrode, and a predetermined bias to the control electrode A first bias current control transistor that forms a constant current source to which a voltage is input, and a first circuit in which the gain control signal is input to a control electrode connected in parallel to a series circuit of the tuning element and the first cascode transistor; A tuned amplifier circuit section composed of one bypass transistor;
A second cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage, a second input transistor having a predetermined voltage input to the control electrode, and a second bias forming a diode A current control transistor, and a second bypass transistor connected in parallel to the second cascode transistor and having the gain control signal input to a control electrode, and is supplied by the first bias current control transistor A control circuit unit that generates a reference current proportional to a bias current, and controls the operation of each of the first and second cascode transistors so that the current flowing through the second bias current control transistor becomes the reference current; ,
Is provided.

Specifically, the control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second cascode transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. An operational amplifier,
I was prepared to.

The variable gain amplifier circuit according to the present invention is a variable gain amplifier circuit that varies the gain according to a gain control signal input from the outside and amplifies and outputs the input high frequency input signal.
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor having the gain control signal input to the control electrode, and a first cascode transistor having the high frequency input signal input to the control electrode A first bias current control transistor that forms a constant current source in which a predetermined bias voltage is input to one input transistor and a control electrode, and a series circuit of the tuning element and the first cascode transistor are connected in parallel A tuned amplifier circuit portion comprising a first bypass transistor;
A second cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage and having the gain control signal input to the control electrode and a second voltage having the predetermined voltage input to the control electrode And a second bias current control transistor forming a diode, and a second bypass transistor connected in parallel to the second cascode transistor, and supplied by the first bias current control transistor A control circuit that generates a reference current proportional to the bias current to be applied and controls the operation of each of the first and second bypass transistors so that the current flowing through the second bias current control transistor becomes the reference current. And
Is provided.

Specifically, the control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second bypass transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. An operational amplifier,
I was prepared to.

  The size ratio of the first cascode transistor, the first input transistor, and the first bypass transistor is the same as the size ratio of the second cascode transistor, the second input transistor, and the second bypass transistor. The size ratio between the first cascode transistor and the first bypass transistor is the same as the size ratio between the second cascode transistor and the second bypass transistor.

The variable gain amplifier circuit according to the present invention is a variable gain amplifier circuit that varies the gain according to a gain control signal input from the outside and amplifies and outputs the input high frequency input signal.
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor, a first input transistor in which the high-frequency input signal is input to a control electrode, and a predetermined bias to the control electrode A first bias current control transistor that forms a constant current source to which a voltage is input, and a first circuit in which the gain control signal is input to a control electrode connected in parallel to a series circuit of the tuning element and the first cascode transistor; A tuned amplifier circuit section composed of one bypass transistor;
A second cascode transistor connected in series between the positive side power supply voltage and the negative side power supply voltage; a second input transistor; a second bias current control transistor forming a diode; and A second bypass transistor connected in parallel to the cascode transistor and having the gain control signal input to a control electrode, and generates a reference current proportional to a bias current supplied by the first bias current control transistor; A control circuit unit for controlling the operation of each of the first and second cascode transistors so that a current flowing through the second bias current control transistor becomes the reference current;
A third cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage and having the positive power supply voltage input to the control electrode, and a common voltage of the high frequency input signal to the control electrode. A reference circuit unit including a third bias current control transistor which forms a constant current source in which the predetermined bias voltage is input to the input third input transistor and the control electrode;
With
The control circuit unit is configured so that a voltage at a connection portion between the second cascode transistor and the second input transistor becomes a voltage at a connection portion between the third cascode transistor and the third input transistor. The operation of the second input transistor is controlled.

Specifically, the control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second cascode transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. A first operational amplifier,
The second input transistor so that the voltage at the connection between the second cascode transistor and the second input transistor becomes the voltage at the connection between the third cascode transistor and the third input transistor. A second operational amplifier for controlling the operation of
I was prepared to.

The variable gain amplifier circuit according to the present invention is a variable gain amplifier circuit that varies the gain according to a gain control signal input from the outside and amplifies and outputs the input high frequency input signal.
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor having the gain control signal input to the control electrode, and a first cascode transistor having the high frequency input signal input to the control electrode A first bias current control transistor that forms a constant current source in which a predetermined bias voltage is input to one input transistor and a control electrode, and a series circuit of the tuning element and the first cascode transistor are connected in parallel A tuned amplifier circuit portion comprising a first bypass transistor;
A second cascode transistor, a second input transistor, and a diode, which are connected in series between the positive power supply voltage and the negative power supply voltage and have the gain control signal input to a control electrode, are formed. A bias current control transistor and a second bypass transistor connected in parallel to the second cascode transistor, and a reference current proportional to the bias current supplied by the first bias current control transistor. A control circuit unit that controls the operation of each of the first and second bypass transistors so that a current that flows through the second bias current control transistor is the reference current.
A third cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage and having the positive power supply voltage input to the control electrode, and a common voltage of the high frequency input signal to the control electrode. A reference circuit unit including a third bias current control transistor which forms a constant current source in which the predetermined bias voltage is input to the input third input transistor and the control electrode;
With
The control circuit unit is configured so that a voltage at a connection portion between the second cascode transistor and the second input transistor becomes a voltage at a connection portion between the third cascode transistor and the third input transistor. The operation of the second input transistor is controlled.

Specifically, the control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second bypass transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. A first operational amplifier,
The second input transistor so that the voltage at the connection between the second cascode transistor and the second input transistor becomes the voltage at the connection between the third cascode transistor and the third input transistor. A second operational amplifier for controlling the operation of
I was prepared to.

  The size ratio of the first cascode transistor, the first input transistor, and the first bypass transistor is different from the size ratio of the second cascode transistor, the second input transistor, and the second bypass transistor. 3 cascode transistors, the third input transistor, and the third bypass transistor have the same size ratio, and the first cascode transistor and the first bypass transistor have a size ratio of the second cascode transistor and the third bypass transistor. It was made to be the same as the size ratio of 2 bypass transistors.

  According to the variable gain amplifier circuit of the present invention, the operating point of each transistor of the tuning amplifier circuit unit is reproduced in a DC manner in the control circuit unit, and then the current flowing through the first cascode transistor and the first bypass transistor are changed. By applying feedback to the control electrode voltage of the first cascode transistor so that the sum of the flowing currents is constant, the control electrode of the first cascode transistor is controlled against the change in the control electrode voltage of the first bypass transistor. The voltage can be controlled, and the gain can be continuously switched. In the tuning amplifier circuit portion, the first cascode transistor and the first bypass transistor are arranged in parallel, but both can be laid out as one transistor having a large number of fingers, and the circuit configuration is simple. Thus, the influence of parasitic capacitance is small, and the frequency characteristics and gain characteristics can be improved.

  Further, the voltage at the connection portion between the first cascode transistor and the first input transistor in the tuned amplifier circuit portion is reproduced in the reference circuit portion, and the reproduced voltage and the second cascode transistor in the control circuit portion and the second The voltage at the connection portion between the second cascode transistor and the second input transistor is tuned by adjusting the voltage at the connection portion with the input transistor and applying feedback to the control electrode of the second input transistor. The operating point can be the same. Accordingly, the voltage at the connection portion between the cascode transistor and the bypass transistor can be made to coincide between the tuning amplifier circuit portion, the control circuit portion, and the reference circuit portion, and flows to the first cascode transistor of the tuning amplifier circuit portion. The sum of the current and the current flowing through the first bypass transistor can be made constant accurately, and the operating point of each of the first cascode transistor, the first bypass transistor, and the first input transistor can be set to a desired value. Therefore, characteristics with respect to distortion such as linearity can be improved.

  In the tuning control circuit unit and the control circuit unit, or in the tuning control circuit unit, the control circuit unit and the reference circuit unit, it is important to reproduce the operating point of the transistor, and the absolute value of the current value is not important. By reducing the size of each transistor while maintaining the same size ratio, the absolute value of the bias current can be reduced, and the current consumption can be reduced.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a variable gain amplifier circuit according to the first embodiment of the present invention.
In FIG. 1, a variable gain amplifier circuit 1 varies the gain according to a control signal input from the outside, amplifies an input high frequency input signal Sin, and outputs the amplified signal as an output signal Sout. The variable gain amplifier circuit 1 includes a tuning amplifier circuit unit 2 and a gate voltage generation circuit unit 3. The tuning amplifier circuit unit 2 includes a first cascode transistor 11, a first input transistor 12, and a first bias. The current control transistor 13, the first bypass transistor 14, the inductor 15, and the capacitor 16 are included, and the inductor 15 and the capacitor 16 constitute a tuning element.

  The gate voltage generation circuit unit 3 includes a second cascode transistor 21, a second input transistor 22, a second bias current control transistor 23, a second bypass transistor 24, an operational amplifier 25, an N-channel transistor 26, 27 and P-channel type transistors 28 and 29. First and second cascode transistors 11 and 21, first and second input transistors 12 and 22, first and second bias current control transistors 13 and 23, and first and second bypasses The transistors 14 and 24 are N-channel transistors, for example, NMOS transistors.

  The N-channel transistors 26 and 27 are, for example, NMOS transistors, the P-channel transistors 28 and 29 are, for example, PMOS transistors, the N-channel transistors are NMOS transistors, and the P-channel transistors are PMOS transistors. A case will be described as an example. The gate voltage generation circuit unit 3 forms a control circuit unit, the NMOS transistor 26 and the PMOS transistors 28 and 29 form a reference current generation circuit, and the NMOS transistor 27 forms a first transistor.

  An inductor 15 and a capacitor 16 are connected in parallel, and one end of the parallel circuit is connected to a DC power supply voltage VCC (hereinafter referred to as power supply voltage VCC) forming a positive power supply voltage, and the other end of the parallel circuit is negatively connected. The first cascode transistor 11, the first input transistor 12, and the first bias current control transistor 13 are connected in series with the ground voltage that forms the side power supply voltage. A first bypass transistor 14 is connected between the power supply voltage VCC and the source of the first cascode transistor 11. The gate voltage Vgate from the gate voltage generation circuit 3 is applied to the gate of the first cascode transistor 11, the high-frequency input signal Sin is applied to the gate of the first input transistor 12, and the gate of the first bias current control transistor 13 is applied. A predetermined bias voltage Vbias is input, and a gain control signal gcnt for controlling the gain of the variable gain amplifier circuit 1 is input from the outside to the gate of the first bypass transistor 14. An output signal Sout is output from a connection portion between the parallel circuit of the inductor 15 and the capacitor 16 and the first cascode transistor 11.

  The PMOS transistors 28 and 29 form a current mirror circuit. In the PMOS transistors 28 and 29, each source is connected to the power supply voltage VCC, and each gate is connected to the drain of the PMOS transistor 28. An NMOS transistor 26 is connected between the drain of the PMOS transistor 28 and the ground voltage, and a bias voltage Vbias is input to the gate of the NMOS transistor 26. An NMOS transistor 27 is connected between the drain of the PMOS transistor 29 and the ground voltage. The gate of the NMOS transistor 27 is connected to the drain of the NMOS transistor 27 to form a diode. Connected to the inverting input.

  A second cascode transistor 21, a second input transistor 22, and a second bias current control transistor 23 are connected in series between the power supply voltage VCC and the ground voltage. A second bypass transistor 24 is connected in parallel. In the second bias current control transistor 23, the gate is connected to the drain to form a diode, and the connection is connected to the inverting input terminal of the operational amplifier 25. The gate of the second cascode transistor 21 is connected to the output terminal of the operational amplifier 25, and the gate voltage Vgate is output from the output terminal of the operational amplifier 25 that forms the output terminal of the gate voltage generation circuit 3. A predetermined DC voltage Vdc is input to the gate of the second input transistor 22, and a gain control signal gcnt is input to the gate of the second bypass transistor 24.

In such a configuration, the bias voltage Vbias is an input voltage for controlling the bias current supplied from the first bias current control transistor 13, and is normally interfaced with the current from the bias current source, and the current mirror circuit is Generated using. The DC component of the high-frequency input signal Sin is set to a voltage at which the first input transistor 12 and the first bias current control transistor 13 can operate in the saturation region. By connecting the first cascode transistor 11 to the drain of the first input transistor 12, the impedance viewed from the output terminal that outputs the output signal Sout is increased, and the linearity characteristic of the tuned amplifier circuit unit 2 is improved. A tuning element including an inductor 15 and a capacitor 16 is provided between the drain of the first cascode transistor 11 and the power supply voltage VCC. The tuning element is voltage-current converted by the first input transistor 12. The current component is converted from current to voltage, and at the same time, it passes through the resonance frequency f represented by f = 1 / 2π (LC) ^1/2 by the inductance L of the inductor 15 and the capacitance C of the capacitor 16. Has frequency characteristics. The output signal Sout is a signal having the power supply voltage VCC as a common voltage.

  On the other hand, the drain of the first bypass transistor 14 is directly connected to the power supply voltage VCC without going through the tuning element. Since there is no element serving as a load, the drain does not contribute to the gain and flows to the first cascode transistor 11. Only current contributes to gain. The gate voltage of the first cascode transistor 11 is controlled so that the sum of the currents flowing through the first cascode transistor 11 and the first bypass transistor 14 is constant. Note that the transistor sizes of the first cascode transistor 11 and the first bypass transistor 14 may be the same.

  In the NMOS transistor 26, a current proportional to the bias current supplied from the first bias current control transistor 13 flows, and the current flows back to the NMOS transistor 27 which is turned back by the current mirror circuit of the PMOS transistors 28 and 29 to form a diode. . The operational amplifier 25 monitors the current flowing through the NMOS transistor 27 by monitoring the voltage of the anode of the diode formed by the NMOS transistor 27, that is, the current flowing through the first bias current control transistor 13. Further, the operational amplifier 25 monitors the current flowing through the second bias current control transistor 23 by monitoring the voltage of the anode of the diode formed by the second bias current control transistor 23. The operational amplifier 25 includes a first cascode transistor 11 and a second cascode transistor 11 so that the voltage of the anode of the diode formed by the NMOS transistor 27 and the voltage of the anode of the diode formed by the second bias current control transistor 23 are the same. The gate voltage Vgate 21 is controlled to perform feedback.

  For this reason, the feedback circuit operates according to the voltage Vcont of the gain control signal gcnt, and the gate voltage Vgate is controlled so that the bias current flowing through the tuning amplifier circuit unit 2 becomes constant. When the bias current becomes constant, the DC voltage of the source and drain of the first input transistor 12 of the tuning amplifier circuit section 2 becomes constant, and the operating point of the first input transistor 12 is stabilized regardless of the setting of the voltage Vcont. Can be made. The operating points of the transistors 11 to 13 may be set to optimum levels in order to improve linearity characteristics and gain characteristics. It is desirable that the size ratio of the transistors 21 to 23 of the gate voltage generation circuit unit 3 is the same as the size ratio of the transistors 11 to 13 of the tuning amplifier circuit unit 2.

  As described above, the variable gain amplifier circuit according to the first embodiment includes the first and second cascode transistors 11 and 2 according to the change in the voltage Vcont of the gain control signal gcnt input as a signal for controlling the gain. The feedback circuit acts on the gate voltage Vgate of 21, and the sum of the currents of the first cascode transistor 11 and the first bypass transistor 14 of the tuned amplifier circuit section 2 can be made constant, and the first input transistor 12 Can be made constant regardless of the voltage Vcont of the gain control signal gcnt, so that the first cascode transistor 11, the first input transistor 12 and the first bypass transistor 14 are at the operating point in a desired region. Can be performed. For this reason, high linearity characteristics and stable gain characteristics can be obtained. Further, since the gain characteristic of the gain control signal gcnt with respect to the voltage Vcont continuously exhibits a monotonously decreasing characteristic, it can be used as a circuit for performing an analog AGC operation in combination with a power detector or the like.

  In FIG. 1, the gain control signal gcnt is input to the gates of the first and second cascode transistors 11 and 21, respectively, and the gate voltage Vgate is applied to the gates of the first and second bypass transistors 14 and 24. May be input respectively. However, it is desirable that the cascode transistor and the bypass transistor have the same transistor size, and when the transistor size is the same, the circuit is substantially the same as in FIG. In this case, the generation of the gate voltage Vgate signal with respect to the gain control signal gcnt is substantially the same as in FIG. 1, but since the gain control signal gcnt is input to the cascode transistor, the gain characteristic is as shown in FIG. Unlike the above, the gain has a monotonically increasing characteristic as the voltage Vcont increases.

Second embodiment.
In the first embodiment, a predetermined DC voltage Vdc is input to the gate of the second input transistor 22, but a voltage corresponding to the drain voltage of the first input transistor 12 is obtained. The gate voltage of the second input transistor 22 may be controlled, and such a configuration is used as the second embodiment of the present invention.
FIG. 2 is a diagram showing a circuit example of a variable gain amplifier circuit according to the second embodiment of the present invention. 2 that are the same as or similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.

  2 differs from FIG. 1 in that a reference circuit unit 4 for generating a voltage corresponding to the drain voltage of the first input transistor 12 of the tuned amplifier circuit unit 2 is provided and generated by the reference circuit unit 4. An operational amplifier 34 for controlling the gate voltage of the second input transistor 22 so as to be a voltage corresponding to the drain voltage of the first input transistor 12 is added to the gate voltage generation circuit unit 3 of FIG. It is in having added. Accordingly, the gate voltage generation circuit unit 3 in FIG. 1 is replaced with the gate voltage generation circuit unit 3a, and the variable gain amplification circuit 1 in FIG. 1 is replaced with the variable gain amplification circuit 1a. In FIG. 2, a high-pass filter including a capacitor 17 and a resistor 18 is added to the tuning amplifier circuit unit 2 of FIG. 1, but a high-pass filter including a capacitor 17 and a resistor 18 is added to the tuning amplifier circuit unit 2 of FIG. The tuning amplifier circuit portions in FIGS. 1 and 2 are substantially the same, and are denoted by the same reference numerals.

  In FIG. 2, the variable gain amplifier circuit 1a amplifies the input high frequency input signal Sin and outputs it as an output signal Sout. The variable gain amplifier circuit 1a includes a tuning amplifier circuit unit 2, a gate voltage generation circuit unit 3a, and a reference circuit unit 4. The gate voltage generation circuit unit 3a includes a second cascode transistor 21, a second Input transistor 22, second bias current control transistor 23, second bypass transistor 24, operational amplifiers 25 and 34, NMOS transistors 26 and 27, and PMOS transistors 28 and 29. The reference circuit unit 4 includes an N-channel transistor, for example, an NMOS transistor, which includes a third cascode transistor 31, a third input transistor 32, and a third bias current control transistor 33.

The gate voltage generation circuit unit 3a serves as a control circuit unit, the operational amplifier 25 serves as a first operational amplifier, and the operational amplifier 34 serves as a second operational amplifier.
In the tuned amplifier circuit 2, a capacitor 17 is connected between the input terminal to which the high frequency input signal Sin is input and the gate of the first input transistor 12, and the gate of the first input transistor 12 and the high frequency input signal Sin. A resistor 18 is connected to the common voltage Vcom. Therefore, a signal obtained by removing the DC component from the high frequency input signal Sin is input to the gate of the first input transistor 12.

In the reference circuit section 4, a third cascode transistor 31, a third input transistor 32, and a third bias current control transistor 33 are connected in series between the power supply voltage VCC and the ground voltage. The power supply voltage VCC is applied to the gate of the third cascode transistor 31, the common voltage Vcom of the high-frequency input signal Sin is applied to the gate of the third input transistor 32, and the bias voltage is applied to the gate of the third bias current control transistor 33. Vbias is input respectively. The drain voltage of the third input transistor is input to the inverting input terminal of the operational amplifier 34 of the gate voltage generation circuit unit 3a.
In the gate voltage generation circuit unit 3 a, the drain voltage of the second input transistor 22 is input to the non-inverting input terminal of the operational amplifier 34, and the output terminal of the operational amplifier 34 is connected to the gate of the second input transistor 22. ing.

  In such a configuration, the third cascode transistor 31, the third input transistor 32, and the third bias current control transistor 33 in the reference circuit unit 4 are the same as the first cascode transistor 11 in the tuned amplifier circuit unit 2, The transistor size ratio is the same as that of the first input transistor 12 and the first bias current control transistor 13. Therefore, the drain voltage of the first input transistor 12 in a state where the gate voltage Vgate is controlled by the gain control signal gcnt can be obtained from the drain voltage of the third input transistor 32.

  The operational amplifier 34 controls the operation of the second input transistor 22 so that the drain voltage of the second input transistor 22 is equal to the drain voltage of the third input transistor 32 of the reference circuit unit 4. For this reason, the operating point of the second input transistor 22 can be made the same as the operating point of the first input transistor 12 of the tuned amplifier circuit unit 2, and the first cascode transistor 11, Each operating point of the first input transistor 12 and the first bypass transistor 14 can be controlled to a desired value, and characteristics with respect to distortion such as linearity can be improved.

Here, FIG. 3 is a diagram illustrating an example of a change in the gate voltage Vgate when the voltage Vcont of the gain control signal gcnt is changed, and the gate voltage Vgate decreases in conjunction with the voltage increase of the voltage Vcont. I understand that.
FIG. 4 shows the current icas2 flowing through the second cascode transistor 21, the current ibip2 flowing through the second bypass transistor 24, and the second bias current control transistor with respect to changes in the voltage Vcont and the gate voltage Vgate shown in FIG. FIG. 6 is a diagram showing an example of each change in the bias current isum2 flowing through 23.

  FIG. 5 shows the current icas1 flowing through the first cascode transistor 11, the current ibip1 flowing through the first bypass transistor 14, and the first bias current control with respect to changes in the voltage Vcont and the gate voltage Vgate shown in FIG. FIG. 6 is a diagram showing each change example of the bias current isum1 flowing through the transistor 13 for operation. 4 and 5, it can be seen that the current flowing through the cascode transistor decreases so as to be inversely proportional to the increase in the current flowing through the bypass transistor, and the sum of the two currents is controlled to be substantially constant.

FIG. 6 shows examples of the drain voltages D1, D2, and D3 of the first to third input transistors 12, 22, and 32 with respect to changes in the voltage Vcont and the gate voltage Vgate shown in FIG. FIG.
3 to 6, the gate voltage Vgate is changed by the gain control signal gcnt, the current flowing through the cascode transistor and the bypass transistor is controlled, and the feedback circuit works so as to keep the sum of the currents flowing through the two transistors constant. Thus, it can be seen that the drain voltage of the input transistor, that is, the source voltages of the cascode transistor and the bypass transistor can be made constant.
FIG. 7 is a diagram illustrating an example of the gain characteristic of the variable gain amplifier circuit 1a with respect to the voltage Vcont, and FIG. 8 is a diagram illustrating an example of the frequency characteristic of the variable gain amplifier circuit 1a with respect to the voltage Vcont. FIG. 8 shows that the peak value in the frequency characteristic increases as the voltage Vcont increases.

  As shown in FIG. 9, in FIG. 2, the gain control signal gcnt is input to the gates of the first and second cascode transistors 11 and 21, respectively, and the first and second bypass transistors 14 and 24 are input. The gate voltage Vgate may be input to each of the gates. However, it is desirable that the cascode transistor and the bypass transistor have the same transistor size, and when the transistor size is the same, the circuit is substantially the same as in FIG. In the case of FIG. 9, the generation of the gate voltage Vgate signal with respect to the gain control signal gcnt is substantially the same as in FIG. 3, but the gain control signal gcnt is input to the cascode transistor. Unlike FIG. 7, as shown in FIG. 10, the gain has a monotonically increasing characteristic as the voltage Vcont increases.

  On the other hand, the variable gain amplifier circuit of FIG. 2 may be configured to amplify a pair of differential signals and output them as differential signals. In this case, FIG. 2 is as shown in FIG. 11, the same or similar elements as those in FIG. 2 are denoted by the same reference numerals, and a resistor 41 is inserted between the sources of the first input transistor to adjust the transconductance gm of voltage-current conversion. Since the operation is the same as that shown in FIG. Also in the case of FIG. 11, as shown in FIG. 9, the gain control signal gcnt is input to the gates of the first and second cascode transistors 11 and 21, respectively, and the first and second bypass transistors 14, The gate voltage Vgate may be inputted to each of the 24 gates. In this case, FIG. 11 becomes as shown in FIG. 11 and 12, a pair of differential signals Sip and Sim are input to corresponding differential input terminals, and the differential signals Sip and Sim are amplified to generate a pair of differential signals Sop. , Som are output from the corresponding differential output terminals.

  As described above, the variable gain amplifier circuit according to the second embodiment includes the drain of the third input transistor 32 in the reference circuit unit 4 that is a DC replica of the gate voltage generation circuit unit 3 a and the tuning amplifier circuit unit 2. By comparing the voltages and performing a feedback operation, the drain voltages of the input transistors of the tuned amplification circuit unit 2 and the gate voltage generation circuit unit 3a can be made the same voltage. At the same time, the source voltages of the cascode transistor and the bypass transistor are also the same voltage. Can be. For this reason, the bias current of the tuning amplifier circuit unit 2 and the gate voltage generation circuit unit 3a can be controlled to the same current value (or current ratio with respect to the transistor size), and each transistor of the cascode transistor, the input transistor, and the bypass transistor is desired. The operation in the above region can be performed more stably, and high linearity characteristics and stable gain characteristics can be obtained.

It is the figure which showed the circuit example of the variable gain amplifier circuit in the 1st Embodiment of this invention. It is the figure which showed the circuit example of the variable gain amplifier circuit in the 2nd Embodiment of this invention. It is the figure which showed the example of the change of the gate voltage Vgate when the voltage Vcont of the gain control signal gcnt is changed. FIG. 4 is a diagram illustrating each change example of currents icas2, ibip2, and isum2 with respect to changes in the voltage Vcont and the gate voltage Vgate shown in FIG. FIG. 4 is a diagram illustrating each change example of currents icas1, ibip1, and isum1 with respect to changes in voltage Vcont and gate voltage Vgate shown in FIG. 3; FIG. 4 is a diagram illustrating examples of drain voltages D1, D2, and D3 of each input transistor with respect to changes in the voltage Vcont and the gate voltage Vgate illustrated in FIG. FIG. 3 is a diagram illustrating an example of gain characteristics of the variable gain amplifier circuit 1a of FIG. 2 with respect to a voltage Vcont. It is the figure which showed the frequency characteristic example of the variable gain amplifier circuit 1a with respect to the voltage Vcont. It is the figure which showed the other circuit example of the variable gain amplifier circuit in the 2nd Embodiment of this invention. It is the figure which showed the gain characteristic example of the variable gain amplifier circuit 1a of FIG. 9 with respect to the voltage Vcont. It is the figure which showed the other circuit example of the variable gain amplifier circuit in the 2nd Embodiment of this invention. It is the figure which showed the other circuit example of the variable gain amplifier circuit in the 2nd Embodiment of this invention. It is the circuit diagram which showed the prior art example of the attenuator unit which performs gain switching. It is the figure which showed the circuit example of the conventional variable gain amplifier circuit. It is the figure which showed the circuit example of the conventional amplifier. It is the figure which showed the circuit example of the conventional variable gain amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Variable gain amplifier circuit 2 Tuning amplifier circuit part 3, 3a Gate voltage generation circuit part 4 Reference circuit part 11 1st cascode transistor 21 2nd cascode transistor 31 3rd cascode transistor 12 1st input transistor 22 1st 2 input transistors 32 3rd input transistor 13 1st bias current control transistor 23 2nd bias current control transistor 33 3rd bias current control transistor 14 1st bypass transistor 24 2nd bypass transistor 15 Inductors 16, 17 Capacitors 18, 41 Resistors 25, 34 Operational amplifiers 26, 27 NMOS transistors 28, 29 PMOS transistors

Claims (10)

In a variable gain amplifier circuit that varies a gain according to a gain control signal input from the outside, amplifies and outputs an input high frequency input signal,
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor, a first input transistor in which the high-frequency input signal is input to a control electrode, and a predetermined bias to the control electrode A first bias current control transistor that forms a constant current source to which a voltage is input, and a first circuit in which the gain control signal is input to a control electrode connected in parallel to a series circuit of the tuning element and the first cascode transistor; A tuned amplifier circuit section composed of one bypass transistor;
A second cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage, a second input transistor having a predetermined voltage input to the control electrode, and a second bias forming a diode A current control transistor, and a second bypass transistor connected in parallel to the second cascode transistor and having the gain control signal input to a control electrode, and is supplied by the first bias current control transistor A control circuit unit that generates a reference current proportional to a bias current, and controls the operation of each of the first and second cascode transistors so that the current flowing through the second bias current control transistor becomes the reference current; ,
A variable gain amplifier circuit comprising: The control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second cascode transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. An operational amplifier,
The variable gain amplifier circuit according to claim 1, further comprising: In a variable gain amplifier circuit that varies a gain according to a gain control signal input from the outside, amplifies and outputs an input high frequency input signal,
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor having the gain control signal input to the control electrode, and a first cascode transistor having the high frequency input signal input to the control electrode A first bias current control transistor that forms a constant current source in which a predetermined bias voltage is input to one input transistor and a control electrode, and a series circuit of the tuning element and the first cascode transistor are connected in parallel A tuned amplifier circuit portion comprising a first bypass transistor;
A second cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage and having the gain control signal input to the control electrode and a second voltage having the predetermined voltage input to the control electrode And a second bias current control transistor forming a diode, and a second bypass transistor connected in parallel to the second cascode transistor, and supplied by the first bias current control transistor A control circuit that generates a reference current proportional to the bias current to be applied and controls the operation of each of the first and second bypass transistors so that the current flowing through the second bias current control transistor becomes the reference current. And
A variable gain amplifier circuit comprising: The control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second bypass transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. An operational amplifier,
The variable gain amplifier circuit according to claim 3, further comprising:   The size ratio of the first cascode transistor, the first input transistor, and the first bypass transistor is the same as the size ratio of the second cascode transistor, the second input transistor, and the second bypass transistor, and 5. The size ratio between the first cascode transistor and the first bypass transistor is the same as the size ratio between the second cascode transistor and the second bypass transistor. Variable gain amplifier circuit. In a variable gain amplifier circuit that varies a gain according to a gain control signal input from the outside, amplifies and outputs an input high frequency input signal,
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor, a first input transistor in which the high-frequency input signal is input to a control electrode, and a predetermined bias to the control electrode A first bias current control transistor that forms a constant current source to which a voltage is input, and a first circuit in which the gain control signal is input to a control electrode connected in parallel to a series circuit of the tuning element and the first cascode transistor; A tuned amplifier circuit section composed of one bypass transistor;
A second cascode transistor connected in series between the positive side power supply voltage and the negative side power supply voltage; a second input transistor; a second bias current control transistor forming a diode; and A second bypass transistor connected in parallel to the cascode transistor and having the gain control signal input to a control electrode, and generates a reference current proportional to a bias current supplied by the first bias current control transistor; A control circuit unit for controlling the operation of each of the first and second cascode transistors so that a current flowing through the second bias current control transistor becomes the reference current;
A third cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage and having the positive power supply voltage input to the control electrode, and a common voltage of the high frequency input signal to the control electrode. A reference circuit unit including a third bias current control transistor which forms a constant current source in which the predetermined bias voltage is input to the input third input transistor and the control electrode;
With
The control circuit unit is configured so that a voltage at a connection portion between the second cascode transistor and the second input transistor becomes a voltage at a connection portion between the third cascode transistor and the third input transistor. A variable gain amplifier circuit that controls an operation of the second input transistor. The control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second cascode transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. A first operational amplifier,
The second input transistor so that the voltage at the connection between the second cascode transistor and the second input transistor becomes the voltage at the connection between the third cascode transistor and the third input transistor. A second operational amplifier for controlling the operation of
The variable gain amplifier circuit according to claim 6, further comprising: In a variable gain amplifier circuit that varies a gain according to a gain control signal input from the outside, amplifies and outputs an input high frequency input signal,
A tuning element connected in series between a positive power supply voltage and a negative power supply voltage, a first cascode transistor having the gain control signal input to the control electrode, and a first cascode transistor having the high frequency input signal input to the control electrode A first bias current control transistor that forms a constant current source in which a predetermined bias voltage is input to one input transistor and a control electrode, and a series circuit of the tuning element and the first cascode transistor are connected in parallel A tuned amplifier circuit portion comprising a first bypass transistor;
A second cascode transistor, a second input transistor, and a diode, which are connected in series between the positive power supply voltage and the negative power supply voltage and have the gain control signal input to a control electrode, are formed. A bias current control transistor and a second bypass transistor connected in parallel to the second cascode transistor, and a reference current proportional to the bias current supplied by the first bias current control transistor. A control circuit unit that controls the operation of each of the first and second bypass transistors so that a current that flows through the second bias current control transistor is the reference current.
A third cascode transistor connected in series between the positive power supply voltage and the negative power supply voltage and having the positive power supply voltage input to the control electrode, and a common voltage of the high frequency input signal to the control electrode. A reference circuit unit including a third bias current control transistor which forms a constant current source in which the predetermined bias voltage is input to the input third input transistor and the control electrode;
With
The control circuit unit is configured so that a voltage at a connection portion between the second cascode transistor and the second input transistor becomes a voltage at a connection portion between the third cascode transistor and the third input transistor. A variable gain amplifier circuit that controls an operation of the second input transistor. The control circuit unit is
A reference current generation circuit for generating a reference current proportional to a bias current supplied by the first bias current control transistor;
A first transistor forming a diode connected between the output terminal of the reference current generation circuit and the negative power supply voltage, and through which the reference current flows;
The operation of each of the first and second bypass transistors is controlled so that the anode voltage of the diode formed by the second bias current control transistor is equal to the anode voltage of the diode formed by the first transistor. A first operational amplifier,
The second input transistor so that the voltage at the connection between the second cascode transistor and the second input transistor becomes the voltage at the connection between the third cascode transistor and the third input transistor. A second operational amplifier for controlling the operation of
9. The variable gain amplifier circuit according to claim 8, further comprising:   The size ratio of the first cascode transistor, the first input transistor, and the first bypass transistor is the same as the size ratio of the second cascode transistor, the second input transistor, and the second bypass transistor. The size ratio of the cascode transistor, the third input transistor, and the third bypass transistor is the same, and the size ratio of the first cascode transistor and the first bypass transistor is the same as that of the second cascode transistor and the second bypass transistor. 10. The variable gain amplifier circuit according to claim 6, wherein the variable gain amplifier circuit has the same size ratio as that of the bypass transistor.

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