JP2008227049A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having an antifuse element that is easy to program, requires less space, and can simplify the manufacturing process.
An antifuse element includes a first terminal portion 22a, a second terminal portion 22b, a fuse main body portion 23 provided between the first terminal portion 22a and the second terminal portion 22b, and It has. It consists of a portion connected to the first terminal portion 22a and a portion connected to the second terminal portion 22b. The fuse body portion 23 is disposed between the portion connected to the first terminal portion 22a, the portion connected to the second terminal portion 22b, and the first terminal portion 22a and the second terminal portion 22b. An antifuse connection portion 24 that substantially insulates the terminal portion. The antifuse 24 can be turned on irreversibly by applying a voltage between the first terminal portion 22a and the second terminal portion 22b.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an electrically programmable antifuse element in a semiconductor device having a silicide film and a method for manufacturing the same.

  The antifuse element is a switch element that is generally provided at a connection portion between conductors and is in an initial state of non-conduction, and can switch the non-conduction portion to an electric conduction state as necessary. .

  FIG. 23 is a cross-sectional view showing a conventional antifuse element in a wiring connection portion. In the semiconductor device shown in the figure, an upper wiring 1 is formed on a lower wiring 2 via an interlayer insulating film 4. A fuse film 3 made of an insulating film is formed on the lower wiring 2 and below the contact plug 5. The programming is performed by applying a high voltage to the upper wiring 1 to cause the dielectric breakdown of the fuse film 3 and making a transition from a non-conductive state to a conductive state. As a result, the upper wiring 1 and the lower wiring 2 are electrically connected. For example, in a DRAM (Dynamic Random Access Memory), information is written to a capacitor manufactured to have the same structure as a cell capacitor by electrically destroying the capacitor insulating film and conducting between the capacitor electrodes. Types of antifuse elements have been considered.

On the other hand, as another example of an electric fuse element, a fuse element that is melted and cut by passing an excessive current through a wiring portion has been studied (Patent Document 1). In this case, in the fuse body in which the silicide film is formed on the polysilicon film, only the fuse cutting portion is made to be easily cut only by the polysilicon film single layer having a melting point lower than that of the refractory metal.
JP 2006-49467 A

  As described above, the antifuse element formed in the conventional semiconductor device cannot be applied to other than DRAM products, and a space of cell capacitor size is required. In addition, in order to produce an antifuse capacitor in the same process as the cell capacitor, a voltage drop increases when a voltage required for the dielectric breakdown is applied, and a larger program power supply circuit than necessary is required.

  Also, in the conventional fuse-cutting type fuse element formed in a semiconductor device, the fuse resistance tends to increase, and there is a problem that the fuse does not melt unless a large voltage is applied.

  It is an object of the present invention to provide a fuse element that can be formed using a process common to a semiconductor device having a transistor, requires less space, and is easy to program, and a method for manufacturing the same.

  The semiconductor device of the present invention is a semiconductor device having an antifuse element having a polysilicon film provided on or above a semiconductor substrate and a metal silicide layer provided on the polysilicon film, The fuse element is provided between the first terminal portion and the second terminal portion both having the polysilicon film and the silicide layer, and between the first terminal portion and the second terminal portion, An antifuse connecting portion that insulates the first terminal portion from the second terminal portion, the fuse body portion including the polysilicon film and the silicide layer; and the metal silicide layer Are arranged at intervals so as to sandwich the antifuse connecting portion.

  With this configuration, a voltage is applied between the two terminal portions, and the antifuse element can be conducted at a relatively low voltage by electromigration of the metal silicide layer. For this reason, the polysilicon film is less likely to be melted when a voltage is applied. Further, the area can be reduced as compared with the conventional antifuse element.

  Note that the anti-fuse element can be formed on the same substrate as the field effect transistor having the gate electrode, and can be disposed between logic cells in the FPGA or used as a memory cell of a nonvolatile memory device, for example. . The antifuse element is preferably provided on the same substrate as the MIS transistor having a so-called FUSI gate which is entirely silicided.

  A first manufacturing method of a semiconductor device of the present invention includes a step (a) of forming a gate electrode made of a polysilicon film and a gate electrode for an antifuse element on a semiconductor substrate via a gate insulating film, and the gate electrode, A step (b) of forming a first insulating film on the antifuse gate electrode and the semiconductor substrate, and a portion of the first insulating film provided on the antifuse element gate electrode; A step (c) of forming a first photoresist film on a part of the first insulating film; and etching the first insulating film using the first photoresist film as a mask to form the gate electrode and the gate for the antifuse element A sidewall is formed on a side surface of the electrode, and the first insulating film is left on a part of the gate electrode for the antifuse element, and then the first photoresist is formed. A step (d) of removing the strike film, and a step (e) of forming a metal silicide layer on at least the semiconductor substrate and the exposed portion of the gate electrode for the antifuse element after the step (d). I have.

  According to a second method of manufacturing a semiconductor device of the present invention, a step (a) of forming a gate electrode made of a polysilicon film and an antifuse element gate electrode on a semiconductor substrate via a gate insulating film, and the gate A step (b) of forming a first insulating film on the electrode, the antifuse gate electrode, and the semiconductor substrate; and being provided on the antifuse element gate electrode in the first insulating film. A step (c) of forming a first photoresist film on a part of the etched portion, and etching the first insulating film using the first photoresist film as a mask to form the antifuse element gate electrode (D) removing the first photoresist film after leaving the first insulating film on a part thereof; and after the step (d), at least on the semiconductor substrate and the anti-resistance. And a step (e) forming a metal silicide layer and on the exposed portion of the gate electrode over's elements.

  According to a third method of manufacturing a semiconductor device of the present invention, a step (a) of forming a gate electrode made of a polysilicon film and an antifuse element gate electrode on a semiconductor substrate via a gate insulating film, A step (b) of forming a first photoresist film opening a part of the fuse gate electrode; and an upper portion of the exposed portion of the gate electrode for the antifuse element using the first photoresist film as a mask. (C) implanting nitrogen ions or oxygen ions into the substrate, and after removing the first photoresist film, at least the nitrogen ions or the oxygen ions on the semiconductor substrate and the gate electrode for the antifuse element are A step (d) of forming a metal silicide layer on the portion excluding the implanted portion.

  According to a fourth method of manufacturing a semiconductor device of the present invention, a step (a) of forming a gate electrode made of a polysilicon film and a gate electrode for an antifuse element on a semiconductor substrate via a gate insulating film, A step (b) of forming a metal silicide layer on the semiconductor substrate and the gate electrode for the antifuse element, and a step of removing a part of the metal silicide layer formed on the gate electrode for the antifuse element (C).

  According to the method as described above, the antifuse element can be manufactured by a process common to the field effect transistor having the gate electrode.

  According to the semiconductor device and the manufacturing method thereof of the present invention, since the antifuse element composed of the polysilicon layer and the metal silicide layer is formed, the area can be reduced as compared with the conventional antifuse element. In addition, the transistor can be easily manufactured by a process common to a transistor having a gate electrode. In addition, since the antifuse element is conducted using electromigration, writing can be performed at a low voltage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1A is a plan view, a cross-sectional view, and an equivalent circuit showing an antifuse element according to the first embodiment of the present invention in an initial state, and FIG. 1B shows the first embodiment after conduction. FIG. 4 is a plan view, a cross-sectional view, and an equivalent circuit of the antifuse element.

  As shown in FIG. 1A, the antifuse element of the present embodiment includes a first terminal portion 22a, a second terminal portion 22b, a first terminal portion 22a, and a second terminal portion 22b. And a fuse body 23 provided therebetween. As can be seen from the equivalent circuit, the fuse body portion 23 is disposed between the portion connected to the first terminal portion 22a, the portion connected to the second terminal portion 22b, and the first portion. The terminal portion 22a and the second terminal portion are configured by an antifuse connecting portion 24 that substantially insulates the terminal portion 22a and the second terminal portion.

Specifically, the antifuse element of the present embodiment includes a polysilicon film 20 having a thickness of, for example, about 60 nm to 160 nm formed on a semiconductor substrate made of silicon or the like with a gate insulating film interposed therebetween, and an antifuse connection portion. It is composed of a metal silicide film such as a NiSi film 21 having a thickness of about 15 nm to 50 nm formed on the polysilicon film 20 except for 24. The impurity concentration in the polysilicon film 20 is 1 × 10 ²¹ cm ⁻³ or less, and the polysilicon film 20 has a very high resistance (substantially in an insulating state). In the example shown in FIG. 1A, the antifuse connection portion 24 in which the NiSi film 21 is not formed is provided in the approximate center of the fuse body portion 23. The width of the fuse body 23 is narrower than that of the first terminal portion 22a and the second terminal portion 22b.

  The length L of the fuse body 23 is, for example, 1 μm, the width W is in the range of 100 nm to 500 nm, and the space S of the antifuse connection portion 24 is preferably formed in the range of 100 nm to 500 nm. This is because if the space S is less than 100 nm, sufficient insulation cannot be maintained in the initial state, and if it exceeds 500 nm, it is difficult to conduct by electromigration. The sheet resistance of the polysilicon film 20 can be adjusted between 4 kΩ / □ and 400 kΩ / □ depending on the impurity concentration. However, in order to make the antifuse connecting portion 24 substantially in an insulating state, the sheet resistance is 10 kΩ / □ or more. Preferably there is.

  Since the antifuse element of this embodiment can be conducted at a lower voltage than a conventional antifuse element utilizing dielectric breakdown, programming (operation for conducting) can be easily performed. In addition, the antifuse element of this embodiment can have a smaller area than a conventional antifuse element that uses a cell capacitor. Further, since it is made of polysilicon and silicide, it can be easily manufactured by a process common to a transistor having a gate electrode.

  Next, a method for using the antifuse element of the present embodiment, its use, and the like will be described. In the following description, an antifuse element having L = 1 μm, W = 100 nm, and S = 100 nm will be described.

  FIG. 1B shows a state where the antifuse connection portion 24 is short-circuited by causing electromigration to Ni in the antifuse element shown in FIG. In this state, for example, by applying a voltage of 0 V to the first terminal portion 22a and 3.3V to the second terminal portion 22b, electrons flowing in the direction from the first terminal portion 22a to the second terminal portion 22b. This can be realized by electromigration of Ni in the direction toward the second terminal portion 22b by wind friction. By this operation, the antifuse connecting portion 24 is irreversibly shorted in the same manner as the insulating film breakdown type antifuse element, but this short circuit can be realized with an applied voltage lower than the dielectric breakdown. Although depending on the size and the like of the antifuse element, the voltage applied between the first terminal portion 22a and the second terminal portion to make the antifuse element conductive is about 1V to 5V. If the voltage applied between the terminals is about 3.3 V as in the present embodiment, the current flowing through the polysilicon film 20 is 10 mA or less, so that the polysilicon film 20 itself cannot melt.

In the antifuse element of the present embodiment, metal silicide is used, and Ni silicide is most preferably used among them. This is because, for example, Ni has a characteristic of easily diffusing in silicon as compared with Ti and Co which are silicide metals. For example, the solid solubility of Ni in silicon is 10 4 to 6 6 greater than Co. In addition, the self-diffusion coefficient is 2 × 10 ^{−4 for} Ti and 2.3 × 10 ⁻¹ for Co, whereas Ni is very large at 1.27. Furthermore, the closest melting point to 1410 ° C. for silicon is 1455 ° C. for Ni, and 1495 ° C. for Co. The melting point is the second closest to Ni, but Ti is 1668 ° C., so Si starts to move first. . That is, it is considered that a metal having a large self-diffusion coefficient and a melting point equal to or lower than that of silicon is likely to cause electromigration in polysilicon like Ni. Therefore, even if a silicide film of Ca (self-diffusion coefficient 8.3, melting point 893 ° C.) and Mg (self-diffusion coefficient 1.5, melting point 650 ° C.) is used, the same effect as in the case of using Ni can be obtained. Conceivable.

  Next, with reference to FIG. 2, a mask ROM capable of logical design using an antifuse element incorporated in a semiconductor substrate together with other circuits will be described. 2A and 2B are diagrams showing circuit configuration examples of the mask ROM, and FIG. 2C is a diagram showing a circuit configuration example using the antifuse element of the present invention in the mask ROM.

  Since the mask ROM writes information to the circuit pattern at the manufacturing stage, the memory information cannot be changed once it is produced. There are two main information writing methods, and one is a method of determining a ROM code (1,0 pattern) based on the presence or absence of a memory transistor at each address, as shown in FIG. Address 30 with a memory transistor stores 1 and address 31 without a memory transistor stores 0. As shown in FIG. 2B, the other method is a method in which memory transistors are formed in all addresses, and information to be stored is determined by whether or not the transistors are connected to the bit lines. The address 32 connected to the bit line stores “1”, and the address 33 not connected to the bit line stores “0”.

  Therefore, in the manufacturing stage of the mask ROM shown in FIG. 2B, the antifuse of the present invention is formed between the memory transistor and the bit line, and all addresses are set to “0”. After shipment, “1” can be stored by connecting an antifuse of a desired address, and the user can freely perform logic design. As shown in FIG. 2C, the shipment fuse 34 stores 0, and the short fuse 35 after shipment stores 1.

  Further, with reference to FIGS. 3A and 3B, an FPGA (Field Programmable Gate Array) that can be programmed by an antifuse element incorporated together with other circuits on a semiconductor substrate will be described. The FPGA regularly arranges programmable logic cells, prepares a wiring area between them, and implements a logic circuit by programming each logic cell and the wiring area. FIG. 3A is a diagram illustrating a circuit configuration example of the FPGA. The antifuse element of the present invention is incorporated in a portion where the internal wiring 1 and the internal wiring 2 intersect.

  Specifically, as shown in FIG. 3B, for example, the first terminal portion of the antifuse element is connected to the first internal wiring 50 via the contact plug 54, and the second terminal of the antifuse element is connected. This part is connected to the second internal wiring 52.

  With the above configuration, an FPGA that can be programmed with a lower voltage than the conventional one can be realized, and power saving can be achieved. In addition, the wiring area can be reduced as compared with the case of using the conventional antifuse element shown in FIG. 23, and the degree of integration can be improved.

  In addition, since the antifuse element of this embodiment is composed of polysilicon, which is the same material as the gate electrode of the MIS transistor, and a metal silicide layer, an element having a gate electrode (such as a field effect transistor) is formed. It can be easily formed on the same substrate as the manufactured semiconductor device by a common process.

  Note that the size of the antifuse element described in the present embodiment is an example, and is not limited to the above values.

(Second Embodiment)
FIGS. 4A and 4B are structural views showing an antifuse element according to the second embodiment of the present invention. FIG. 4A shows an anti-fuse element in which the width of the fuse body 23 is gradually increased. Here, the fuse body portion 23 has three levels of width, and an antifuse connection portion in which no silicide layer is formed is provided in each portion having a different width. In the equivalent circuit, three antifuse elements F1, F2, and F3 are connected in series with each other in order from the narrowest width.

  When a voltage is applied between the terminals, the antifuse F2 and the antifuse F3 are connected in order from the narrow antifuse F1. In the initial state, as shown in the equivalent circuit, all of the antifuses F1 to F3 are open. FIG. 4B shows a state in which a fuse is connected when a voltage is applied between the pads and the potential difference between both ends of F1 becomes 3.3V. The widths of the polysilicon film and the silicide film in the antifuses F1, F2, and F3 may be arbitrary as long as they are narrower than the widths of the first terminal portion and the second terminal portion, and the interval between the antifuse connection portions is about 100 nm to 500 nm. It is. The lengths of the antifuses F1, F2, and F3 may be arbitrary. Further, the sheet resistance of the polysilicon film can be adjusted between 4 kΩ / □ and 400 kΩ / □ depending on the impurity concentration. However, in order to make the antifuse connection portion substantially insulated, the sheet resistance is 10 kΩ / □ or more. Preferably there is.

  Next, the operation of the antifuse element according to the present embodiment will be described in detail with reference to FIG. FIG. 5A is a plan view showing an antifuse element according to this embodiment having a standard size. Here, an example is shown in which antifuses F1, F2, and F3, each having a fuse body length of 1 μm and an antifuse connection space of 100 nm, are connected in series. The widths of the antifuses F1, F2, and F3 are 100 nm, 125 nm, and 167 nm in this order, the length of each antifuse is 1 μm, and the sheet resistance of the polysilicon film constituting the antifuse element is 500Ω / □. The voltage application was such that the left terminal (first terminal part) was 0 V and the right terminal (second terminal part) was variable.

  FIG. 5B is a graph showing the relationship between the voltage applied to the right terminal and the current flowing through the fuse. First, as shown in the graph until F1 is short-circuited, when a voltage of 7.92 V is applied between the first terminal portion and the second terminal portion, the potential difference applied to F1 becomes 3.3 V, A current of 6.6 mA flows and F1 is short-circuited. Since the current flowing through F1 is 10 mA or less, the polysilicon film does not melt. Subsequently, when a voltage of 5.78 V is applied between the first terminal portion and the second terminal portion, the potential difference applied to F2 becomes 3.3 V, a current of 8.3 mA flows, and F2 is short-circuited. Again, since the current is suppressed to 10 mA or less, the polysilicon film does not melt. In other words, by adjusting the width of the fuse and the sheet resistance of the polysilicon film, the antifuse connection portions of a plurality of antifuses connected in series can be selectively short-circuited. It is also possible to control the voltage for short-circuiting each antifuse.

  With reference to FIGS. 6A and 6B, a resistance trimming method using the antifuse element of this embodiment will be described.

  FIG. 6A is a conventional trimming circuit diagram using three antifuses and four terminals. The resistance value R of the entire antifuse element in the initial state is represented by r1 + r2 + r3. As a result of evaluating the device characteristics, when it is necessary to lower the resistance value, F1 is short-circuited to lower resistance R to r2 + r3, or F1 and F2 are short-circuited to lower resistance R to r3. Trimming is performed as appropriate. The antifuse element is short-circuited by applying a voltage between two terminals sandwiching the antifuses F1 to F3. FIG. 6B is a trimming circuit using the antifuse element of the present embodiment shown in FIG. When this trimming circuit is used to connect even an antifuse having a desired width, a resistance adjustment function similar to that of the conventional trimming circuit shown in FIG.

  According to the trimming circuit of the present embodiment, the number of terminals for applying a voltage to the antifuse is only two, so the number of terminals can be reduced as compared with the conventional trimming circuit. Therefore, space saving of the trimming circuit can be achieved. Such a trimming circuit is used for various circuits such as a logic circuit.

  The number of antifuses provided in one antifuse element may be four or more as long as they have different widths, or may be two.

(Third embodiment)
FIGS. 7A to 7H and FIGS. 8A to 8H illustrate a method of manufacturing a semiconductor device having a MOS transistor and the antifuse element of the present invention according to the third embodiment of the present invention. It is sectional drawing shown. Here, a case where the MOS transistor has a gate electrode (FUSI gate) made of metal silicide will be described as an example.

  First, as shown in FIG. 7A, an element isolation region 101 such as STI that partitions three element formation regions 201, 202, and 203 is formed on a semiconductor substrate made of silicon, and then a semiconductor is formed by thermal oxidation or the like. A gate insulating film 102 having a thickness of about 1.6 nm is formed on the substrate. Here, an N-channel MOS transistor, a P-channel MOS transistor, and the antifuse element of the present invention are formed in the element formation regions 201, 202, and 203, respectively, in a later process. Next, a polysilicon film 103 and a silicon oxide film 104 are sequentially formed on the semiconductor substrate on the gate insulating film 102 by a CVD method or the like. The thickness of the polysilicon film 103 is 100 nm, for example, and the thickness of the silicon oxide film 104 is 25 nm.

  Next, as shown in FIG. 7B, a photoresist film 105 having a predetermined pattern is formed. Thereafter, as shown in FIG. 7C, the silicon oxide film 104 is subjected to anisotropic dry etching using the photoresist film 105 as a mask to form a hard mask 106. Next, the photoresist film 105 is removed.

  Subsequently, as shown in FIG. 7D, a photoresist film 105a is formed on the element formation region 203 as a gate electrode pattern for the antifuse element.

  Next, as shown in FIG. 7E, the polysilicon film 103 and the gate insulating film 102 are sequentially patterned by anisotropic dry etching using the hard mask 106 and the photoresist film 105a as a mask to form the gate electrode 107a. Then, an antifuse element gate electrode 107b is formed. Further, a low concentration impurity layer 108 is formed in a region of the semiconductor substrate located on the side of the gate electrode 107a and the antifuse element gate electrode 107b. Here, the low-concentration impurity layer 108 is formed in a self-aligned manner with respect to the gate electrode 107a and the antifuse element gate electrode 107b by ion implantation.

  Next, as shown in FIG. 7F, in each element formation region, a silicon nitride film 109 having a thickness of 40 nm is formed so as to cover each MOS transistor and antifuse element gate electrode 107b by CVD or the like. Form.

  Next, as shown in FIG. 7G, a photoresist film 105b is formed as a connection pattern on the antifuse element gate electrode 107b. FIG. 9A shows the antifuse element gate electrode 107b in a state where the photoresist film 105b is formed.

  Next, as shown in FIG. 7H, the silicon nitride film 109 is patterned by anisotropic dry etching using the photoresist film 105b as a mask to form side surfaces of the gate electrode 107a and the gate electrode 107b for the antifuse element. A sidewall 110 is formed thereon, and an antifuse connection portion 111 is formed on a part of the antifuse element gate electrode 107b. In this step, the antifuse connection portion 111 is formed using a silicon nitride film for forming a sidewall. The state of the semiconductor device when this step is completed is shown in FIG.

  Next, as shown in FIG. 8A, a high-concentration impurity layer 112 is formed in a self-aligning manner by using the gate electrode 107a, the antifuse element gate electrode 107b, and the sidewall 110 as a mask by ion implantation.

  Next, as shown in FIG. 8B, a Ni film 113 having a thickness of 10 nm is formed on the entire surface of the semiconductor device by sputtering or the like, and further a TiN film 114 having a thickness of 15 nm is formed on the Ni film 113. Form.

  Next, as shown in FIG. 8C, after the first RTA (Rapid Thermal Annealing) process is performed under the conditions of 300 ° C. and 30 seconds, the unreacted Ni film 113 and TiN film 114 are removed. When removing the excess Ni film 113 and TiN film 114, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed may be used, or ammonium hydroxide and hydrogen peroxide water are mixed. It is also possible to use alkaline solutions. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds to form a NiSi film 115 on the high concentration impurity layer 112 and the antifuse element gate electrode 107b. Here, FIG. 9C shows the state of the semiconductor device when this process is completed.

  Next, as shown in FIG. 8D, after removing the silicon nitride film 109 remaining in the antifuse connection portion 111, a liner having a thickness of 20 nm is formed on the entire surface of the semiconductor device including the MOS transistor by a CVD method or the like. After forming the nitride film 116, an interlayer insulating film 117 made of silicon oxide is formed on the liner nitride film 116.

  Next, as shown in FIG. 8E, the liner insulating film 116 is etched by etching the interlayer insulating film 117 in a region excluding the element formation region 203 where the antifuse element gate electrode 107b is not formed. Expose the top of.

  Subsequently, as shown in FIG. 8F, the upper surface of the gate electrode 107a made of a polysilicon film is exposed by opening the gate electrode 107a. At this time, the interlayer insulating film 117 is still provided above the antifuse element gate electrode 107b.

  As shown in FIG. 8G, in the element formation region 202 for forming the P-channel type MOS transistor, the upper portion of the gate electrode 107a made of the polysilicon film is removed by hydrofluoric acid-based wet etching to form an on-gate trench. 118 is formed. At this time, the thickness of the gate electrode 107a is 100 nm in the element formation region 201 for forming the N-channel MOS transistor, and the thickness of the gate electrode 107a is 50 nm in the element formation region 202 for forming the P-channel MOS transistor. It is. Next, the interlayer insulating film 117 is removed.

Next, as shown in FIG. 8 (h), as the FUSI process, a Ni film having a thickness of 60 nm and a TiN film having a thickness of 15 nm are formed in this order, and the first RTA process is performed at 300 ° C. for 30 seconds. . Further, the unreacted Ni film and TiN film are removed. In order to remove the unreacted Ni film and TiN film, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide solution are mixed may be used, or ammonium hydroxide and hydrogen peroxide solution are mixed. Alkaline solutions can also be used. Next, the second RTA process is performed at 500 ° C. for 30 seconds, thereby converting the entire gate electrode 107a of the N-channel MOS transistor into the NiSi film 115, and the entire gate electrode of the P-channel MOS transistor. The Ni ₂ Si film 119 is converted.

  As described above, when the antifuse element of the present invention is formed by a process common to the MOS transistor having the FUSI gate, it is possible to avoid the unexpected situation that the MOS transistor gate is blown during the fuse programming. This is because the MOS transistor gate is formed of only the refractory metal silicide even when the fuse program voltage (3V to 8V) is applied.

  The antifuse element shown in the second embodiment of the present invention can also be realized by the manufacturing method shown in the third embodiment. Specifically, in the process shown in FIG. 7D, the antifuse element gate electrode pattern is simply formed into a desired shape by the photoresist film 105a.

Incidentally, the anti-fuse element of the present embodiment is using NiSi film, the use of Ca 2 _Si film or Mg 2 _Si film can exert the same effect as the anti-fuse element of the present embodiment. However, when the silicide metal used for the antifuse element is different from the FUSI gate material, a silicide film is formed only on the antifuse element after the process shown in FIG. This can be realized by forming a mask on top.

-Modification of the third embodiment-
As a modified example of the third embodiment, a method of manufacturing the antifuse element of the present invention by a process common to a MOS transistor having a gate electrode whose upper part is silicided will be described.

  FIGS. 10A to 10G and FIGS. 11A to 11C illustrate a method for manufacturing a semiconductor device having a MOS transistor and an antifuse element according to a modification of the third embodiment of the present invention. It is sectional drawing shown. It is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention.

  First, as shown in FIG. 10A, after forming an element isolation region 101 such as STI for partitioning two element formation regions 201 and 203 on a semiconductor substrate, gate insulation is formed on the semiconductor substrate by thermal oxidation or the like. A film 102 is formed, and subsequently, a polysilicon film 103 having a thickness of about 100 nm is formed on the gate insulating film 102. In the element formation regions 201 and 203, an N-channel MOS transistor and the antifuse element of the present invention are formed in a later process.

  Next, as shown in FIG. 10B, a photoresist film 105a having a predetermined pattern is formed on predetermined regions of the element formation regions 201 and 203. Next, as shown in FIG. Then, as shown in FIG. 10C, anisotropic etching of the polysilicon film 103 and the gate insulating film 102 is performed using the photoresist film 105a to make the gate insulating film 102 into a predetermined shape, and the gate electrode 107a and antifuse element gate electrode 107b are formed. Further, after removing the photoresist film 105a, a low concentration impurity layer 108 is formed in regions of the semiconductor substrate located on both sides of the gate electrode 107a and the antifuse element gate electrode 107b.

  Next, as shown in FIG. 10D, a silicon nitride film 109 having a thickness of about 40 nm is formed on the semiconductor substrate, the gate electrode 107a, and the antifuse element gate electrode 107b.

  Next, as shown in FIG. 10E, a photoresist film 105b is formed on a part of the silicon nitride film 109 located on the antifuse element gate electrode 107b. The semiconductor device after completion of this process is as shown in FIG.

  Next, as shown in FIG. 10F, the silicon nitride film 109 is removed by anisotropic dry etching using the photoresist film 105b. Accordingly, the antifuse connection portion 111 can be formed simultaneously with the formation of the sidewalls 110 on both side surfaces of the gate electrode 107a and the antifuse element gate electrode 107b. The semiconductor device after this process is completed is as shown in FIG.

  Next, as shown in FIG. 10G, the high-concentration impurity layer 112 is formed in a self-aligned manner by ion implantation using the gate electrode 107a, the antifuse element gate electrode 107b, and the sidewalls as a mask.

  Next, as shown in FIG. 11A, a Ni film 113 having a thickness of about 10 nm is formed on the entire surface of the semiconductor device by sputtering or the like, and TiN having a thickness of about 15 nm is further formed on the Ni film 113. A film is formed.

  Next, as shown in FIG. 11B, after the first RTA treatment is performed at 300 ° C. for 30 seconds, the unreacted Ni film 113 and TiN film 114 are removed. When removing the excess Ni film 113 and TiN film 114, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed may be used, or ammonium hydroxide and hydrogen peroxide water are mixed. It is also possible to use alkaline solutions. Subsequently, a second RTA process is performed under conditions of 500 ° C. for 30 seconds, so that the high concentration impurity layer 112, the gate electrode 107a, and the antifuse element gate electrode 107b excluding the antifuse connection portion 111 are respectively formed. A NiSi film 115 is formed. Here, FIG. 9C shows the state of the semiconductor device when this process is completed.

  Next, as illustrated in FIG. 11C, a liner nitride film 116 having a thickness of 20 nm is formed on the entire surface of the semiconductor device including the MOS transistor by a CVD method or the like, and then a silicon oxide film is formed on the liner nitride film 116. An interlayer insulating film 117 made of is formed.

  As described above, even when the gate electrode of the MOS transistor is not a FUSI gate, it can be manufactured using a process common to the antifuse of the present invention.

(Fourth embodiment)
12 (a) to 12 (i) and FIGS. 13 (a) to 13 (h) show a method of manufacturing a semiconductor device having a MOS transistor and the antifuse element of the present invention according to the fourth embodiment of the present invention. It is sectional drawing shown. Here, a case where the MOS transistor has a gate electrode (FUSI) made of metal silicide will be described as an example.

  First, the gate insulating film 102, the gate electrode 107a, the antifuse element gate electrode 107b, and the silicon nitride film 109 are formed on the semiconductor substrate by the steps shown in FIGS. The steps up to here are the same as those described with reference to FIGS.

  Next, as shown in FIG. 12G, the silicon nitride film 109 is patterned by anisotropic dry etching to form sidewalls 110 on both side surfaces of the gate electrode 107a and the antifuse element gate electrode 107b. To do. Subsequently, a high-concentration impurity layer 112 is formed in a self-aligning manner by ion implantation using the gate electrode 107a, the antifuse element gate electrode 107b, and the sidewall 110 as a mask.

  Next, as shown in FIG. 12H, a silicon oxide film 120 having a thickness of 30 nm is formed on the entire surface of the semiconductor device by a CVD method or the like.

  Next, as shown in FIG. 12I, a photoresist film 105c is formed on a portion of the silicon oxide film 120 provided on the antifuse element gate electrode 107b. The semiconductor device at the end of this step is shown in FIG.

  Next, as shown in FIG. 13A, the silicon oxide film 120 is patterned by anisotropic dry etching using the photoresist film 105c as a mask to form the antifuse connection portion 111. Next, as shown in FIG. FIG. 14B shows the antifuse connection portion 111 created by using the formation process of the silicon oxide film 120 for forming the non-silicide region.

  Next, as shown in FIG. 13B, a Ni film 113 having a thickness of 10 nm is formed, and a TiN film 114 having a thickness of 15 nm is further formed thereon.

  Next, as shown in FIG. 13C, after the first RTA (Rapid Thermal Annealing) process is performed under the conditions of 300 ° C. and 30 seconds, the unreacted Ni film 113 and TiN film 114 are removed. When removing the excess Ni film 113 and TiN film 114, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed may be used, or ammonium hydroxide and hydrogen peroxide water are mixed. It is also possible to use alkaline solutions. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds to form a NiSi film 115 on the high concentration impurity layer 112 and the antifuse element gate electrode 107b. Here, FIG. 14C shows the state of the semiconductor device when this process is completed.

  Next, as shown in FIG. 13D, a liner nitride film 116 having a thickness of 20 nm is formed on the entire surface of the semiconductor device including the MOS transistor by CVD or the like, and then silicon oxide is formed on the liner nitride film 116. An interlayer insulating film 117 made of is formed.

  Next, as shown in FIG. 13E, the interlayer insulating film 117 is etched to remove the liner nitride film in a region excluding the element formation region 203 provided with the antifuse element gate electrode 107b not subjected to FUSI. The top of 116 is exposed.

  Next, as shown in FIG. 13F, the upper surface of the gate electrode 107a made of a polysilicon film is exposed by opening the gate electrode 107a. Subsequently, as shown in FIG. 13G, in the element formation region 202 for forming the P-channel MOS transistor, the upper portion of the gate electrode 107a made of the polysilicon film is removed by hydrofluoric acid-based wet etching to form a gate. An upper trench 118 is formed. At this time, the thickness of the gate electrode is 100 nm in the element formation region 201 for forming the N-channel MOS transistor, and the thickness of the gate electrode 107a is 50 nm in the element formation region 202 for forming the P-channel MOS transistor. is there. Next, the interlayer insulating film 117 is removed.

Next, as shown in FIG. 13 (h), as the FUSI process, a Ni film having a thickness of 60 nm and a TiN film having a thickness of 15 nm are formed thereon, and the first RTA treatment is performed at 300 ° C. for 30 seconds. I do. Further, the unreacted Ni film and TiN film are removed. For this purpose, for example, an acidic solution obtained by mixing sulfuric acid or hydrochloric acid and hydrogen peroxide solution may be used, or an alkaline solution obtained by mixing ammonium hydroxide and hydrogen peroxide solution may be used. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds, whereby the polysilicon film is formed as the NiSi film 115 for the gate electrode of the element formation region 201 for forming the N-channel MOS transistor, The gate electrode 107a in the element formation region 202 for forming the P-channel MOS transistor is converted to the Ni ₂ Si film 119 and subjected to FUSI processing.

  As described above, when the antifuse element of the present invention is formed by a process common to the MOS transistor having the FUSI gate, an unexpected situation in which the MOS transistor gate is blown during fuse programming can be avoided. This is because even when a fuse program voltage (3V to 8V) is applied, the MOS transistor gate is formed only of a low-resistance refractory metal silicide, so that it is difficult to generate heat. In the method of the present embodiment, the step shown in FIG. 12I for forming the antifuse connecting portion 111 can be performed simultaneously with the step of creating a mask for protecting a region that is not silicided. Therefore, the antifuse element of the present invention can be formed with a smaller number of steps than the method according to the third embodiment.

  Further, the antifuse element according to the second embodiment of the present invention can also be realized by the manufacturing method shown in the present embodiment. Specifically, in the step shown in FIG. 12D, the antifuse element gate electrode pattern is simply formed into a desired shape by the photoresist film 105a.

Incidentally, the anti-fuse element of the present embodiment is using NiSi film, the use of Ca 2 _Si film or Mg 2 _Si film can exert the same effect as the anti-fuse element of the present embodiment.

-Modification of the fourth embodiment-
As a modification of the fourth embodiment, a method for manufacturing the antifuse element of the present invention by a process common to a MOS transistor having a gate electrode whose upper part is silicided will be described.

  FIGS. 15A to 15H and FIGS. 16A to 16C show a method of manufacturing a semiconductor device having a MOS transistor and an antifuse element according to a modification of the fourth embodiment of the present invention. It is sectional drawing shown.

  First, as shown in FIGS. 15A to 15D, a gate insulating film 102, a gate electrode 107a, an antifuse element gate electrode 107b, and a silicon nitride film 109 are formed on a semiconductor substrate, and then formed in the semiconductor substrate. A low concentration impurity layer 108 is formed. The steps so far are the same as the method according to the modification of the third embodiment shown in FIGS.

  Next, as shown in FIG. 15E, by performing etch back of the silicon nitride film 109, the side walls 110 made of the silicon nitride film 109 are formed on both sides of the gate electrode 107a and the antifuse element gate electrode 107b. Form on the surface.

  Next, as shown in FIG. 15F, ion implantation is performed using the gate electrode 107a, the antifuse element gate electrode 107b, and the sidewall 110 as a mask to form a low-concentration impurity layer in the semiconductor substrate. A silicon oxide film 120 having a thickness of 30 nm is formed on the entire surface of the semiconductor device.

  Next, as shown in FIG. 15G, a photoresist film 105c is formed on a part of the silicon oxide film 120 provided on the antifuse element gate electrode 107b. The semiconductor device at the end of this step is shown in FIG.

  Next, as shown in FIG. 15H, after the silicon oxide film 120 is removed by anisotropic dry etching using the photoresist film 105c as a mask, the photoresist film 105c is removed. Thereby, the antifuse connecting portion 111 is formed. The semiconductor device at the end of this step is shown in FIG.

  Next, as shown in FIG. 16A, a Ni film 113 having a thickness of about 10 nm is formed on the entire surface of the semiconductor device by sputtering or the like, and TiN having a thickness of about 15 nm is further formed on the Ni film 113. A film is formed.

  Next, as shown in FIG. 16B, after the first RTA treatment is performed at 300 ° C. for 30 seconds, the unreacted Ni film 113 and TiN film 114 are removed. When removing the excess Ni film 113 and TiN film 114, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed may be used, or ammonium hydroxide and hydrogen peroxide water are mixed. It is also possible to use alkaline solutions. Subsequently, a second RTA process is performed under conditions of 500 ° C. for 30 seconds, so that the high concentration impurity layer 112, the gate electrode 107a, and the antifuse element gate electrode 107b excluding the antifuse connection portion 111 are respectively formed. A NiSi film 115 is formed.

  Next, as illustrated in FIG. 16C, a liner nitride film 116 having a thickness of 20 nm is formed on the entire surface of the semiconductor device including the MOS transistor by CVD or the like, and then a silicon oxide film is formed on the liner nitride film 116. An interlayer insulating film 117 made of is formed.

  As described above, even when the gate electrode of the MOS transistor is not a FUSI gate, it can be manufactured using a process common to the antifuse of the present invention.

(Fifth embodiment)
17A to 17H and FIGS. 18A to 18H show a method of manufacturing a semiconductor device having a MOS transistor and the antifuse element of the present invention according to the fifth embodiment of the present invention. It is sectional drawing shown. Here, a case where the MOS transistor has a gate electrode (FUSI) made of metal silicide will be described as an example.

  First, the gate insulating film 102, the gate electrode 107a, the antifuse element gate electrode 107b, the sidewall 110, and the like are formed on the semiconductor substrate by the steps shown in FIGS. 17A to 17G. A concentration impurity layer 108 and a high concentration impurity layer 112 are formed. The steps up to here are the same as those described with reference to FIGS.

As shown in FIG. 17H, a photoresist film 105d that opens only above a part of the antifuse element gate electrode 107b (the part that will later become the antifuse connecting portion 111) is formed on the semiconductor device. Subsequently, by ion implantation, nitrogen ions are applied only to the connection portion on the antifuse element gate electrode 107b at an acceleration voltage of 1 keV and an injection amount of 1.3 × 10 ¹⁵ / cm ^2. Implanted in the vicinity of the upper surface of 107b. FIG. 19A shows the antifuse element gate electrode 107b in a state where the connection portion pattern is formed.

  Next, as shown in FIG. 18A, the photoresist film 105d is removed. Note that the nitrogen implantation layer 131 is formed in the vicinity of a part of the upper surface of the gate electrode 107b for the antifuse element by the ion implantation process shown in FIG. The antifuse element gate electrode 107b at this time is shown in FIG. This process is a characteristic process of the manufacturing method of this embodiment. Note that the step of forming the nitrogen implantation layer 131 can be performed before the formation of the sidewall 110, for example, but is preferably performed immediately before the silicide formation step in order to prevent the nitrogen implantation layer 131 from being reduced by dry etching. .

  Next, as shown in FIG. 18B, a Ni film 113 having a thickness of 10 nm is formed on the entire surface of the semiconductor device, and a TiN film 114 having a thickness of 15 nm is further formed thereon.

  Subsequently, as shown in FIG. 18C, after the first RTA treatment is performed at 300 ° C. for 30 seconds, the unreacted Ni film 113 and TiN film 114 are removed. When removing the excess Ni film 113 and TiN film 114, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed may be used, or ammonium hydroxide and hydrogen peroxide water are mixed. It is also possible to use alkaline solutions. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds to form a NiSi film 115 on the high concentration impurity layer 112 and the antifuse element gate electrode 107b. FIG. 19C shows the antifuse element gate electrode 107b at the end of this step. As shown in the figure, since the polysilicon and Ni do not react in the region where nitrogen ions are implanted, silicide (NiSi) is not formed. The portion where the silicide is not formed becomes the antifuse connection portion 111.

  Next, as shown in FIG. 18D, a liner nitride film 116 having a thickness of 20 nm is formed on the entire surface of the semiconductor device including the MOS transistor by CVD or the like, and then silicon oxide is formed on the liner nitride film 116. An interlayer insulating film 117 made of is formed. Next, as shown in FIG. 18E, the liner insulating film 116 is etched by etching the interlayer insulating film 117 in a region excluding the element formation region 203 where the antifuse element gate electrode 107b is not formed. Expose the top of.

  Next, as shown in FIG. 18F, the upper surface of the gate electrode 107a made of a polysilicon film is exposed by opening the gate electrode 107a. Subsequently, as shown in FIG. 18G, the upper portion of the gate electrode 107a made of a polysilicon film is removed by hydrofluoric acid wet etching in the element formation region 202 for forming the P-channel MOS transistor, An upper trench 118 is formed. At this time, the thickness of the gate electrode is 100 nm in the element formation region 201 for forming the N-channel MOS transistor, and the thickness of the gate electrode 107a is 50 nm in the element formation region 202 for forming the P-channel MOS transistor. is there. Next, the interlayer insulating film 117 is removed.

Next, as shown in FIG. 18 (h), as the FUSI process, a Ni film having a thickness of 60 nm and a TiN film having a thickness of 15 nm are formed thereon, and the first RTA treatment is performed at 300 ° C. for 30 seconds. Do. Further, the unreacted Ni film and TiN film are removed. For this purpose, for example, an acidic solution obtained by mixing sulfuric acid or hydrochloric acid and hydrogen peroxide solution may be used, or an alkaline solution obtained by mixing ammonium hydroxide and hydrogen peroxide solution may be used. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds, whereby the polysilicon film is formed as the NiSi film 115 for the gate electrode of the element formation region 201 for forming the N-channel MOS transistor, The gate electrode 107a in the element formation region 202 for forming the P-channel MOS transistor is converted to the Ni ₂ Si film 119 and subjected to FUSI processing.

  As described above, when the antifuse element of the present invention is formed by a process common to the MOS transistor having the FUSI gate, an unexpected situation in which the MOS transistor gate is blown during fuse programming can be avoided. This is because even when a fuse program voltage (3V to 8V) is applied, the MOS transistor gate is formed only of a low-resistance refractory metal silicide, so that it is difficult to generate heat.

  In this embodiment, nitrogen is implanted in the step shown in FIG. 17H. However, even if oxygen is implanted, the same effect as this embodiment can be exhibited.

  Further, the antifuse element according to the second embodiment of the present invention can also be realized by the manufacturing method shown in the present embodiment. Specifically, in the step shown in FIG. 17D, the antifuse element gate electrode pattern is merely formed into a desired shape by the photoresist film 105a.

Incidentally, the anti-fuse element of the present embodiment is using NiSi film, the use of Ca 2 _Si film or Mg 2 _Si film can exert the same effect as the anti-fuse element of the present embodiment.

  Further, a method of forming the antifuse connection portion 111 using the nitrogen implantation layer 131 formed in the steps shown in FIGS. 17H and 18A is the same as that of the antifuse element and the gate electrode of the present invention. It is also possible to apply to a manufacturing method of a semiconductor device including only a silicided MOS transistor.

(Sixth embodiment)
20A to 20H and FIGS. 21A to 21H show a method of manufacturing a semiconductor device having a MOS transistor and the antifuse element of the present invention according to the sixth embodiment of the present invention. It is sectional drawing shown. Here, a case where the MOS transistor has a gate electrode (FUSI) made of metal silicide will be described as an example.

  20A to 20G, a gate insulating film 102, a gate electrode 107a, an antifuse element gate electrode 107b, a sidewall 110, and the like are formed on a semiconductor substrate, and the semiconductor substrate has a low thickness. A concentration impurity layer 108 and a high concentration impurity layer 112 are formed. The steps up to here are the same as those described with reference to FIGS.

  As shown in FIG. 20H, a Ni film 113 having a thickness of 10 nm is formed on the entire surface of the semiconductor device, and a TiN film 114 having a thickness of 15 nm is further formed thereon.

  As shown in FIG. 21A, after the first RTA treatment is performed at 300 ° C. for 30 seconds, the unreacted Ni film 113 and TiN film 114 are removed. When removing the excess Ni film 113 and TiN film 114, for example, an acidic solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed may be used, or ammonium hydroxide and hydrogen peroxide water are mixed. It is also possible to use alkaline solutions. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds to form a NiSi film 115 on the high concentration impurity layer 112 and the antifuse element gate electrode 107b. The state of the antifuse element gate electrode 107b at the end of this step is shown in FIG.

  Next, as shown in FIG. 21B, a photoresist film 105e is formed on the semiconductor device that opens only above part of the gate electrode 107b for the antifuse element (the part that will later become the antifuse connection part 111). To do. FIG. 22B shows the state of the antifuse element gate electrode 107b at the end of this step.

  Next, as shown in FIG. 21C, the NiSi film 115 is patterned by removing the NiSi film 115 on the antifuse element gate electrode 107b by anisotropic dry etching using the photoresist film 105e as a mask. Then, the antifuse connecting portion 111 is formed. Thereafter, the photoresist film 105e is removed. The state of the antifuse element gate electrode 107b at the end of this step is shown in FIG.

  Next, as shown in FIG. 21D, a liner nitride film 116 having a thickness of 20 nm is formed on the entire surface of the semiconductor device including the MOS transistor by CVD or the like, and then silicon oxide is formed on the liner nitride film 116. An interlayer insulating film 117 made of is formed.

  Next, as shown in FIG. 21E, the interlayer insulating film 117 is etched to remove the liner nitride film in a region excluding the element formation region 203 provided with the antifuse element gate electrode 107b not subjected to FUSI. The top of 116 is exposed.

  Next, as shown in FIG. 21F, the upper surface of the gate electrode 107a made of a polysilicon film is exposed by opening the gate electrode 107a. Subsequently, as shown in FIG. 21G, the upper portion of the gate electrode 107a made of the polysilicon film is removed by hydrofluoric acid wet etching in the element formation region 202 for forming the P-channel MOS transistor, An upper trench 118 is formed. At this time, the thickness of the gate electrode is 100 nm in the element formation region 201 for forming the N-channel MOS transistor, and the thickness of the gate electrode 107a is 50 nm in the element formation region 202 for forming the P-channel MOS transistor. is there. Next, the interlayer insulating film 117 is removed.

Next, as shown in FIG. 21 (h), as the FUSI process, a Ni film having a thickness of 60 nm and a TiN film having a thickness of 15 nm are formed thereon, and the first RTA treatment is performed at 300 ° C. for 30 seconds. I do. Further, the unreacted Ni film and TiN film are removed. For this purpose, for example, an acidic solution obtained by mixing sulfuric acid or hydrochloric acid and hydrogen peroxide solution may be used, or an alkaline solution obtained by mixing ammonium hydroxide and hydrogen peroxide solution may be used. Subsequently, a second RTA process is performed at 500 ° C. for 30 seconds, whereby the polysilicon film is formed as the NiSi film 115 for the gate electrode of the element formation region 201 for forming the N-channel MOS transistor, The gate electrode 107a in the element formation region 202 for forming the P-channel MOS transistor is converted to the Ni ₂ Si film 119 and subjected to FUSI processing.

  As described above, when the antifuse element of the present invention is formed by a process common to the MOS transistor having the FUSI gate, an unexpected situation in which the MOS transistor gate is blown during fuse programming can be avoided. This is because even when a fuse program voltage (3V to 8V) is applied, the MOS transistor gate is formed only of a low-resistance refractory metal silicide, so that it is difficult to generate heat.

  The antifuse element according to the second embodiment of the present invention can also be realized by the manufacturing method shown in the sixth embodiment. Specifically, in the step shown in FIG. 20D, the antifuse element gate electrode pattern is simply formed into a desired shape by the photoresist film 105a.

Incidentally, the anti-fuse element of the present embodiment is using NiSi film, the use of Ca 2 _Si film or Mg 2 _Si film can exert the same effect as the anti-fuse element of the present embodiment. However, when the silicide metal used for the antifuse element is different from the FUSI gate material, after the process shown in FIG. 20G, masking is performed except for the antifuse element region, and thereafter, the process shown in FIG. Do. After that, a non-silicide region can be realized by repeating the steps shown in FIGS. 20 (h) to 21 (a) and starting from FIG. 21 (d).

  As described above, the antifuse element of the present invention is useful for a method for manufacturing a semiconductor device having a silicide film.

(A) is a plan view, a cross-sectional view, and an equivalent circuit showing the antifuse element according to the first embodiment of the present invention in the initial state, and (b) is an antifuse element according to the first embodiment after conduction. It is a top view of a fuse element, a sectional view, and an equivalent circuit. (A), (b) is a figure which shows the circuit structural example of mask ROM, (c) is a figure which shows the circuit structural example using the antifuse element of this invention in mask ROM. (A) is a figure which shows the circuit structural example of FPGA, (A), (b) is a structural diagram which shows the antifuse element based on the 2nd Embodiment of this invention. (A) is a top view which shows the antifuse element which concerns on 2nd Embodiment of standard size, (b) represents the relationship between the voltage applied to a 2nd terminal part, and the electric current which flows into a fuse. It is a graph. (A) is a conventional trimming circuit diagram using three antifuses and four terminals, and (b) uses the antifuse element according to the second embodiment shown in FIG. 5 (a). A trimming circuit. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 3rd Embodiment of this invention. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 3rd Embodiment of this invention. (A)-(c) is a perspective view which shows the gate electrode for antifuse elements at the time of completion | finish of the process shown to FIG.7 (g), (h), and FIG.8 (c), respectively. (A)-(g) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and an antifuse element based on the modification of the 3rd Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and an antifuse element based on the modification of the 3rd Embodiment of this invention. (A)-(i) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 4th Embodiment of this invention. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 4th Embodiment of this invention. (A)-(c) is a perspective view which shows the gate electrode for antifuse elements at the time of completion | finish of the process shown to FIG.12 (i), FIG.13 (a), respectively. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and an antifuse element based on the modification of the 4th Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and an antifuse element based on the modification of the 4th Embodiment of this invention. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 5th Embodiment of this invention. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 5th Embodiment of this invention. (A)-(c) is a perspective view which shows the gate electrode for antifuse elements at the time of completion | finish of the process shown to FIG.17 (h), FIG.18 (a), respectively. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 6th Embodiment of this invention. (A)-(h) is sectional drawing which shows the manufacturing method of the semiconductor device which has a MOS transistor and the antifuse element of this invention based on the 6th Embodiment of this invention. (A)-(c) is a perspective view which shows the gate electrode for antifuse elements at the time of completion | finish of the process shown to FIG. 21 (a), (b), (c), respectively. It is sectional drawing which shows the conventional antifuse element in a wiring connection part.

Explanation of symbols

20 Polysilicon film
21 NiSi film
22a 1st terminal part
22b Second terminal portion
23 Fuse body
24 Antifuse connection
30, 31, 32, 33 addresses
34 Fuse at the time of shipment
35 short fuse
50 First internal wiring
52 Second internal wiring
54 Contact plug
F1, F2, F3 Antifuse
101 Element isolation region
102 Gate insulation film
103 Polysilicon film
104 Silicon oxide film
105, 105a, 105b, 105c, 105d, 105e Photoresist film
106 hard mask
107a gate electrode
107b Gate electrode for antifuse element
108 Low-concentration impurity layer
109 Silicon nitride film
110 sidewall
111 Antifuse connection
112 High concentration impurity layer
113 Ni film
114 TiN film
115 NiSi film
116 Liner nitride film
117 Interlayer insulation film
118 Trench on gate
119 Ni ₂ Si film
120 Silicon oxide film
131 Nitrogen injection layer
201, 202, 203 Element formation region

Claims (17)

A semiconductor device having an antifuse element having a polysilicon film provided on or above a semiconductor substrate and a metal silicide layer provided on the polysilicon film,
The antifuse element is
A first terminal portion and a second terminal portion both having the polysilicon film and the silicide layer;
An antifuse connecting portion provided between the first terminal portion and the second terminal portion and insulating the first terminal portion and the second terminal portion is formed in part; A fuse body having a silicon film and the silicide layer;
The semiconductor device, wherein the metal silicide layers are arranged with an interval so as to sandwich the antifuse connection portion.   2. The semiconductor device according to claim 1, wherein the metal silicide film is any one selected from a nickel silicide film, a calcium silicide film, and a magnesium silicide film.   The semiconductor device according to claim 1, further comprising a field effect transistor formed on the semiconductor substrate and having a gate electrode.   4. The semiconductor device according to claim 3, wherein the entire gate electrode is made of metal silicide.   5. The fuse body portion according to claim 1, wherein a width of the fuse body portion is narrower when viewed in plan than the first terminal portion and the second terminal portion. Semiconductor device. The fuse body is formed by arranging a plurality of antifuses having different widths so that the width gradually increases.
The semiconductor device according to claim 5, wherein each of the plurality of antifuses is provided with one antifuse connection portion. Forming a gate electrode made of a polysilicon film and an antifuse element gate electrode on a semiconductor substrate via a gate insulating film;
A step (b) of forming a first insulating film on the gate electrode, the antifuse gate electrode, and the semiconductor substrate;
A step (c) of forming a first photoresist film on a part of the first insulating film provided on the antifuse element gate electrode;
The first insulating film is etched using the first photoresist film as a mask to form sidewalls on the side surfaces of the gate electrode and the antifuse element gate electrode, and the antifuse element gate electrode (D) removing the first photoresist film after leaving the first insulating film on a part thereof;
A method of manufacturing a semiconductor device, comprising: a step (e) of forming a metal silicide layer on at least the semiconductor substrate and on the exposed portion of the gate electrode for the antifuse element after the step (d). The step (a)
A step (a1) of sequentially forming the gate insulating film, the polysilicon film, and a second insulating film on the semiconductor substrate;
And (a2) forming the gate electrode with the second insulating film left on the upper surface,
(F) forming a third insulating film on the gate electrode, the antifuse element gate electrode, and the semiconductor substrate after removing the first insulating film;
Removing the third insulating film and the second insulating film to expose the gate electrode (g);
The method of manufacturing a semiconductor device according to claim 7, further comprising a step (h) of siliciding the entire gate electrode after the step (g). Forming a gate electrode made of a polysilicon film and an antifuse element gate electrode on a semiconductor substrate via a gate insulating film;
A step (b) of forming a first insulating film on the gate electrode, the antifuse gate electrode, and the semiconductor substrate;
A step (c) of forming a first photoresist film on a part of the first insulating film provided on the antifuse element gate electrode;
The first insulating film is etched using the first photoresist film as a mask to leave the first insulating film on a part of the gate electrode for the antifuse element, and then the first photoresist film Removing step (d);
A method of manufacturing a semiconductor device, comprising: a step (e) of forming a metal silicide layer on at least the semiconductor substrate and on the exposed portion of the gate electrode for the antifuse element after the step (d). The step (a)
A step (a1) of sequentially forming the gate insulating film, the polysilicon film, and a second insulating film on the semiconductor substrate;
And (a2) forming the gate electrode with the second insulating film left on the upper surface,
(F) forming a third insulating film on the gate electrode, the antifuse element gate electrode, and the semiconductor substrate after removing the first insulating film;
Removing the third insulating film and the second insulating film to expose the gate electrode (g);
The method of manufacturing a semiconductor device according to claim 9, further comprising a step (h) of siliciding the entire gate electrode after the step (g). In the step (a), a second gate electrode made of the polysilicon film is further formed on the non-silicide region of the semiconductor substrate via the gate insulating film,
In the step (b), the first insulating film is also formed on the semiconductor substrate and the second gate electrode in the non-silicide region,
In the step (c), the first photoresist film is formed also on the first insulating film provided on the semiconductor substrate and the second gate electrode in the non-silicide region,
In the step (d), the first insulating film is also left on the semiconductor substrate and the second gate electrode in the non-silicide region,
In the step (g), upper surfaces of the semiconductor substrate and the second gate electrode in the non-silicide region are covered with the first insulating film,
11. The method of manufacturing a semiconductor device according to claim 10, wherein in the step (h), the semiconductor substrate and the second gate electrode in the non-silicide region are not silicided. Forming a gate electrode made of a polysilicon film and an antifuse element gate electrode on a semiconductor substrate via a gate insulating film;
A step (b) of forming a first photoresist film opening a part of the antifuse gate electrode;
(C) implanting nitrogen ions or oxygen ions into the upper part of the exposed portion of the gate electrode for the antifuse element using the first photoresist film as a mask;
After removing the first photoresist film, a metal silicide layer is formed at least on the semiconductor substrate and on a portion of the antifuse element gate electrode excluding a portion where the nitrogen ions or oxygen ions are implanted. And (d) a semiconductor device manufacturing method. The step (a)
A step (a1) of sequentially forming the gate insulating film, the polysilicon film, and the first insulating film on the semiconductor substrate;
And (a2) forming the gate electrode with the first insulating film left on the upper surface,
After the step (d), a step (e) of forming a second insulating film on the gate electrode, the antifuse element gate electrode, and the semiconductor substrate;
Removing the second insulating film and the first insulating film to expose the gate electrode (f);
13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step (g) of siliciding the entire gate electrode after the step (f). Forming a gate electrode made of a polysilicon film and an antifuse element gate electrode on a semiconductor substrate via a gate insulating film;
A step (b) of forming a metal silicide layer on at least the semiconductor substrate and the antifuse element gate electrode;
A step (c) of removing a part of the metal silicide layer formed on the gate electrode for the antifuse element. The step (a)
A step (a1) of sequentially forming the gate insulating film, the polysilicon film, and the first insulating film on the semiconductor substrate;
And (a2) forming the gate electrode with the first insulating film left on the upper surface,
After the step (c), a step (d) of forming a second insulating film on the gate electrode, the antifuse element gate electrode, and the semiconductor substrate;
Removing the second insulating film to expose the gate electrode (e);
15. The method of manufacturing a semiconductor device according to claim 14, further comprising a step (f) of siliciding the entire gate electrode after the step (e).   16. The method of manufacturing a semiconductor device according to claim 7, wherein the metal silicide layer is made of any one of nickel silicide, calcium silicide, and magnesium silicide.   The antifuse element gate electrodes formed in the step (a) are connected to each other between the first terminal portion and the second terminal portion, and between the first terminal portion and the second terminal portion. 17. The semiconductor according to claim 7, wherein the plurality of portions having different widths include a fuse body portion arranged so that the width gradually increases. Device manufacturing method.

Images