JP2008218461A - Manufacturing method of field effect transistor, field effect transistor, semiconductor device equipped with the field effect transistor and communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a field effect transistor and the field effect transistor which can reduce IMD (intermodulation distortion), and to provide a semiconductor device equipped with this field effect transistor and a communication apparatus. <P>SOLUTION: This field effect transistor 1 has a buried gate region 5 formed by doping an impurity in a compound semiconductor substrate 19, wherein concave portions 6L and 6R are provided on both the sides of the buried gate region 5 of the compound semiconductor substrate 19. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a field effect transistor with reduced intermodulation distortion, a field effect transistor, a semiconductor device including the field effect transistor, and a communication device.

  In a transmission / reception device such as a cellular phone, a field effect transistor (hereinafter referred to as a field effect transistor) is used as a switch for switching a high-frequency signal transmitted / received from an antenna. As such a switch, for example, a series switch and a shunt switch in which a junction field effect transistor (hereinafter referred to as JFET) using a GaAs compound semiconductor is configured in multiple stages are known.

  13 shows a circuit diagram of a communication device such as a mobile phone, and FIG. 14 shows a switch circuit 162 serving as a switch connected between the antenna 161 and the transmission / reception circuit 163 in the communication device such as a mobile phone. . As illustrated in FIGS. 13 and 14, the terminal P <b> 1 is connected to the transmission / reception circuit 163, and the terminal P <b> 2 is connected to the antenna 161. A shunt circuit 101 is configured by connecting transistors T1, T2, and T3 made of JFETs in series between the terminal P1 and GND. Further, between the terminals P1 and P2, transistors T4, T5 and T6 made of JFETs are connected in series to form a through circuit 102. The gates of the transistors T1, T2 and T3 are connected to the control terminal S1 via resistors R5 to R7, and the gates of the transistors T4, T5 and T6 are connected to the control terminal S2 via resistors R12 to R14. . Further, the connection point of each transistor is electrically connected to the terminal B1 and the terminal B2 for substrate bias through resistors R1 to R4 and resistors R8 to R11, and is configured to be stabilized by applying a constant voltage. (For example, refer to Patent Document 1).

When transmitting / receiving a signal of a specific frequency by the transmission / reception circuit 163 connected to the terminal P1, an on-voltage is applied to the control terminal S2 of the through circuit 102 to turn on the transistors T4, T5, and T6. On the other hand, an off voltage is applied to the control terminal S1 of the shunt circuit 101 to turn off the transistors T1, T2, and T3. Further, when transmission / reception is performed by another transmission / reception circuit 163 by switching the frequency band or communication mode, an off voltage is applied to the control terminal S2 of the through circuit 102 to turn off and shut off the transistors T4, T5, and T6. An ON voltage is applied to the control terminal S1 of the shunt circuit 101, and a high frequency signal input to the terminal P1 is dropped to GND. This prevents a signal input from the terminal P2 from being transmitted to the terminal P1 side.
JP 2005-323030 A

  However, the above-described switch requires low on-resistance and high off-resistance for high-frequency signals with relatively large power, and requires that the intermodulation distortion (IMD: Inter Modulation Distortion) of the transmitted signal be as low as possible. Has been. That is, the transistors constituting these switches have low on-resistance with respect to high-frequency signals with relatively large power, and signals that are transmitted / received in other bands when off and interference signals input from the antenna. It was necessary to reduce signal leakage and to reduce IMD during transmission and reception as much as possible.

  In view of the above, the present invention provides a field effect transistor manufacturing method and field effect transistor capable of reducing IMD, a semiconductor device including the field effect transistor, and a communication device.

  According to a first aspect of the present invention, there is provided a method of manufacturing a field effect transistor having a buried gate region formed by doping an impurity in a gate formation region of a compound semiconductor substrate, wherein recesses adjacent to both sides of the gate formation region are formed in the compound A recess forming step formed in the semiconductor substrate and a gate forming step of forming the buried gate region in a self-aligned manner in the gate forming region are characterized.

  According to a second aspect of the present invention, in the first aspect of the present invention, in the gate forming step, an insulating film is formed on the compound semiconductor substrate in which concave portions adjacent to both sides of the gate forming region are formed. A step of planarizing the insulating film, a step of forming a gate formation opening in the insulating film on the gate formation region, and doping the compound semiconductor substrate with impurities from the gate formation opening And a step of forming a gate region.

  According to a third aspect of the present invention, in the first aspect of the present invention, in the gate forming step, an insulating film is formed on the compound semiconductor substrate in which concave portions adjacent to both sides of the gate forming region are formed. Forming a photoresist film on the insulating film, sequentially etching the photoresist film and the insulating film to planarize the insulating film, and forming the insulating film on the gate formation region The method includes a step of forming a gate forming opening and a step of doping the compound semiconductor substrate with an impurity from the gate forming opening to form the buried gate region.

  According to a fourth aspect of the invention, in the first aspect of the invention, the recess forming step includes a step of doping the compound semiconductor substrate with the impurity to form an impurity layer, and a step of forming the gate forming region. Etching the impurity layers on both sides to form the recesses, wherein the impurity layer in the gate formation region is used as the buried gate region.

  According to a fifth aspect of the present invention, in the first aspect of the present invention, the recess forming step includes a step of forming a sacrificial layer on the compound semiconductor substrate, and selectively etching the sacrificial layer to form the sacrificial layer. A step of forming openings adjacent to both sides of the gate formation region, and a step of forming the recess by etching the compound semiconductor substrate through the opening, wherein the gate formation step includes the step of forming the gate formation region. Selectively removing the sacrificial layer other than the sacrificial gate gate sacrificial layer to form an insulating film on the compound semiconductor substrate; and planarizing the insulating film to expose the gate sacrificial layer Removing the gate sacrificial layer to form a gate formation opening; and doping the compound semiconductor substrate with an impurity through the gate formation opening to form the gate region Characterized by a step of forming.

  According to a sixth aspect of the present invention, in a field effect transistor having a buried gate region formed by doping an impurity in a compound semiconductor substrate, recesses adjacent to both sides of the buried gate region are provided in the compound semiconductor substrate. It is characterized by being.

  According to a seventh aspect of the present invention, in a semiconductor device including a field effect transistor having a buried gate region formed by doping a compound semiconductor substrate with an impurity, the field effect transistor is provided on both sides of the buried gate region. Adjacent recesses are provided in the compound semiconductor substrate.

  According to an eighth aspect of the present invention, in a communication device that transmits or receives a signal to or from another communication device, the signal is transmitted to or received from the other communication device via a communication port. A communication means for performing, and a switch disposed between the communication means and the communication port for controlling passage and blocking of the signal, the switch including a field effect transistor, The compound semiconductor substrate has a buried gate region formed by doping impurities, and the compound semiconductor substrate is provided with recesses adjacent to both sides of the buried gate region.

  According to the present invention, in the field effect transistor, the IMD can be improved by forming the recess adjacent to the buried gate region. Moreover, by etching the vicinity of the embedded gate region of the compound semiconductor substrate to form a recess, the parasitic capacitance around the gate formed between the umbrella portion of the gate electrode and the channel layer can be reduced, and the gain can be reduced. It can also contribute to improvement.

  According to the method for manufacturing a field effect transistor of the present invention, in the method for manufacturing a field effect transistor having a buried gate region formed by doping an impurity in a compound semiconductor substrate, the compound semiconductor substrate is provided on both sides of the gate formation region. Since it has a recess forming step for forming adjacent recesses and a gate forming step for forming a gate region in a self-aligned manner in the buried gate forming region, the recess is formed by etching between the gate and drain and between the gate and source. The embedded gate region can be formed in a self-aligning manner by adjoining the recesses on both sides without being restricted by the alignment accuracy by the photolithography method, and the IMD can be effectively improved.

  The field effect transistor according to the present embodiment is a field effect transistor having a buried gate region formed by doping a compound semiconductor substrate with impurities, and the compound semiconductor substrate is provided with recesses adjacent to both sides of the buried gate region. .

  Thus, the IMD can be improved by forming the recess adjacent to the buried gate region. Moreover, by etching the vicinity of the embedded gate region of the compound semiconductor substrate to form a recess, the parasitic capacitance around the gate formed between the umbrella portion of the gate electrode and the channel layer can be reduced, and the gain can be reduced. It can also contribute to improvement.

  The field effect transistor according to the present embodiment is formed in a semiconductor device as a switch, for example. By using this field effect transistor as a switch in a communication device or the like, occurrence of signal distortion due to the switch can be reduced, and malfunction of the receiving circuit can be reduced.

  The field effect transistor manufacturing method according to the present embodiment includes a step of forming a recess adjacent to both sides of a gate forming region for forming a buried gate region in the compound semiconductor substrate, and a self-alignment with the gate forming region. In particular, a manufacturing method having a gate forming step for forming the buried gate region is preferable.

  According to this manufacturing method, since the buried gate region having the concave portions adjacent to both sides is formed in a self-aligned manner, the concave portion is formed adjacent to the buried gate region without being restricted by the alignment accuracy by the photolithography method. Can effectively improve the IMD. In addition, by etching the compound semiconductor substrate in the vicinity of the buried gate region to provide a recess, the parasitic capacitance around the gate formed between the umbrella portion of the gate electrode and the channel layer can be reduced, and the gain is improved. Can also contribute. Further, since the buried gate region is positioned by the self-alignment process so that both sides are adjacent to the concave portion, it is possible to prevent a characteristic defect caused by misalignment and improve the yield.

  Here, specifically, the following first to fourth manufacturing methods are more preferable as the manufacturing method having the recess forming step and the gate forming step.

  In the first manufacturing method, the gate forming step includes a step of forming an insulating film on the compound semiconductor substrate in which concave portions adjacent to both sides of the gate forming region are formed, and the insulating film is flattened. A manufacturing method comprising: forming a gate forming opening in the insulating film on the gate forming region; and doping the compound semiconductor substrate with an impurity from the gate forming opening to form the buried gate region. It is.

  In the second manufacturing method, the gate forming step includes the steps of forming an insulating film on the compound semiconductor substrate on which concave portions adjacent to both sides of the gate forming region are formed, and a photoresist on the insulating film. Forming a film, sequentially etching the photoresist film and the insulating film to planarize the insulating film, forming a gate formation opening in the insulating film on the gate formation region, and the gate Forming a buried gate region by doping impurities into the compound semiconductor substrate from a formation opening.

  In the third manufacturing method, the recess forming step includes a step of doping the compound semiconductor substrate with the impurity to form an impurity layer, and etching the impurity layer on both sides of the gate forming region to form the recess. And forming the impurity layer in the gate formation region as the buried gate region.

  In the fourth manufacturing method, the recess forming step includes a step of forming a sacrificial layer on the compound semiconductor substrate, and a step of selectively etching the sacrificial layer to form openings adjacent to both sides of the gate forming region. And the step of forming the recess by etching the compound semiconductor substrate through the opening, and the gate formation step is other than the gate sacrificial layer which is the sacrificial layer on the gate formation region Selectively removing the sacrificial layer, forming an insulating film on the compound semiconductor substrate, planarizing the insulating film to expose the gate sacrificial layer, and removing the gate sacrificial layer Forming a gate forming opening; and doping the compound semiconductor substrate with an impurity through the gate forming opening to form the buried gate region. It is a method.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, the field effect transistor according to the present embodiment will be described in detail. FIG. 1 is a configuration diagram showing a field effect transistor according to the present embodiment.

  The field effect transistor 1 according to the present embodiment includes a buried gate region 5 in which recesses 6L and 6R are adjacent to a compound semiconductor substrate 19 in which a channel layer 21 epitaxially grown on a semi-insulating substrate 20 and a compound semiconductor substrate 22 are stacked. Is provided.

  For example, the semi-insulating substrate 20 can be formed of a GaAs layer, the channel layer 21 can be formed of an InGaAs layer, and the compound semiconductor substrate 22 can be formed of an AlGaAs layer. The channel layer is formed of a layer made of GaAs, InGaAs, AlGaAs, InGaP, or the like by epitaxial growth.

  FIG. 2A is a characteristic diagram in which when the concave portions are provided on both sides of the buried gate region, the vertical axis indicates the second-order intermodulation distortion and the horizontal axis indicates the gate potential. Note that FIG. 2B is a configuration diagram of the field-effect transistor according to this embodiment. The interval ET is the distance from the end of the buried gate region to the end of the recess. Line a represents ET = 0.05 μm, line b represents ET = 0.1 μm, and line c represents the case without a recess (conventional field effect transistor structure).

  In the field effect transistor according to the present embodiment, the concave portions adjacent to both sides of the buried gate region are provided, but compared with the characteristics in the case where the concave portion having the conventional structure is not provided (line c in FIG. 2A), Better characteristics are obtained when the recesses are further provided adjacent to the buried gate region (lines a and b in FIG. 2A). The shorter the interval ET, the better the characteristics. The concave portions adjacent to both sides of the buried gate region is the optimum positional relationship for improving the IMD, and means the shortest distance ET interval that can be created by the self-alignment process.

  According to the field effect transistor 1 according to the present embodiment, the embedded gate region 5 adjacent to the recesses 6L and 6R (recess etching regions) is formed in a self-aligned manner without being restricted by alignment accuracy by a photolithography method. And can effectively improve IMD. Further, by etching the vicinity of the embedded gate region 5 of the compound semiconductor substrate 22 to form the recesses 6L and 6R, the parasitic capacitance around the gate formed between the umbrella portion of the gate electrode 2 and the channel layer 21 is also increased. This can be reduced and can contribute to an improvement in gain.

  Next, a method for manufacturing the field effect transistor 1 will be specifically described with reference to the drawings.

  The method of manufacturing the field effect transistor 1 includes a step of forming a recess in the compound semiconductor substrate 19 adjacent to both sides of a gate formation region serving as a buried gate region, and the buried gate region in a self-aligned manner with the gate formation region. Forming a gate. As a manufacturing method which has this recessed part formation process and a gate formation process, there exist the 1st-4th manufacturing method shown below, for example.

  First, the first manufacturing method will be described. 3 to 6 are process diagrams of the first manufacturing method of the field effect transistor according to the present embodiment.

  First, as shown in FIG. 3A, a compound semiconductor substrate 19 includes a channel layer 21 that is an epitaxial layer epitaxially grown on a semi-insulating substrate 20, a compound semiconductor substrate 22 that forms a field effect transistor 1, and a sacrificial layer. The layers are stacked in the order of 23. The epi layer is formed so as to obtain a desired device structure. For example, the semi-insulating substrate 20 can be formed with a GaAs layer, the channel layer with an InGaAs layer, the compound semiconductor substrate 22 with an AlGaAs layer, and the sacrificial layer 23 with a GaAs layer. The AlGaAs layer of the compound semiconductor substrate 22 is formed with a thickness of about 150 nm, and the GaAs layer of the sacrificial layer 23 is formed with a thickness of about 300 nm. The channel layer is formed of a layer made of GaAs, InGaAs, AlGaAs, InGaP, or the like by epitaxial growth.

  Next, as shown in FIG. 3B, a photoresist 24 is applied on the sacrificial layer 23, and a recess adjacent to the gate formation region to be a buried gate region is formed in the photoresist 24 by photolithography. A resist mask 24a having openings 10L and 10R opened on the recess etching region is formed.

  Next, as shown in FIG. 3C, using the resist mask 24a, only the sacrificial layer 23 is selectively etched by wet etching such as citric acid or dry etching such as RIE (Reactive Ion Etching). To do. Of the selectively formed sacrificial layer 23, the sacrificial layer 23 on the gate formation region is referred to as a gate sacrificial layer 11.

  Next, as shown in FIG. 3D, the compound semiconductor substrate 22 under the sacrificial layer 23 is selectively etched by dry etching using the etching opening of the sacrificial layer 23 as a mask to form the recesses 6L and 6R. Form. For example, the depth of the recess is about 100 nm.

  Next, as shown in FIG. 3E, the resist mask 24a is removed by ashing or the like.

  Next, as shown in FIG. 3F, a photoresist mask 24 is applied by photolithography to cover only the sacrificial layer remaining between the recesses 6L and 6R, that is, the gate sacrificial layer 11. 24b is formed.

  Next, as shown in FIG. 4G, the gate sacrificial layer 11 is left using the resist mask 24b as a mask, and the remaining sacrificial layer 23 is selectively removed by wet or dry etching.

  Next, as shown in FIG. 4H, the resist mask 24b is removed by wet or dry etching. At this time, the gate sacrificial layer 11 is left on the compound semiconductor substrate 22 between the recesses 6L and 6R.

  Next, as shown in FIG. 4I, an interlayer insulating film 25 is formed by CVD (Chemical Vapor Deposition) or the like so as to be deposited on the compound semiconductor substrate and the gate sacrificial layer and the two recesses. The interlayer insulating film 25 has a concavo-convex shape in which the two concave portions 6L and 6R and the protruding gate sacrificial layer 11 are transferred. For example, the interlayer insulating film 25 is formed of SiN or the like with a film thickness of about 300 nm.

  Next, as shown in FIG. 4J, the concavo-convex interlayer insulating film 25 is ground and planarized by CMP (Chemical Mechanical Polishing) or the like so that the gate sacrificial layer 11 is exposed. For example, the thickness of the interlayer insulating film 25 after polishing and planarization is about 250 nm.

  Next, as shown in FIG. 4K, the gate sacrificial layer 11 is selectively removed by wet etching or dry etching. A gate formation opening 13 is formed at a position where the gate sacrificial layer is removed. That is, the gate forming opening 13 is formed in the middle between the two recesses 6L and 6R.

  Next, as shown in FIG. 4L, the buried gate region 5 is formed in a self-aligned manner by diffusing impurities into the compound semiconductor substrate 22 through the gate formation opening 13 by, for example, diffusion or ion plantation technology. For example, P-type atoms such as Zn are diffused into the compound semiconductor substrate 22 through the gate formation opening 13 to form the buried gate region 5.

  Next, as shown in FIG. 5M, a metal film 26 is formed on the entire surface of the interlayer insulating film 25 and the buried gate region 5 by vapor deposition or sputtering. For example, the metal film 26 is formed of Ti / Pt / Au or the like.

  Next, as shown in FIG. 5N, a photoresist 24 is applied and patterned by photolithography, and a resist mask 24c is selectively formed in a portion where a gate electrode is to be formed.

  Next, as shown in FIG. 5O, the gate electrode 2 is formed by selectively etching the metal film 26 using ion milling, dry etching, or the like using the resist mask 24c as a mask. The gate electrode 2 serves as an extraction electrode for the buried gate region, and has an umbrella shape protruding on the interlayer insulating film 25.

  Next, as shown in FIG. 5P, the resist mask 24c is selectively removed by wet etching or dry etching.

  Next, as shown in FIG. 5Q, an interlayer insulating film 27 is further formed on the entire surface of the interlayer insulating film 25 and the gate electrode 2 by CVD or the like. For example, the interlayer insulating film 27 is made of SiN, SiO2, or the like with a thickness of about 100 nm.

  Next, as shown in FIG. 5R, a photoresist 24 is applied and patterned by photolithography to form a resist mask 24d having openings 14S and 14D in portions where source and drain electrodes are to be formed. Form.

  Next, as shown in FIG. 6S, using the resist mask 24d as a mask, the interlayer insulating film 27 and the interlayer insulating film 25 are selectively etched through the openings 14S and 14D by wet etching or dry etching. By removing, the openings 14S and 14D to be the source electrode and the drain electrode are formed.

  Next, as shown in FIG. 6T, a metal film 28 is formed on the resist mask 24d and through the openings 14S and 14D by sputtering, vapor deposition, or the like while leaving the resist mask 24d. For example, the metal film is made of AuGe / Ni or the like.

  Next, as shown in FIG. 6U, the source mask 3 and the drain electrode 4 are formed by removing the resist mask 24d and the metal film 28 formed on the resist mask 24d by lift-off. The field effect transistor 1 according to the present embodiment including the recesses 6L and 6R adjacent to the buried gate region 5 is obtained.

FIG. 7 is a configuration diagram in which the source electrode and the drain electrode of the field effect transistor according to the present embodiment in FIG. 6 (U) are ohmic electrodes.
When the field effect transistor 1 according to the present embodiment shown in FIG. 6 (U) is heat-treated at about 400 degrees, the metal film of the source electrode 3 ′ and the metal film of the drain electrode 4 ′ are alloyed with the compound semiconductor substrate 22. Into an ohmic electrode. A field effect transistor 41 according to another embodiment of the present invention having an ohmic electrode is obtained.

  Next, the second manufacturing method will be described. FIG. 8 is a process diagram showing a second manufacturing method of the field effect transistor according to the present embodiment. FIG. 8 is described using the same reference numerals as those in FIGS.

  As shown in FIG. 8A, a channel layer 21 and a compound semiconductor substrate 22 are sequentially stacked on a semi-insulating substrate 20 to form a compound semiconductor substrate 19. The compound semiconductor substrate 22 is selectively etched by dry etching using photolithography technology to form the recesses 6L and 6R. For example, the depth of the recess is about 100 nm. The channel layer 21 is formed so as to obtain a desired device structure. For example, the semi-insulating substrate 20 can be formed with a GaAs layer, the channel layer with an InGaAs layer, and the compound semiconductor substrate 22 with an AlGaAs layer. An AlGaAs layer of the compound semiconductor substrate 22 is formed with a film thickness of about 150 nm. The channel layer is formed of a layer made of GaAs, InGaAs, AlGaAs, InGaP, or the like by epitaxial growth.

  Next, as shown in FIG. 8B, an insulating film 25a is formed on the compound semiconductor substrate 22 by a CVD (Chemical Vapor Deposition) method or the like. For example, the insulating film 25a is formed to have a film thickness in which the recess is embedded with SiN, SiO2, or the like. For example, the insulating film 25a is formed of SiN or the like with a film thickness of about 300 nm.

  Next, as shown in FIG. 8C, the uneven shape of the insulating film 25a is ground and planarized by a CMP (Chemical Mechanical Polishing) method or the like. At this time, polishing and planarization are performed to such an extent that the gate formation region that becomes the buried gate region is not exposed.

  Next, as shown in FIG. 8D, a photoresist 24 is applied onto the insulating film 25a by photolithography and etching techniques, and then patterned to form an upper insulating film 25a serving as a gate formation region. A gate formation opening 13 is formed in the resist mask 24e. That is, in the insulating film 25a, the gate formation opening 13 is formed in the middle between the recesses 6L and 6R.

  Next, as shown in FIG. 8E, the resist mask 24e is removed by an ashing technique. Impurities are diffused from the gate formation opening 13 into the compound semiconductor substrate 22 by ion plantation to form the buried gate region 5 in a self-aligning manner. At this time, portions other than the formation of the buried gate region 5 are covered with the insulating film 25a. For example, p-type atoms such as Zn are diffused into the compound semiconductor substrate 22 through the gate formation opening 13 to form the buried gate region 5. Although not shown, an interlayer insulating film 25 is further formed by CVD (Chemical Vapor Deposition) or the like, and then an opening on the buried gate region is formed by photolithography and etching techniques. Next, a metal film is formed on the entire surface of the interlayer insulating film 25 and the buried gate region 5 by vapor deposition or sputtering. For example, Ti / Pt / Au or the like is formed as the metal film. The gate electrode 2 is formed by selectively etching the metal film using ion milling or dry etching or the like by photolithography and etching techniques. An interlayer insulating film 27 is further formed on the entire surface of the interlayer insulating film 25 and the gate electrode 2 by CVD or the like. For example, the interlayer insulating film 27 is made of SiN, SiO 2 or the like with a required film thickness. Photoresist 24 is applied by photolithography and patterned to form a resist mask provided with openings in portions where source and drain electrodes are to be formed. Using the resist mask as a mask, the interlayer insulating film 27 and the interlayer insulating film 25 are selectively removed by etching through the openings by wet etching or dry etching, thereby forming openings serving as source and drain electrodes. A metal film is formed on the resist mask and through the opening by sputtering, vapor deposition or the like while leaving the resist mask. For example, the metal film is made of AuGe / Ni or the like. Further, the metal film formed on the resist mask is removed by lift-off.

  Next, as illustrated in FIG. 8F, the source electrode 3, the drain electrode 4, and the umbrella-shaped gate electrode 2 are formed over the compound semiconductor substrate 22. The field effect transistor 1 according to the present embodiment including the recesses 6L and 6R adjacent to the buried gate region 5 is obtained.

  Next, the third manufacturing method will be described. FIG. 9 is a process diagram showing a third manufacturing method of the field effect transistor according to the present embodiment. FIG. 9 is described using the same reference numerals as in FIGS.

  As shown in FIG. 9A, a channel layer 21 and a compound semiconductor substrate 22 are sequentially stacked on a semi-insulating substrate 20 to form a compound semiconductor substrate 19. By photolithography, the compound semiconductor substrate 22 is selectively etched by dry etching to form the recesses 6L and 6R. For example, the depth of the recess is about 100 nm. The channel layer 21 is formed so as to obtain a desired device structure. For example, the semi-insulating substrate 20 can be formed with a GaAs layer, the channel layer with an InGaAs layer, and the compound semiconductor substrate 22 with an AlGaAs layer. An AlGaAs layer of the compound semiconductor substrate 22 is formed with a film thickness of about 150 nm. The channel layer is formed of a layer made of GaAs, InGaAs, AlGaAs, InGaP, or the like by epitaxial growth.

  Next, as shown in FIG. 9B, an insulating film 25a is formed on the compound semiconductor substrate 22 by a CVD (Chemical Vapor Deposition) method or the like. The insulating film 25a has a concavo-convex shape in which the two concave portions 6L and 6R are transferred. A photoresist 24 is applied by photolithography to form a resist mask 24f. For example, the insulating film 25a is formed to have a film thickness in which the recess is embedded with SiN, SiO2, or the like. For example, the insulating film 25a is formed of SiN or the like with a film thickness of about 300 nm. The photoresist 24 is formed with a low viscosity. For example, the viscosity of the photoresist is 20 cps or less. At this time, since the viscosity of the photoresist 24 is low, the photoresist 24 is formed thick in a low height region (a region on the concave portion) and thin in a high height region.

  Next, as shown in FIG. 9C, the insulating film 25a is ground and flattened by dry etching with a selection ratio of, for example, 1: 1 between the resist mask 24f and the insulating film 25a. At this time, grinding and flattening are performed to such an extent that the gate forming region that becomes the buried gate region is not exposed. The convex portions forming the concave portions 6L and 6R and the buried gate region 5 are buried with the insulating film 25a.

  Next, as shown in FIG. 9D, the photoresist 24 is applied onto the insulating film 25a by photolithography and etching techniques, and then patterned to form the insulating film 25a on the gate formation region. A gate formation opening 13 is formed in the resist mask 24g. That is, in the insulating film 25a, the gate formation opening 13 is formed in the middle between the recesses 6L and 6R.

  Next, as shown in FIG. 9E, the resist mask 24g is removed by an ashing technique. Impurities are diffused from the gate formation opening 13 into the compound semiconductor substrate 22 by ion plantation to form the buried gate region 5 in a self-aligning manner. At this time, portions other than the formation of the buried gate region 5 are covered with the insulating film 25a. For example, p-type atoms such as Zn are diffused into the compound semiconductor substrate 22 through the gate formation opening 13 to form the buried gate region 5. Although not shown, an interlayer insulating film 25 is further formed by CVD (Chemical Vapor Deposition) or the like, and then an opening on the buried gate region is formed by photolithography and etching techniques. Next, a metal film is formed on the entire surface of the interlayer insulating film 25 and the buried gate region 5 by vapor deposition or sputtering. For example, Ti / Pt / Au or the like is formed as the metal film. The gate electrode 2 is formed by selectively etching the metal film using ion milling or dry etching or the like by photolithography and etching techniques. An interlayer insulating film 27 is further formed on the entire surface of the interlayer insulating film 25 and the gate electrode 2 by CVD or the like. For example, the interlayer insulating film 27 is made of SiN, SiO 2 or the like with a required film thickness. Photoresist 24 is applied by photolithography and patterned to form a resist mask provided with openings in portions where source and drain electrodes are to be formed. By using the resist mask as a mask, the interlayer insulating film 27 and the interlayer insulating film 25 are selectively etched and removed through the openings by wet etching or dry etching, thereby forming each opening to be a source electrode and a drain electrode. To do. A metal film is formed on the resist mask and through the opening by sputtering, vapor deposition or the like while leaving the resist mask. For example, the metal film is made of AuGe / Ni or the like. Further, the metal film formed on the resist mask is removed by lift-off.

  Next, as illustrated in FIG. 9F, the source electrode 3, the drain electrode 4, and the umbrella-shaped gate electrode 2 are formed over the compound semiconductor substrate 22. The field effect transistor 1 according to the present embodiment including the recesses 6L and 6R adjacent to the buried gate region 5 is obtained.

  Next, a fourth manufacturing method will be described. FIG. 10 is a process diagram of the fourth manufacturing method of the field effect transistor according to the present embodiment. FIG. 10 is described using the same reference numerals as those in FIGS.

  First, the channel semiconductor layer 21 and the compound semiconductor substrate 22 are sequentially stacked on the semi-insulating substrate 20 to form the compound semiconductor substrate 19. As shown in FIG. 10A, a gate buried region is formed in the compound semiconductor substrate 22. Impurity layers 29 are formed by ion implantation or thermal diffusion of impurities.

  As shown in FIG. 10B, after a photoresist 24 is applied and patterned by photolithography and etching, the photoresist 24 opens on the recess adjacent to the gate formation region to be a buried gate region. The resist mask 24h having an opening is formed. By etching the impurity layer 29 through the opening, two recesses 6L and 6R are formed. The recesses 6L and 6R are formed adjacent to the buried gate region 5. The depths of the recesses 6L and 6R are such that there is no impurity layer. For example, the depth is such that the concentration of the impurity layer is 1E-15 cm −3 or less.

  As shown in FIG. 10C, a resist mask 24i is formed by patterning so as to cover the buried gate region 5 by photolithography and etching techniques, and then formed on the compound semiconductor substrate 19 by ion implantation technique. The source region 33 and the drain region 34 are formed at a concentration higher than that of the impurity layer 29.

  As shown in FIG. 10D, after not shown, after removing the resist mask 24i, an interlayer insulating film 25 is formed by a CVD (Chemical Vapor Deposition) method or the like, and is ground by a CMP (Chemical Mechanical Polishing) method or the like. -Flatten. By applying a photoresist 24 on the interlayer insulating film 25 by a photoresist method and an etching technique and then patterning it, a gate forming opening is formed in the interlayer insulating film 25 and the resist mask on the gate forming region. . The resist mask is removed by ashing technology. Further, a metal film is formed on the entire surface of the interlayer insulating film 25 and the buried gate region 5 by vapor deposition or sputtering. For example, Ti / Pt / Au or the like is formed as the metal film. The gate electrode 2 is formed by selectively etching the metal film using ion milling or dry etching or the like by photolithography and etching techniques. An interlayer insulating film 27 is further formed on the entire surface of the interlayer insulating film 25 and the gate electrode 2 by CVD or the like. For example, the interlayer insulating film is made of SiN, SiO 2 or the like with a required film thickness. Photoresist 24 is applied by photolithography and patterned to form a resist mask provided with openings in portions where source and drain electrodes are to be formed. By using the resist mask as a mask, the interlayer insulating film 27 and the interlayer insulating film 25 are selectively etched and removed through the openings by wet etching or dry etching, thereby forming each opening to be a source electrode and a drain electrode. To do. A metal film is formed on the resist mask and through the opening by sputtering, vapor deposition or the like while leaving the resist mask. For example, the metal film is made of AuGe / Ni or the like. Further, the metal film formed on the resist mask is removed by lift-off. The field effect transistor 51 according to the present embodiment including the recesses 6L and 6R adjacent to the buried gate region 5 is obtained.

  Examples of the field effect transistor include a high electron mobility transistor (HEMT) or a junction high electron mobility transistor (JHEMT).

  Next, a semiconductor switch circuit (corresponding to an example of a switch) including a field effect transistor FET and a plurality of semiconductor switch circuits (corresponding to an example of a semiconductor device) will be described. An example of use of a semiconductor switch circuit for conducting and blocking a high-frequency signal will be described with reference to FIG. FIG. 11 is a block diagram of a transmission / reception part of a mobile phone (corresponding to an example of a communication device) capable of switching a plurality of radio wave bands used for communication.

  The mobile phone shown in FIG. 11 includes semiconductor switch circuits SW1 to SW3 in a portion for switching between a radio wave band used in GSM (Global System for Mobile Communications) and a radio wave band of WCDMA (Wideband Code Division Multiple Access). ing. The semiconductor switch circuits SW <b> 1 to SW <b> 3 are provided between an antenna 40 (one form of communication port) that transmits and receives radio waves and a duplexer 42.

  When transmitting and receiving information using a WCDMA frequency band in a cellular phone, the semiconductor switch circuit SW1 is set in a conducting state, and the antenna 40 and the duplexer 42 are conducted.

  When the semiconductor switch circuit SW1 is set to a conductive state, for example, the gate voltage (Vg10) of the semiconductor switch circuit 48a is set to low, and the high-impedance is established between the drain D of the FET1 and the source S of the FET4 of the semiconductor switch circuit 48a. At the same time, the gate voltage (Vg11) of the semiconductor switch circuit 49a is set to high so that the drain D-source S of the semiconductor switch circuit 49a is in a low impedance state, and the antenna 40 and the duplexer 42 are made conductive. .

  On the other hand, the unused semiconductor switch circuits SW2 and SW3 in the GSM frequency band are set in a cut-off state. For example, when the semiconductor switch circuit SW2 is set to the cut-off state, the gate voltage (Vg20) of the semiconductor switch circuit 48b is set to high so that the drain D-source S of the semiconductor switch circuit 48b is in a low impedance state. Then, the gate voltage (Vg21) of the semiconductor switch circuit 49b is set to be low so that the drain D and the source S of the semiconductor switch circuit 49b are in a high impedance state, the GSM circuit is disconnected from the antenna 40, and the GSM duplexer The input signal is interrupted by shorting the input terminal (not shown) to ground. Similarly, the semiconductor switch circuit SW3 is also set to a cut-off state.

  The duplexer 42 transmits a WCDMA transmission signal Tx with a frequency of 1.95 GHz output from the power amplifier 46 (one form of communication means for transmission) to the antenna 40, and receives a 2.14 GHz WCDMA reception signal received from the antenna 40. It has a function of transmitting Rx to the low noise amplifier 44 (one form of communication means for reception), and for example, a signal is branched for each frequency using a trap filter. In the embodiment shown in FIG. 11, the antenna 40 is used as a communication port for transmitting and receiving signals. However, the communication port is not limited to the antenna 40. A communication port can be used.

  FIG. 12 shows a configuration example of the semiconductor switch circuit SW1 corresponding to the semiconductor device according to the embodiment of the present invention. The RF0 terminal of the semiconductor switch circuit SW1 shown in FIG. 12 is connected to the antenna 40 as shown in FIG. The RF1 terminal is connected to the duplexer 42.

  In the example shown in FIG. 12, a semiconductor switch circuit 49a that functions as a through FET and a semiconductor that functions as a shunt FET in order to cut off a signal having a large amplitude and reduce the capacitance existing between the drain D and the source S. The switch circuit 48a is composed of FETs connected in a plurality of stages (four stages) in series. Further, the gates G of the FET5 to FET8 constituting the semiconductor switch circuit 49a are connected in common via a resistor Rg to constitute the gate of the semiconductor switch circuit 49a. Further, the gates G of the FET1 to FET4 constituting the semiconductor switch circuit 48a are connected in common via a resistor Rg to constitute the gate of the semiconductor switch circuit 48a.

  According to the communication device according to the present embodiment, in a communication device that transmits or receives a signal to or from another communication device (a mobile phone as one form), a communication unit that transmits or receives a signal, and the other communication device A communication port (antenna as one form) for transmitting or receiving a signal, and a switch (semiconductor switch circuit as one form) that is disposed between the communication means and the communication port and controls passage and blocking of the signal; The switch has a plurality of field effect transistors, the field effect transistor has a buried gate region formed by doping impurities into the compound semiconductor substrate 19, and the buried gate region on the compound semiconductor substrate 19 By providing concavities adjacent to both sides, the concavities can be formed on both sides without being restricted by the accuracy of alignment by photolithography. It can improve IMD can be formed in a self-aligned manner buried gate region in contact. Moreover, by etching the vicinity of the embedded gate region of the compound semiconductor substrate to form a recess, the parasitic capacitance around the gate formed between the umbrella portion of the gate electrode and the channel layer can be reduced, and the gain can be reduced. It can also contribute to improvement. Therefore, a high-frequency signal with less distortion can be transmitted. Further, by reducing the occurrence of signal distortion due to the switch, malfunctions of the transmission and reception circuits can be reduced.

It is a figure which shows the fundamental structure of the field effect transistor in embodiment of this invention. (A) It is a figure which shows the characteristic of electric power-gate potential. (B) It is a figure which shows the structure of the principal part of a field effect transistor. It is FIG. (The 1) which shows the 1st manufacturing process of the field effect transistor in embodiment of this invention. It is FIG. (2) which shows the 1st manufacturing process of the field effect transistor in embodiment of this invention. It is FIG. (The 3) which shows the 1st manufacturing process of the field effect transistor in embodiment of this invention. It is FIG. (The 4) which shows the 1st manufacturing process of the field effect transistor in embodiment of this invention. It is a figure which shows the fundamental structure of the field effect transistor in embodiment of this invention. It is a figure which shows the 2nd manufacturing process of the field effect transistor in embodiment of this invention. It is a figure which shows the 3rd manufacturing process of the field effect transistor in embodiment of this invention. It is a figure which shows the 4th manufacturing process of the field effect transistor in embodiment of this invention. It is a figure which shows the basic structural circuit of the communication apparatus in embodiment of this invention. It is a figure which shows the circuit connection of the semiconductor device in embodiment of this invention. It is a figure which shows the basic composition of the conventional communication apparatus. It is a figure which shows the structure of the conventional semiconductor switch circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Field effect transistor 2 Gate electrode 3 Source electrode 4 Drain electrode 5 Embedded gate electrode 6L, 6R Recess 10L, 10R Opening 11 Gate sacrificial layer 13 Gate formation opening 19 Compound semiconductor substrate 20 Semi-insulating substrate 21 Channel layer 22 Compound semiconductor substrate 24 Photoresist 24a, 24b, 24c, 24d, 24f, 24g, 24h Resist mask 25 Interlayer insulating film 27 Interlayer insulating film 28 Metal film 29 Impurity layer

Claims (8)

In a method of manufacturing a field effect transistor having a buried gate region formed by doping an impurity in a gate formation region of a compound semiconductor substrate,
Forming a recess in the compound semiconductor substrate adjacent to both sides of the gate forming region; and
A method of manufacturing a field effect transistor, comprising: a gate forming step of forming the buried gate region in a self-aligned manner in the gate forming region. The gate forming step includes
Forming an insulating film on the compound semiconductor substrate in which concave portions adjacent to both sides of the gate forming region are formed;
Planarizing the insulating film;
Forming a gate formation opening in the insulating film on the gate formation region;
The method of manufacturing a field effect transistor according to claim 1, further comprising: doping the compound semiconductor substrate with an impurity from the gate formation opening to form the buried gate region. The gate forming step includes
Forming an insulating film on the compound semiconductor substrate in which concave portions adjacent to both sides of the gate forming region are formed;
Forming a photoresist film on the insulating film, and sequentially etching the photoresist film and the insulating film to planarize the insulating film;
Forming a gate formation opening in the insulating film on the gate formation region;
The method of manufacturing a field effect transistor according to claim 1, further comprising: doping the compound semiconductor substrate with an impurity from the gate formation opening to form the buried gate region. The recess forming step includes
A step of doping the compound semiconductor substrate with the impurity to form an impurity layer;
Etching the impurity layer on both sides of the gate formation region to form the recess,
The method of manufacturing a field effect transistor according to claim 1, wherein the impurity layer in the gate formation region is used as the buried gate region. The recess forming step includes
Forming a sacrificial layer on the compound semiconductor substrate;
Selectively etching the sacrificial layer to form adjacent openings on both sides of the gate formation region;
Forming the recess by etching the compound semiconductor substrate through the opening,
The gate forming step includes
Selectively removing the sacrificial layer other than the gate sacrificial layer, which is the sacrificial layer on the gate formation region, and forming an insulating film on the compound semiconductor substrate;
Planarizing the insulating film to expose the gate sacrificial layer;
Removing the gate sacrificial layer to form a gate formation opening;
The method of manufacturing a field effect transistor according to claim 1, further comprising: doping the compound semiconductor substrate with an impurity through the gate formation opening to form the buried gate region. In a field effect transistor having a buried gate region formed by doping impurities in a compound semiconductor substrate,
A field effect transistor, wherein the compound semiconductor substrate is provided with recesses adjacent to both sides of the buried gate region. In a semiconductor device comprising a field effect transistor having a buried gate region formed by doping an impurity in a compound semiconductor substrate,
The field effect transistor is
Recesses adjacent to both sides of the buried gate region are provided in the compound semiconductor substrate. In a communication device that transmits or receives signals with other communication devices,
Communication means for transmitting or receiving the signal to the other communication device via a communication port;
A switch that is disposed between the communication means and the communication port and controls passage and blocking of the signal;
The switch has a field effect transistor;
The field effect transistor is
A communication device having a buried gate region formed by doping an impurity in a compound semiconductor substrate, and provided with concave portions adjacent to both sides of the buried gate region in the compound semiconductor substrate.

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