JP2008211114A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a polishing process and have a fine gate space pattern on an element separating area. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 100, an element separating dielectric film 101, a first and second electrodes 107a, 107b, a gate dielectric film pattern 104, and a side-wall dielectric film 108. The element separating dielectric film 101 is located on the semiconductor substrate 100, and the first and second electrodes 107a, 107b are located on the element separating dielectric film 101 so as to sandwich the gate dielectric film pattern 104. The side-wall dielectric film 108 is located on a portion except the portion adjacent to the gate dielectric film pattern 104 among the side-walls of the first and second electrodes 107a, 107b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly characterized in a method for forming a gate electrode pattern.

  In recent semiconductor devices, an active element such as a MOS (Metal Oxide Semiconductor) transistor and a passive element such as a resistor are formed on a common semiconductor substrate to form an LSI (Large Scale Integrated-circuit). High integration of the entire semiconductor device is underway. For this reason, it is necessary to form a line pattern or a space pattern with a fine dimension in accordance with the purpose of the gate electrode constituting the element region. On the active region for forming the active element, it is necessary to form a region to be a source / drain region of the MOS transistor between the gate electrodes, and to make a contact plug electrically contact with the source / drain region. For this reason, the dimension between the gate electrodes is limited by the dimension of the contact plug and the dimension of the side wall insulating film of the gate electrode, and the integration is not performed so as to be limited by the miniaturization limit of the gate space pattern. On the other hand, the gate electrode on the element isolation insulating film does not require a contact plug or the like to be formed between the gate electrodes, so that a fine space pattern may be required.

FIG. 7 shows a cross-sectional view of a semiconductor device when a semiconductor device is formed on the element isolation insulating film using a conventional gate electrode formation process. As shown in FIG. 7, such a conventional semiconductor device includes an element isolation insulating film 601 formed on a semiconductor substrate 600, a gate electrode 602 and a gate electrode 603, and a gate electrode 602 and a gate electrode 603, respectively. The side wall insulating film 604 formed on the side wall of the semiconductor substrate 600 and the interlayer insulating film 605 covering the entire surface of the semiconductor substrate 600 are formed. Here, the gate electrode 602 and the gate electrode 603 are formed separately from each other by etching the gate electrode material using a photoresist as a mask.
JP 2002-305251 A

  However, the prior art described above has the following problems.

  In order to highly integrate a semiconductor device (semiconductor element), it is desirable to make the gate separation width a between the gate electrode 602 and the gate electrode 603 as small as possible. Here, the gate separation width a is limited by the resolution limit of exposure for the space pattern of the photoresist. In the photoresist, the space pattern has a larger resolution limit dimension than the line pattern, so that it is difficult to form a fine pattern.

  Also, in recent years, in order to reduce the line pattern of the gate electrode constituting the MOS transistor on the active region, the gate electrode material is anisotropically etched after the photoresist mask pattern is isotropically etched (shrink). Etching) is used. For this reason, the gate isolation width a is further larger than the resolution limit of the photoresist space pattern. As a result, it is more difficult to form a fine gate space pattern than to form a fine gate line pattern.

  The above problem becomes more serious when a fine gate line pattern is separated from another gate pattern.

  As a specific example that requires fine gate line pattern separation, there is a case where a plurality of MOS transistors are arranged in parallel to each other. FIG. 8A shows a top view of two MOS transistors arranged in parallel with each other. In the figure, the side wall insulating film of the gate electrode is omitted in order to prevent the drawing from being complicated.

The gate electrodes 701 and 702 are provided on the active regions 700 and 700, respectively, and are separated from each other on the element isolation insulating film 703. Each of the gate electrodes 701 and 702 has resist patterns 704 and 705 (these resist patterns 704 and 705 are removed after the gate electrode pattern is formed, and are indicated by broken lines in FIG. 8A). It is used as a mask and is formed by shrink etching. Here, since the resist patterns 704 and 705 are fine line patterns, their end portions are formed while the corners are rounded and receded during photolithography. Specifically, as shown in FIG. 8B, when the rounded corner 706 of the resist overlaps the reticle pattern 708, the end portion of the resist pattern (fine line pattern) 707 is formed as shown in FIG. Retreat from reticle pattern 708. Since the resist patterns 704 and 705 are formed in this way, the resist separation width b ₀ between the resist pattern 704 and the resist pattern 705 becomes larger than the resolution limit of the photoresist space pattern. Furthermore, since the formation of the gate electrode 701 and the gate electrode 702 using a shrink etching, the gate isolation width b between the gate electrode 701 and the gate electrode 702 is larger than the resist separation width b _0. Therefore, if the space between the active regions 700 is not sufficiently widened, a region having a short gate length is formed in the thick dotted line portion shown in FIG. 8A, and desired MOS transistor characteristics cannot be obtained. Further, widening the space between the active regions 700 means inhibiting the miniaturization of the gate line pattern.

  For this reason, in Japanese Patent Laid-Open No. 2002-305251, the gate electrode is formed by using the following method. 9A and 9B show the configuration of a semiconductor device formed using the method disclosed in the publication, FIG. 9A is a top view thereof, and FIG. ) Is a cross-sectional view taken along line IXB-IXB shown in FIG.

  Specifically, first, a dummy gate layer (not shown) made of an insulating film is formed so as to straddle the two active regions 800, 800, and a sidewall insulating film 801 is formed on the side surface of the dummy gate layer. Next, an interlayer insulating film 802 is formed to the same height as the dummy gate layer, a portion that becomes a gate electrode region in the dummy gate layer is opened, and a gate electrode 803 and a gate electrode 804 are formed in the opening. As a result, the gate electrode 803 and the gate electrode 804 are formed across the non-opening region 806 of the dummy gate layer, that is, separated from each other on the element isolation insulating film 805. When the gate electrode is formed in this manner, it is possible to prevent the corner of the gate electrode end from being rounded.

  However, when a date electrode is formed using the method disclosed in Japanese Patent Laid-Open No. 2002-305251, polishing is performed when the interlayer insulating film 802 is formed and when the gate electrode 803 and the gate electrode 804 are formed. Will be performed twice. If polishing is not performed uniformly, the heights of the gate electrode 803 and the gate electrode 804 will be different.

  In addition, when the metal salicide is formed on the active region 800 using a known technique, the characteristics of the metal salicide deteriorate when the gate impurity activation process is performed after the gate electrode is formed. Polysilicon that has been used cannot be used as a gate electrode material.

  Furthermore, it is difficult to open only a part of the dummy gate layer using the anisotropic etching method without etching the sidewall insulating film 801 and the interlayer insulating film 802.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a fine gate space pattern on an element isolation region and a manufacturing method thereof while reducing a polishing process and the like. It is to be.

  A first semiconductor device of the present invention includes an element isolation insulating film formed on a semiconductor substrate, a first electrode and a second electrode provided on the element isolation insulating film so as to be separated from each other, a first electrode, The insulating film pattern provided on the element isolation insulating film so as to be sandwiched between the second electrode and the portions of the side surfaces of the first electrode and the second electrode other than the portion in contact with the insulating film pattern. And a sidewall insulating film.

  In the first semiconductor device of the present invention, the insulating film pattern has a portion having the smallest width, and the width of the insulating film pattern in the portion having the smallest width is preferably 80 nm or less.

  In the first semiconductor device of the present invention, an element region and a dummy region exist in the semiconductor substrate, and the first electrode and the second electrode, the insulating film pattern, and the sidewall insulating film are in the element region. It is preferable that an insulating film pattern and a sidewall insulating film provided on a side surface of the insulating film pattern are provided in the dummy region.

  In the first semiconductor device of the present invention, the area of the portion of the insulating film pattern that is in contact with the upper surface of the semiconductor substrate is preferably 20% or more and 50% or less of the area of the upper surface of the semiconductor substrate.

  In the first semiconductor device of the present invention, the element isolation insulating film is preferably wider than the insulating film pattern.

  The first semiconductor device of the present invention preferably further includes a metal silicide film provided on each of the first electrode and the second electrode, and an interlayer insulating film covering the metal silicide film and the insulating film pattern. .

  A second semiconductor device according to the present invention includes an active region and an element isolation insulating film formed on a semiconductor substrate so as to be adjacent to each other, a gate insulating film provided on the active region, and a gate insulating film. A first gate electrode provided; an insulating film pattern provided on the element isolation insulating film and in contact with the first gate electrode; and a second gate provided on the opposite side of the first gate electrode across the insulating film pattern An electrode, sidewall insulating films respectively provided on portions of the side surfaces of the first gate electrode and the second gate electrode other than a portion in contact with the insulating film pattern, and within the active region and below the gate insulating film And provided source / drain electrodes. The insulating film pattern extends parallel to the active region, while the first gate electrode and the second gate electrode extend substantially perpendicular to the active region, respectively, and both ends of the first gate electrode and the second gate electrode. Are provided on the element isolation insulating film.

  In the second semiconductor device of the present invention, the second gate electrode is preferably provided to face the first gate electrode with the insulating film pattern interposed therebetween.

  In the second semiconductor device of the present invention, the second active region provided on the side opposite to the active region with respect to the element isolation insulating film, and the second gate insulation provided on the second active region. A second gate electrode is provided on the second gate insulating film, and each of the first gate electrode and the second gate electrode is an SRAM (static random access memory) gate electrode. Preferably there is.

  The second semiconductor device of the present invention further includes a metal silicide film provided on each of the first gate electrode and the second gate electrode, and an interlayer insulating film covering the metal silicide film and the insulating film pattern. It is preferable that an insulating film is provided between the metal silicide film and the interlayer insulating film.

  In the first and second semiconductor devices of the present invention, the insulating film pattern is preferably formed by stacking a plurality of insulating film patterns, and the upper surface of the insulating film pattern is preferably made of a silicon oxide film. .

  The first method for manufacturing a semiconductor device of the present invention includes a step of sequentially providing an element isolation insulating film and an insulating film material on a semiconductor substrate, a step of providing a first resist pattern on the insulating film material, and a first resist pattern Etching the insulating film material using the mask as a mask, forming an insulating film pattern on the element isolation insulating film, and providing an electrode material in a portion of the element isolation insulating film other than the portion where the insulating film pattern is formed A step of providing a second resist pattern on the insulating film pattern and the electrode material; and etching the electrode material using the second resist pattern as a mask so that the insulating film pattern is sandwiched between the first electrode and the second electrode. And forming a sidewall insulating film on the exposed portions of the side surfaces of the first electrode and the second electrode.

  In the first method of manufacturing a semiconductor device of the present invention, in the step of forming the insulating film pattern, after the isotropic etching is performed on the first resist pattern, the first resist pattern is used as a mask to the insulating film material. In the step of forming the first electrode and the second electrode by performing anisotropic etching, after the isotropic etching is performed on the second resist pattern, the second resist pattern is used as a mask to make a difference from the electrode material. It is preferable to perform isotropic etching.

  In the first method of manufacturing a semiconductor device of the present invention, the step of providing the electrode material includes the step of providing the electrode material so as to cover the insulating film pattern, and the step of polishing the electrode material until the upper surface of the insulating film pattern is exposed. And a step of performing a heat treatment after injecting impurities into the electrode material.

  In the first method for manufacturing a semiconductor device of the present invention, after the step of forming the sidewall insulating film, a step of providing a metal silicide film on each of the first electrode and the second electrode, and a metal silicide film and an insulating film pattern are provided. And a step of providing an interlayer insulating film so as to cover it.

  According to a second method of manufacturing a semiconductor device of the present invention, a step of forming an active region and an element isolation insulating film on a semiconductor substrate so as to be adjacent to each other, a step of providing a gate insulating film on the active region, A step of providing an insulating film material on the film and the element isolation insulating film; a step of providing a first resist pattern on the insulating film material so as to extend substantially parallel to the active region; and using the first resist pattern as a mask Forming an insulating film pattern on the element isolation insulating film by etching the insulating film material; and providing a gate electrode material in a portion of the element isolation insulating film other than the portion where the insulating film pattern is formed; A step of providing a second resist pattern on the insulating film pattern and the gate electrode material so as to extend substantially perpendicular to the active region; Forming a first gate electrode on the gate insulating film and forming a second gate electrode on the opposite side of the first gate electrode across the insulating film pattern by etching the gate electrode material as A step of providing a sidewall insulating film on the exposed portions of the side surfaces of the first gate electrode and the second gate electrode; and by implanting source / drain electrode materials into the active region, respectively, from the gate insulating film in the active region And a step of forming source / drain electrodes underneath.

  In the second method for manufacturing a semiconductor device of the present invention, a step of forming a second active region on the side opposite to the active region with respect to the element isolation insulating film, and a second gate on the second active region A step of providing an insulating film, and a second gate electrode is preferably provided on the second gate insulating film.

  In the second method of manufacturing a semiconductor device of the present invention, in the step of forming the insulating film pattern, after the isotropic etching is performed on the first resist pattern, the first resist pattern is used as a mask to the insulating film material. In the step of forming the first gate electrode and the second gate electrode by performing anisotropic etching, isotropic etching is performed on the second resist pattern, and then the gate electrode material is formed using the second resist pattern as a mask. On the other hand, it is preferable to perform anisotropic etching.

  In the second method for manufacturing a semiconductor device of the present invention, after the step of forming the sidewall insulating film, a step of providing a metal silicide film on the first gate electrode and the second gate electrode, respectively, and a metal silicide film and an insulating film It is preferable to further include a step of providing an interlayer insulating film so as to cover the pattern.

  In the second semiconductor device manufacturing method of the present invention, in the step of providing the second resist pattern, the second resist pattern is provided so that a part of the insulating film pattern is exposed, and the first gate electrode and the second gate electrode are formed. In this step, etching is preferably performed on the exposed portion of the insulating film pattern.

  According to the present invention, the polishing process and the like are reduced, and a fine gate space pattern is provided on the element isolation region.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same members are denoted by the same reference numerals, and the description thereof is omitted. Further, the present application is not limited to the following description.

Embodiment 1 of the Invention
FIG. 1A to FIG. 1J are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment, particularly a method for manufacturing an element region 120 of the semiconductor device.

  First, as shown in FIG. 1A, an element insulating film 101 and a silicon nitride film (insulating film material) 102 are sequentially formed on a p-type silicon substrate (semiconductor substrate) 100. Here, it is preferable to form the element insulating film 101 on the silicon substrate 100 by using an STI (Shallow Trench Isolation) method. As for the film thickness, it is preferable that the film thickness of the element insulating film 101 is 300 nm and the film thickness of the silicon nitride film 102 is 140 nm.

  Next, as shown in FIG. 1B, a resist pattern (first resist pattern) 103 is formed on the silicon nitride film 102 by using a lithography technique.

  Subsequently, the silicon nitride film 102 is anisotropically etched using the resist pattern 103 as a mask to form a gate isolation insulating film pattern (insulating film pattern) 104 as shown in FIG. 1C, and the resist pattern 103 is removed. . The etching conditions for the silicon nitride film 102 are preferably set so that the silicon nitride film 102 is etched preferentially over the element insulating film 101. In addition, the lateral dimension of the gate isolation insulating film pattern 104 may be reduced by performing isotropic etching of the resist pattern 103 before anisotropic etching of the silicon nitride film 102 (shrink etching). Further, the width of the gate isolation insulating film pattern 104 is preferably narrower than the width of the element isolation insulating film 101 and may not be substantially the same in the longitudinal direction. The width is preferably 80 nm or less. Moreover, it is preferable that the area of the portion of the gate isolation insulating film pattern 104 that is in contact with the upper surface of the semiconductor substrate is 20% or more and 50% or less of the area of the upper surface of the semiconductor substrate.

  Subsequently, as shown in FIG. 1D, polysilicon is formed on the entire upper surface of the P-type silicon substrate 100 (on the element insulating film 101 and the gate isolation insulating film pattern 104) by using a CVD (Chemical Vapor Deposition) method. (Electrode material) 105 is deposited. At this time, it is preferable to deposit the polysilicon 105 until the film thickness becomes, for example, 160 mm.

  Subsequently, as shown in FIG. 1E, the polysilicon 105 is polished using the CMP (Chemical Mechanical Polish) method until the gate isolation insulating film pattern 104 is exposed. Including over-polishing, the thickness of the gate isolation insulating pattern 104 and the polysilicon 105 is preferably 120 nm, for example. Here, in a portion of the gate isolation insulating film pattern 104 where the pattern density is low, the thickness after polishing of the polysilicon 105 becomes thinner than that of the silicon nitride film 102 where the pattern density is high due to a phenomenon called dishing. End up. Dishing can be avoided by using the gate isolation insulating film pattern 104 as a dummy pattern in CMP. To this end, gate isolation is not only performed in the region where the gate electrode is to be isolated, but also in portions other than the element formation region. An insulating film pattern 104 is formed. In this case, the area ratio of the portion used as the dummy pattern in the gate isolation insulating film pattern 104 is preferably 20% or more, and the size is arbitrary, and it is not necessarily formed on the element isolation insulating film 101. It does not have to be.

  Subsequently, although not shown, an impurity is implanted into the polysilicon 105 using an ion implantation method, and the impurity is activated.

  Subsequently, as shown in FIG. 1F, a resist pattern (second resist pattern) 106 is formed on the gate isolation insulating film pattern 104 and the polysilicon 105 by using a lithography technique. Here, the resolution limit dimension of the photoresist space pattern (resist pattern 106) constituting the resist pattern 106 is larger than the lateral dimension of the gate isolation insulating film pattern 104.

  Subsequently, as shown in FIG. 1G, the polysilicon 105 is shrink etched using the resist pattern 106 as a mask. Thereby, the first and second electrodes 107a and 107b are formed. Here, the amount by which the resist pattern 106 is reduced by isotropic etching applied to the resist pattern 106 is about 20 nm.

  Subsequently, as shown in FIG. 1H, for example, a film thickness of 40 nm is formed on the entire top surface of the P-type silicon substrate 100 (on the gate isolation insulating film pattern 104 and on the first and second electrodes 107a and 107b). After the silicon nitride film is deposited, the silicon nitride film is etched back. As a result, the sidewall insulating film 108 is formed on the portions of the sidewalls of the first and second electrodes 107a and 107b that are not in contact with the gate isolation insulating film pattern 104.

  Subsequently, as shown in FIG. 1I, the entire upper surface of the p-type silicon substrate 100 (on the gate isolation insulating film pattern 104 and the first and second electrodes 107a and 107b) is formed using a plasma CVD method or the like. A silicon oxide film (having a thickness of 500 nm to 700 nm, for example) is deposited, and then CMP is performed. As a result, an interlayer insulating film 109 (having a thickness of 100 nm to 300 nm, for example) is formed on the first and second electrodes 107a and 107b and the gate isolation insulating film pattern 104.

  When the semiconductor device thus formed is viewed from above, it is as shown in FIG. That is, in the semiconductor device according to the present embodiment, the element insulating film 101 is formed on the upper surface of the semiconductor substrate 100. A gate isolation insulating film pattern 104 and first and second electrodes 107a and 107b are provided on the element insulating film 101, and the first and second electrodes 107a and 107b are provided with the gate isolation insulating film pattern 104 interposed therebetween. It has been. Sidewall insulating films 108 are provided on portions of the side surfaces of the first and second electrodes 107 a and 107 b that are not in contact with the gate isolation insulating film pattern 104.

  As described above, the gate isolation insulating pattern 104 is provided between the first electrode 107a and the second electrode 107b, whereby the first electrode 107a and the second electrode 107b are provided apart from each other. ing. In order to form such first and second electrodes 107a and 107b, a gate isolation insulating film pattern 104 is formed using a photoresist line pattern (resist pattern 103) as a mask, and the gate isolation insulating film pattern 104 is sandwiched therebetween. A step of providing a gate electrode material (polysilicon) on the substrate, and a step of etching a portion of the gate electrode material exposed from the photoresist space pattern and then filling the etched portion with an insulating film (interlayer insulating film 109). Two types of processes are combined.

  Further, when the first and second electrodes 107a and 107b are formed by shrink etching without using the gate isolation insulating film pattern 104, a gate line pattern below the resolution limit can be formed, but the space pattern is It will spread. However, by combining shrink etching when forming the gate isolation insulating film pattern 104, it is possible to form a gate space pattern below the resolution limit. That is, by performing shrink etching twice, both the gate line pattern and the gate space pattern can be formed below the resolution limit.

  In addition, after the sidewall insulating film 108 is formed, if a metal silicide film is formed on the surface of each of the first and second electrodes 107a and 107b using a known method, the activation process of the gate impurity is performed to form the sidewall insulating film 108. Has been completed before. Therefore, after the metal silicide film is formed, the metal silicide film is not exposed to a high-temperature and long-time heat treatment typified by a gate impurity activation process, so that deterioration of silicide characteristics can be prevented.

  In the semiconductor device according to the present embodiment, the gate isolation insulating film pattern 104 is produced by etching the silicon nitride film 102. However, the silicon nitride film 102 may be an insulating film that is preferentially etched over the element insulating film 101, and may have a laminated structure of a lower silicon nitride film and an upper silicon oxide film. When the silicon nitride film 102 has a laminated structure as described above, after patterning the upper silicon oxide film and the lower silicon nitride film by anisotropic etching, only the lower silicon nitride film is further narrowed by isotropic etching. Can be processed. In this processing, since the width of the upper silicon oxide film is not reduced, the apparent area ratio of the gate isolation insulating film pattern is not reduced. Therefore, when a laminated structure is employed as the silicon nitride film 102, dishing can be avoided by using a pattern with a small area ratio, and the gate isolation width can be reduced.

  In addition, when the entire semiconductor substrate is considered, there are regions (for example, dummy regions) that do not require fine gate pattern formation. In the process of depositing a silicon oxide film on the entire semiconductor substrate after forming the gate electrode and then performing CMP to form an interlayer insulating film, dishing occurs in regions where the gate pattern area ratio is low during CMP. . For this reason, in the conventional method, the occurrence of dishing is suppressed by forming a dummy gate electrode pattern in the dummy region to prevent a reduction in the area ratio of the gate pattern. However, as shown in FIG. 2A, when the wiring pattern 205 is disposed on the interlayer insulating film 204 in the dummy region 210, stray capacitance is generated between the wiring pattern 205 and the dummy gate electrode pattern 202. There has been a problem that the operating speed of the semiconductor device becomes slow. In FIG. 2A, reference numeral 200 denotes a p-type silicon substrate, 201 denotes an element isolation insulating film, and 203 denotes a sidewall insulating film.

  On the other hand, when the semiconductor device manufacturing method according to the present embodiment is applied, as shown in FIG. 2B, in the dummy region 220, a part of the dummy gate electrode 205 is replaced with a gate isolation insulating film pattern (insulating film pattern). 206 can be replaced. As a result, no stray capacitance is generated between the dummy gate electrode pattern 205 and the gate isolation insulating film pattern 206, so that dishing can be prevented and a decrease in the operating speed of the semiconductor device can be suppressed. If the area ratio of the gate pattern can be ensured, all the dummy gate electrode patterns 202 may be replaced with the gate isolation insulating film pattern 206.

<< Embodiment 2 of the Invention >>
FIG. 3A to FIG. 3G are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. In the following description, the same contents as those in the first embodiment are omitted.

  First, as shown in FIG. 3A, an element isolation insulating film 301, a silicon nitride film (insulating film material) 302, and a polysilicon 303 are sequentially formed on a p-type silicon substrate (semiconductor substrate) 300. At this time, it is preferable that the element isolation insulating film 301 has a thickness of, for example, 300 nm, the silicon nitride film 302 has a thickness of, for example, 140 nm, and the polysilicon 303 has a thickness of 30 nm.

  Next, as shown in FIG. 3B, a resist pattern (first resist pattern) 304 is formed on the polysilicon 303 by photolithography.

  Subsequently, the polysilicon 303 is anisotropically etched using the resist pattern 304 as a mask, a polysilicon mask 305 is formed as shown in FIG. 3C, and the resist pattern 304 is removed. It is preferable that the polysilicon 303 is etched under conditions where the polysilicon 303 is preferentially etched over the silicon nitride film 302. In addition, the resist pattern 304 may be isotropically etched to reduce the lateral dimension of the polysilicon mask 305 before anisotropic etching of the polysilicon 303 is performed.

  Subsequently, as shown in FIG. 3D, a gate isolation insulating film pattern (insulating film pattern) 306 is formed by anisotropically etching the silicon nitride film 302 using the polysilicon mask 305 as a mask. It is preferable that the silicon nitride film 302 is etched under a condition that the silicon nitride film 302 is preferentially etched over the element isolation insulating film 301.

  Subsequently, as shown in FIG. 3E, the dimensions of the gate isolation insulating film pattern 306 are shrunk by isotropic etching to form a gate isolation insulating film pattern (insulating film pattern) 316. Here, since the polysilicon mask 305 is provided on the gate isolation insulating film pattern 306, no shrinkage occurs in the vertical direction of the gate isolation insulating film pattern 306. The amount of shrinkage of the gate isolation insulating film pattern 306 by isotropic etching is preferably about 20 nm.

  Subsequently, as shown in FIG. 3F, the entire upper surface of the p-type silicon substrate 300 (specifically, on the element isolation insulating film 301, on the side of the gate isolation insulating film pattern 316, and the like) using the CVD method. Polysilicon (electrode material) 307 is deposited on the polysilicon mask 305). At this time, it is preferable to deposit polysilicon 307 having a film thickness of 160 nm, for example, on the upper surface of the p-type silicon substrate 300 and the polysilicon mask 305, respectively.

  Subsequently, as shown in FIG. 3G, the polysilicon 307 is polished by CMP until the gate isolation insulating film pattern 316 is exposed. At this time, it is preferable that the film thicknesses of the gate isolation insulating film pattern 316 and the polysilicon 307 are each 120 nm including over polishing. Further, the polysilicon mask 305 is removed by the CMP method. In subsequent steps, FIG. 1 (f) to FIG. 1 (i) of the first embodiment are sequentially performed.

  In the semiconductor device thus formed, the element isolation insulating film 301 is formed on the semiconductor substrate 300 as in the first embodiment, and two gate electrodes (not shown) are formed on the element isolation insulating film 301. ) Are provided so as to sandwich the gate isolation insulating film pattern 316. However, since the gate isolation insulating film pattern 316 is formed by shrink etching, it is narrower than the gate isolation insulating film pattern 104 in the first embodiment.

  As in the first embodiment, the semiconductor device manufactured using the above manufacturing method is excellent in forming a fine gate line pattern (resist pattern 304) and excellent in forming a fine gate space pattern (not shown). By using them properly according to the intended pattern, fine gate processing becomes possible, and the semiconductor device can be highly integrated. Further, since the gate isolation insulating film pattern 316 is shrunk by isotropic etching after patterning, the semiconductor device can be further integrated as compared with the first embodiment. Further, as will be described later, since the resist pattern 304 is also miniaturized as compared with the first embodiment, the semiconductor device can be further highly integrated.

  When patterning is performed using shrink etching, the height of the pattern of the resist pattern formed on the material to be etched is also shrunk by performing isotropic etching (the height of the resist pattern is reduced). In general, if the shrink amount of the resist height is too large, the resist may disappear before the etching of the material to be etched is completed. Therefore, the shrink amount of the resist height cannot be set to a certain value or more. However, in this embodiment, the object (material to be etched) to be anisotropically etched using the resist pattern 304 as a mask is not the silicon nitride film 302 (for example, the film thickness is 140 nm) but the polysilicon 303 (for example, the film thickness is 30 nm). Therefore, the film thickness of the resist pattern 304 necessary for completing the etching is thinner than that in the first embodiment. Thereby, the shrink amount with respect to the resist pattern 304 can be increased. Alternatively, the initial film thickness of the resist pattern 304 can be reduced as compared with the first embodiment without increasing the shrink amount with respect to the resist pattern 304. Usually, in resist patterning in lithography, a finer resist pattern 304 can be formed as compared with the first embodiment when the amount of shrinkage is not increased because a finer pattern can be resolved with a thinner resist film. .

  In the present embodiment, the gate isolation insulating film pattern 306 can be shrunk by using the polysilicon mask 305 as a hard mask. Therefore, the gate isolation insulating film pattern 316 finer than the resist pattern 304 can be formed more stably than in the first embodiment. Further, since the polysilicon mask 305 is made of the same material as the gate electrode (not shown), it is possible to suppress adverse effects on the gate electrode when the polysilicon 307 is polished by the CMP method.

<< Embodiment 3 of the Invention >>
FIG. 4A to FIG. 4I are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment. In the following description, the same contents as those in the first embodiment are omitted.

  First, as shown in FIG. 4A, a trench region (not shown) is formed on the upper surface of a p-type silicon substrate (semiconductor substrate) 400 using a well-known element isolation method, and element isolation insulation is formed in the trench region. The film 401 is embedded to separate the device into a first active region (active region) 402 and a second active region (second active region) 422. At this time, the element isolation insulating film 401 is formed so as to be sandwiched between the first active region 402 and the second active region 422. After the sacrificial oxide films 404 and 404 are formed on the first and second active regions 402 and 422, respectively, the entire upper surface of the p-type silicon substrate 400 (specifically, on the element isolation insulating film 401 and the first A silicon nitride film (insulating film material) 403 is formed on the first and second active regions 402 and 422). Here, the depth of the trench region is preferably 300 nm, for example, the thickness of the silicon nitride film 403 is preferably 140 nm, for example, and the thickness of the sacrificial oxide films 404 and 404 is preferably 10 nm, for example.

  Next, as shown in FIG. 4B, a resist pattern (first resist pattern) 405 is formed on the silicon nitride film 403 by lithography. At this time, a resist pattern 405 is formed substantially parallel to the first active region 402.

  Subsequently, the silicon nitride film 403 is anisotropically etched using the resist pattern 405 as a mask to form a gate isolation insulating film pattern (insulating film pattern) 406 as shown in FIG. Thereafter, the resist pattern 405 is removed. When etching the silicon nitride film 403, it is preferable to set the etching conditions so that the silicon nitride film 403 is preferentially etched over the element isolation insulating film 401 and the sacrificial oxide films 404. Here, the width of the gate isolation insulating film 406 is made smaller than that of the element isolation insulating film 401 in anticipation of the width of a sidewall insulating film 412 (see FIG. 4H) formed in a process described later, Since it is preferable that the sidewall insulating film 412 of the isolation insulating film pattern does not cover the active region 402, it is preferable to perform isotropic etching (shrink etching) on the resist pattern 405 as necessary.

  Subsequently, the sacrificial oxide films 404 and 404 are removed to expose the upper surfaces of the first and second active regions 402 and 422, respectively. Then, as shown in FIG. 4D, the first and second gate insulating films (in order, the gate insulating film and the second insulating film are formed on the first and second active regions 402 and 422, respectively, using a thermal oxidation method. Gate insulating films) 407 and 427 are formed, and further, the entire upper surface of the semiconductor substrate 400 (specifically, on the element isolation insulating film 401 and the first and second gate insulating films 407 and 427) is formed by CVD. Polysilicon (electrode material) 408 is deposited on the upper surface and on the top and sides of the gate isolation insulating film pattern 406. At this time, the thicknesses of the first and second gate insulating films 407 and 427 are each preferably 2 nm, for example, and the thickness of the polysilicon 408 is preferably 160 nm, for example.

  Subsequently, as shown in FIG. 4E, the polysilicon 408 is polished by CMP until the gate isolation insulating film pattern 406 is exposed. The film thickness of the gate isolation insulating film pattern 406 and the polysilicon 408 including over polishing is preferably set to 120 nm, for example. Although not shown, an impurity is implanted into the polysilicon by an ion implantation method to activate the impurity.

  Subsequently, as shown in FIG. 4F, lithography is applied to the entire upper surface of the p-type silicon substrate 400 (specifically, on the gate isolation insulating film pattern 406 and on the polysilicon 408). A resist pattern (second resist pattern) 409 is formed. At this time, a resist pattern 409 is formed so as to extend substantially perpendicular to the first active region 402.

  Subsequently, the polysilicon 408 is shrink-etched using the resist pattern 409 as a mask to form first and second gate electrodes 410a and 410b, respectively, as shown in FIG. Thus, the first and second gate electrodes 410 a and 410 b are provided so as to extend substantially perpendicular to the first active region 402, and both ends thereof are provided on the element isolation insulating film 401. At this time, it is preferable to perform isotropic etching on the resist pattern 409 during shrink etching to reduce the resist pattern 409 by about 20 nm.

  Subsequently, as shown in FIG. 4H, impurities are implanted into the active region 402 by ion implantation using the first and second gate electrodes 410a and 410b as masks, and the first and second upper diffusion layers 411 are implanted. , 421 are formed. Here, actually, the first and second upper diffusion layers 411 and 421 are not formed immediately below the first and second gate electrodes 410a and 410b, respectively, but the first and second upper diffusion layers 411 and 421 are not formed. In order to show the position where it is formed, it is indicated by a broken line in FIG. Then, a silicon nitride film is deposited on the p-type silicon substrate 400 and etched back. As a result, the sidewall insulating film 412 is formed on portions of the side surfaces of the first and second gate electrodes 410a and 410b other than the portion in contact with the gate isolation insulating film pattern 406.

  Subsequently, as shown in FIG. 4I, an impurity is implanted into the active region 402 by ion implantation using the first and second gate electrodes 410a and 410b and the sidewall insulating film 412 as a mask. Thereby, the first and second lower diffusion layers 413 and 423 are formed. Here, the first and second lower diffusion layers 413 are not formed below the gate electrode 410a and the gate electrode 410b, but to show the positions where the first and second lower diffusion layers 413 and 423 are formed. In FIG. 4 (i), it is indicated by a broken line. Then, the entire upper surface of the p-type silicon substrate (specifically, on the gate isolation insulating film pattern 406, on the first and second gate electrodes 410a and 410b, and on the sidewall insulating film 412) is formed using the CVD method. In addition, a liner film (insulating film) 414 is formed, and an interlayer insulating film 415 is formed on the liner film 414. Here, the liner film 414 is preferably made of a silicon nitride film, and its film thickness is preferably 20 nm. The thickness of the silicon oxide film is preferably 500 nm to 700 nm, and the thickness of the interlayer insulating film 405 is preferably 100 nm to 300 nm. Thereafter, although not shown, a semiconductor device can be manufactured by forming a wiring pattern or the like.

  The semiconductor device thus formed is shown in FIG. Here, FIG. 5A is a top view of the semiconductor device according to the present embodiment, and FIG. 5A shows a state in which the liner film 414 and the interlayer insulating film 415 have been removed. FIG. 5B is a cross-sectional view taken along line VB-VB shown in FIG.

  As shown in FIGS. 5A and 5B, in the semiconductor device according to the present embodiment, the element isolation insulating film 401 is formed on the p-type silicon substrate 400 with the first active region 402 and the second active region 422. It is sandwiched between. First and second gate insulating films 407 and 427 are provided on the first and second active regions 402 and 422, respectively. The first and second gate insulating films 407 and 427 are provided on the first and second gate insulating films 407 and 427, respectively. Second gate electrodes 410a and 410b are provided. The first and second gate electrodes 410a and 410b are provided so as to extend substantially perpendicular to the first and second active regions 402 and 422, respectively, and both ends thereof are provided on the element isolation insulating film 401, respectively. ing.

  A gate isolation insulating film pattern 406 is provided on the element isolation insulating film 401, and the gate isolation insulating film pattern 406 is provided between the first gate electrode 410a and the second gate electrode 410b. A sidewall insulating film 412 is provided on the exposed portions of the first and second gate electrodes 410a and 410b.

  In the manufacturing method according to this embodiment, when the end of a fine gate line pattern (resist pattern 405) is separated from another gate pattern, the gate line pattern with a fine width is prevented from retreating and the transistor characteristics are stabilized. In addition, separation from another gate pattern is achieved with a fine separation width. Furthermore, in this embodiment, by combining shrink etching, it is possible to simultaneously form a fine gate line pattern and a gate space pattern (resist pattern 409) below the resolution limit, thereby increasing the integration density of the semiconductor device. Can be realized.

  In addition, when the step of forming a metal silicide film using a known method on the surfaces of the gate electrode 410a, the gate electrode 410b, and the active region 402 after the formation of the sidewall insulating film 412, the gate impurity activation process is performed. This is completed before the sidewall insulating film 412 is formed. Therefore, since the metal silicide film formed by using a known method is not exposed to a high-temperature and long-time heat treatment represented by the activation treatment of the gate impurity, deterioration of the silicide characteristics can be suppressed.

  Although the case where two MOS transistors arranged in parallel are manufactured has been described above, integration is possible even when one MOS transistor and the gate wiring on the element isolation insulating film are formed separately from each other. Can do. FIGS. 6A to 6C are diagrams showing a configuration in the case where one MOS transistor and a gate wiring are formed separately from each other. As described above, the sidewall insulating film 412 is formed on the portion of the gate electrode 410a and the gate electrode 410b that is not in contact with the gate isolation insulating film 406. For this reason, as shown in FIG. 6A, it is preferable that the gate isolation insulating film pattern 406 and the active region 402 be separated from each other by the thickness of the sidewall insulating film 412 or more.

  However, as shown in FIG. 8, even in the case other than the case where two MOS transistors are arranged side by side, the gate isolation is expanded due to the rounding of the corners of the gate end that occurs when the present invention is not used. In particular, as the shrinkage amount in shrink etching increases when the gate electrode 410a and the gate electrode 410b are formed, the retreat amount of the gate end portion dramatically increases. Therefore, when the present invention is not used, the pattern layout larger than the film thickness of the sidewall insulating film 412 necessary when the present invention is used must be enlarged. Therefore, in the present invention, high integration can be realized for a semiconductor device other than a semiconductor device in which a plurality of MOS transistors such as SRAM are arranged.

  Further, when the gate electrode 410a is a gate wiring formed on the element isolation insulating film 401, as shown in FIG. 6B, if the gate isolation insulating film pattern 406 is used without performing shrink etching. In addition, the pattern width of the portion in contact with the gate isolation insulating film pattern 406 can be made below the resolution limit.

  Further, since the gate isolation insulating film pattern 406 only needs to be sandwiched between the first gate electrode 410a and the second gate electrode 410b, the shape shown in FIG. In this case, since the sidewall insulating film 412 is not provided between the first active region 402 and the gate isolation insulating film pattern 406, the first gate electrode 410a and the sidewall insulating film 412 are compared with the case shown in FIGS. The distance from the first active region 402 can be further reduced. Therefore, unlike the case shown in FIGS. 6A and 6B, the semiconductor device can be further highly integrated in the case shown in FIG. 6C.

  In order to form the gate isolation insulating film pattern 406 shown in FIG. 6C, for example, a resist pattern 409 is formed so as to expose a part of the gate isolation insulating film pattern 406 in the step shown in FIG. Etching is performed using the provided resist pattern 409 as a mask, whereby the first and second gate electrodes 410a and 410b can be formed and the gate isolation insulating film pattern 406 shown in FIG. 6C can be formed.

  As described above, the present invention is useful for forming a semiconductor device having a narrow gate isolation width.

Sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. Sectional drawing explaining the manufacturing process of the semiconductor device concerning the modification of Embodiment 1 of this invention. Sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. Sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 3 of this invention. (A) is a top view of the semiconductor device concerning Embodiment 3 of this invention, (b) is sectional drawing in the VB-VB line | wire shown in FIG.4 (i). (A)-(c) is a top view of the semiconductor device concerning the modification of Embodiment 3 of this invention. Sectional drawing of the semiconductor device concerning a 1st conventional form. (A) is a top view of a semiconductor device having a fine gate line pattern formed by using the process in the second conventional embodiment, and (b) is a state in which the end portion of the resist pattern 707 recedes from the reticle pattern 708. FIG. (A) is a top view which shows the manufacturing process of the MOS transistor concerning another conventional embodiment, (b) is sectional drawing in the IXB-IXB line | wire shown to (a).

Explanation of symbols

100 p-type silicon substrate (semiconductor substrate)
101 element isolation insulating film 102 silicon nitride film (insulating film material)
103 resist pattern (first resist pattern)
104 Gate isolation insulating film pattern (insulating film pattern)
105 Polysilicon (electrode material)
106 resist pattern (second resist pattern)
107a First electrode 107b Second electrode 108 Side wall insulating film 109 Interlayer insulating film 200 p-type silicon substrate (semiconductor substrate)
201 Element isolation insulating film 202 Dummy gate electrode pattern 203 Side wall insulating film 204 Interlayer insulating film 205 Wiring pattern 206 Gate isolation insulating film pattern (insulating film pattern)
300 p-type silicon substrate (semiconductor substrate)
301 Element isolation insulating film 302 Silicon nitride film (insulating film material)
303 Polysilicon 304 resist pattern (first resist pattern)
305 Polysilicon mask 306 Gate isolation insulating film pattern (insulating film pattern)
307 Polysilicon (electrode material)
316 Gate isolation insulating film pattern (insulating film pattern)
400 p-type silicon substrate (semiconductor substrate)
401 Element isolation insulating film 402 First active region (active region)
403 Silicon nitride film (insulating film material)
404 Sacrificial oxide film 405 Resist pattern (first resist pattern)
406 Gate isolation insulating film pattern (insulating film pattern)
407 First gate insulating film (gate insulating film)
408 Polysilicon (electrode material)
409 resist pattern (second resist pattern)
410a First gate electrode 410b Second gate electrode 411 First upper diffusion layer 412 Side wall insulating film 413 First lower diffusion layer 414 Liner film (insulating film)
415 Interlayer insulating film 421 Second upper diffusion layer 422 Second active region (second active region)
423 Second lower diffusion layer 427 Second gate insulating film (second gate insulating film)
600 Semiconductor substrate 601 Element isolation insulating film 602 Gate electrode 603 Gate electrode 604 Side wall insulating film 605 Interlayer insulating film 700 Active region 701 Gate electrode 702 Gate electrode 703 Element isolation insulating film 704 Resist pattern 705 Resist pattern 706 Rounded corner of resist 707 Resist Pattern 708 Resist pattern 800 Active region 801 Side wall insulating film 802 Interlayer insulating film 803 Gate electrode 804 Gate electrode 805 Element isolation insulating film 806 Non-opening region of dummy gate layer

Claims (22)

An element isolation insulating film formed on a semiconductor substrate;
A first electrode and a second electrode provided on the element isolation insulating film so as to be separated from each other;
An insulating film pattern provided on the element isolation insulating film so as to be sandwiched between the first electrode and the second electrode;
A side wall insulating film provided on each of the side surfaces of the first electrode and the second electrode other than a portion in contact with the insulating film pattern. The insulating film pattern has a portion having a minimum width,
The semiconductor device according to claim 1, wherein a width of the insulating film pattern of the portion having the smallest width is 80 nm or less. The semiconductor substrate has an element region and a dummy region,
The first electrode and the second electrode, the insulating film pattern, and the sidewall insulating film are provided in the element region,
The semiconductor device according to claim 1, wherein the insulating film pattern and a side wall insulating film provided on a side surface of the insulating film pattern are provided in the dummy region.   2. The semiconductor device according to claim 1, wherein an area of a portion of the insulating film pattern that is in contact with an upper surface of the semiconductor substrate is 20% or more and 50% or less of an area of the upper surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the element isolation insulating film is wider than the insulating film pattern. Metal silicide films respectively provided on the first electrode and the second electrode;
The semiconductor device according to claim 1, further comprising an interlayer insulating film that covers the metal silicide film and the insulating film pattern. An active region and an element isolation insulating film formed on a semiconductor substrate so as to be adjacent to each other;
A gate insulating film provided on the active region;
A first gate electrode provided on the gate insulating film;
An insulating film pattern provided on the element isolation insulating film and in contact with the first gate electrode;
A second gate electrode provided on the opposite side of the first gate electrode across the insulating film pattern;
Sidewall insulating films provided respectively on portions of the side surfaces of the first gate electrode and the second gate electrode other than the portion in contact with the insulating film pattern;
A source / drain electrode provided in the active region and below the gate insulating film;
While the insulating film pattern extends parallel to the active region,
The first gate electrode and the second gate electrode each extend substantially perpendicular to the active region, and both ends of the first gate electrode and the second gate electrode are provided on the element isolation insulating film, respectively. A semiconductor device.   The semiconductor device according to claim 7, wherein the second gate electrode is provided to face the first gate electrode with the insulating film pattern interposed therebetween. A second active region provided on the side opposite to the active region with respect to the element isolation insulating film;
A second gate insulating film provided on the second active region,
The second gate electrode is provided on the second gate insulating film;
The semiconductor device according to claim 7, wherein each of the first gate electrode and the second gate electrode is an SRAM gate electrode. Metal silicide films respectively provided on the first gate electrode and the second gate electrode;
The semiconductor device according to claim 7, further comprising an interlayer insulating film that covers the metal silicide film and the insulating film pattern.   The semiconductor device according to claim 10, wherein an insulating film is provided between the metal silicide film and the interlayer insulating film.   The semiconductor device according to claim 1, wherein the insulating film pattern is formed by stacking a plurality of insulating film patterns.   The semiconductor device according to claim 12, wherein an upper surface of the insulating film pattern is made of a silicon oxide film. A step of sequentially providing an element isolation insulating film and an insulating film material on a semiconductor substrate;
Providing a first resist pattern on the insulating film material;
Forming an insulating film pattern on the element isolation insulating film by etching the insulating film material using the first resist pattern as a mask;
A step of providing an electrode material in a portion of the element isolation insulating film other than the portion where the insulating film pattern is formed;
Providing a second resist pattern on the insulating film pattern and the electrode material;
Etching the electrode material using the second resist pattern as a mask to form a first electrode and a second electrode so as to sandwich the insulating film pattern; and
And a step of providing a side wall insulating film on the exposed portions of the side surfaces of the first electrode and the second electrode, respectively. In the step of forming the insulating film pattern, after performing isotropic etching on the first resist pattern, anisotropic etching is performed on the insulating film material using the first resist pattern as a mask,
In the step of forming the first electrode and the second electrode, after the isotropic etching is performed on the second resist pattern, anisotropy with respect to the electrode material is performed using the second resist pattern as a mask. The method for manufacturing a semiconductor device according to claim 14, wherein etching is performed. The step of providing the electrode material includes:
Providing the electrode material so as to cover the insulating film pattern;
Polishing the electrode material until an upper surface of the insulating film pattern is exposed;
The method for manufacturing a semiconductor device according to claim 14, further comprising a step of performing heat treatment after implanting impurities into the electrode material. After the step of forming the sidewall insulating film,
Providing a metal silicide film on each of the first electrode and the second electrode;
The method of manufacturing a semiconductor device according to claim 14, further comprising: providing an interlayer insulating film so as to cover the metal silicide film and the insulating film pattern. Forming an active region and an element isolation insulating film on a semiconductor substrate so as to be adjacent to each other;
Providing a gate insulating film on the active region;
Providing an insulating film material on the gate insulating film and the element isolation insulating film;
Providing a first resist pattern on the insulating film material so as to extend substantially parallel to the active region;
Forming the insulating film pattern on the element isolation insulating film by etching the insulating film material using the first resist pattern as a mask;
Providing a gate electrode material in a portion other than the portion where the insulating film pattern is formed in the element isolation insulating film;
Providing a second resist pattern on the insulating film pattern and the gate electrode material so as to extend substantially perpendicular to the active region;
The gate electrode material is etched using the second resist pattern as a mask to form a first gate electrode on the gate insulating film, and on the opposite side of the first gate electrode across the insulating film pattern Forming a second gate electrode;
Providing a sidewall insulating film on an exposed portion of the side surfaces of the first gate electrode and the second gate electrode;
Forming a source / drain electrode below the gate insulating film in the active region by injecting a source / drain electrode material into the active region, respectively. . Forming a second active region on a side opposite to the active region with respect to the element isolation insulating film;
Providing the second gate insulating film on the second active region,
The method of manufacturing a semiconductor device according to claim 18, wherein the second gate electrode is provided on the second gate insulating film. In the step of forming the insulating film pattern, after performing isotropic etching on the first resist pattern, anisotropic etching is performed on the insulating film material using the first resist pattern as a mask,
In the step of forming the first gate electrode and the second gate electrode, after the isotropic etching is performed on the second resist pattern, the second resist pattern is used as a mask for the gate electrode material. The method for manufacturing a semiconductor device according to claim 18, wherein anisotropic etching is performed. After the step of forming the sidewall insulating film,
Providing a metal silicide film on each of the first gate electrode and the second gate electrode;
The method for manufacturing a semiconductor device according to claim 18, further comprising: providing an interlayer insulating film so as to cover the metal silicide film and the insulating film pattern. In the step of providing the second resist pattern, the second resist pattern is provided so that a part of the insulating film pattern is exposed,
19. The method of manufacturing a semiconductor device according to claim 18, wherein in the step of forming the first gate electrode and the second gate electrode, etching is performed on an exposed portion of the insulating film pattern.

Images