JP2008198828A - Solid-state imaging device and manufacturing method thereof - Google Patents

Abstract

Even when a peripheral circuit portion including a multilayer wiring and an image pickup portion are formed on the same wafer, it is possible to suppress unevenness in thickness of a color filter or the like by reducing a height difference in a chip. Provided is a solid-state imaging device capable of maintaining sensitivity and uniformity of color tone.
An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, and a signal corresponding to the generated signal charge and an element driving signal are transmitted to the imaging unit. A solid-state imaging device 100 including a peripheral circuit unit 20 for inputting / outputting, and forming a field insulating film 81 on the surface of the semiconductor substrate 1 between the imaging unit 10 and the peripheral circuit unit 20 and removing it. The substrate surface height H2 of the peripheral circuit unit 20 is set lower than the substrate surface height H1 of the imaging unit 10.
[Selection] Figure 2

Description

  The present invention relates to a solid-state imaging device including an imaging unit and a peripheral circuit unit for inputting and outputting signals to and from the imaging unit on a semiconductor substrate, and a method for manufacturing the same.

In recent years, solid-state imaging devices used for video cameras, electronic cameras, and the like have been further improved in image quality and functionality. This solid-state imaging device has an imaging unit configured by two-dimensionally arranging a large number of pixels on one semiconductor chip, and a peripheral circuit unit arranged outside the imaging unit. In the pixel unit, a photodiode (photoelectric conversion element) generates a signal charge in response to incident light, and in the peripheral circuit unit, the signal charge generated in the imaging unit is extracted as an image signal based on the drive signal and output to the outside. is doing.
In the peripheral circuit section, wiring for extracting a pixel signal from the imaging section, and signal processing for subjecting the pixel signal from the imaging section to predetermined signal processing such as CDS (correlated double sampling), gain control, A / D conversion, etc. A circuit, a drive control circuit that drives each pixel of the imaging pixel unit and controls output of a pixel signal, and the like are provided. And these image pick-up parts and peripheral circuit parts are formed on a flat semiconductor substrate (for example, refer to patent documents 1).
Japanese Patent Laid-Open No. 10-200088 JP 2003-273342 A

However, as in the configuration described in Patent Document 1 and the like, in the imaging element manufacturing process, the wiring metal layer does not exist in the imaging unit, and the wiring metal layer is formed in the peripheral circuit unit outside the imaging unit. For this reason, as shown in FIG. 7, when a signal processing circuit such as an imaging unit and peripheral logic is formed on the same wafer, the height difference H between the upper end of the wiring stack of the signal processing circuit and the upper end of the imaging unit becomes large. It was. When such a height difference H is large, when an optical layer such as a flattening film, a protective film, a color filter layer, or a microlens is formed on the imaging unit after the wiring metal layer is formed, the imaging unit and the peripheral circuit unit Thus, a step corresponding to the laminated thickness of the wiring metal layer is generated. As a result, the thickness of the color filter or the like is uneven, and there is a disadvantage that the uniformity of sensitivity and color tone is lowered.
In addition, if a planarization film is formed so as to completely cover the wiring metal layer of the peripheral circuit section, the planarization film thickness on the imaging section becomes thicker than necessary, so the rate at which received light reaches the photoelectric conversion section Decreases, the sensitivity of the image sensor decreases, and the F value dependency increases. Due to the effect of the step, the thickness of the flattening film differs between the vicinity of the step and the position away from the step, which may cause a characteristic defect that causes uneven sensitivity of the image sensor.
As the functionality of solid-state image sensors increases, multilayer wiring has been promoted in the peripheral circuit portion, and two, three, or more wiring layers tend to be formed, and the above problem becomes more prominent. .
The present invention has been made in view of the above situation. Even when the peripheral circuit portion including the multilayer wiring and the imaging portion are formed on the same wafer, the color difference is reduced by reducing the height difference in the chip. An object of the present invention is to provide a solid-state imaging device capable of suppressing film thickness unevenness such as a filter and maintaining uniformity of sensitivity and color tone.

The above object of the present invention is achieved by the following configuration.
(1) An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, and a signal corresponding to the generated signal charge and an element driving signal are input to the imaging unit. A solid-state imaging device comprising a peripheral circuit unit for outputting,
By forming a field insulating film on the surface of the semiconductor substrate between the imaging unit and the peripheral circuit unit and removing it, the substrate surface height of the peripheral circuit unit is made lower than the substrate surface height of the imaging unit A solid-state imaging device characterized by that.

  According to this solid-state imaging device, the field insulating film is formed on the surface of the semiconductor substrate between the imaging unit and the peripheral circuit unit and is removed, so that the substrate surface height of the peripheral circuit unit is set to the substrate surface height of the imaging unit. Therefore, even if the wiring layer is multi-layered in the peripheral circuit portion and the total film thickness is increased, the height difference from the imaging portion is reduced. In addition, the flattened film thickness on the imaging unit is not increased more than necessary.

(2) The solid-state imaging device according to (1),
A solid-state imaging device, wherein a step portion is formed by lowering the substrate surface height of the peripheral circuit portion further than the substrate surface height of the imaging portion by forming and removing the field insulating film a plurality of times.

  According to this solid-state imaging device, the height difference between the formed step portions can be arbitrarily increased by forming and removing the field insulating film a plurality of times.

(3) The solid-state imaging device according to (1) or (2) 2,
The solid-state imaging device, wherein the peripheral circuit portion has a plurality of wiring layers, and an end portion of the wiring layer on the imaging portion side forms a stepped stepped portion.

  According to this solid-state imaging device, the end of the wiring layer on the imaging unit side forms a stepped stepped portion, so that local steps are reduced and the end of the wiring layer is macroscopically smooth. Can be. Thereby, film-forming quality, such as a film thickness, improves and the sensitivity and color uniformity of a solid-state image sensor are improved more.

(4) An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, and a signal corresponding to the generated signal charge and an element driving signal are input to the imaging unit. A solid-state imaging device comprising a peripheral circuit unit for outputting,
Forming a field insulating film in a region including the peripheral circuit portion leaving the imaging portion on the surface of the semiconductor substrate;
Removing the formed field insulating film;
And a substrate surface height of the peripheral circuit portion is formed to be lower than a substrate surface height of the imaging portion.

  According to this method for manufacturing a solid-state imaging device, a field insulating film is formed on the surface of the semiconductor substrate between the imaging unit and the peripheral circuit unit and removed, and the substrate surface height of the peripheral circuit unit is set to the substrate surface of the imaging unit. Since it is formed lower than the height, even if the wiring layer is multi-layered in the peripheral circuit portion and the total film thickness is increased, the height difference from the imaging portion is reduced. In addition, the flattened film thickness on the image pickup unit is not increased more than necessary.

(5) A method for producing a solid-state imaging device according to (4),
A method of manufacturing a solid-state imaging device, wherein the step of forming and removing the field insulating film is repeated a plurality of times.

  According to this method for manufacturing a solid-state imaging device, it is possible to arbitrarily increase the difference in level of the formed step portion by repeatedly performing the step of forming and removing the field insulating film.

(6) A method for producing a solid-state imaging device according to (5),
A method of manufacturing a solid-state imaging device, wherein the formation starting point of the field insulating film is set so as to be sequentially separated from the imaging unit side every time the field insulating film is repeatedly formed.

  According to this method for manufacturing a solid-state imaging device, a stepped step can be formed on the semiconductor substrate.

(7) The method for manufacturing a solid-state imaging device according to any one of (4) to (6),
When forming an insulating layer on the surface of the semiconductor substrate from which the field insulating film has been removed and forming a wiring layer on the insulating layer, a staircase is provided at the end of the wiring layer between the imaging unit and the peripheral circuit unit. A method of manufacturing a solid-state imaging device, wherein the wiring layer is formed so that a stepped shape is formed.

  According to this method for manufacturing a solid-state imaging device, by forming a stepped step at the end of the wiring layer on the imaging unit side, the local step is reduced and the end of the wiring layer is macroscopically smoothed. Can be. Thereby, film-forming quality, such as a film thickness, improves, and the uniformity of the sensitivity and color tone of a solid-state image sensor are improved more.

According to the present invention, the step portion is provided by forming and removing the field insulating film, and the peripheral circuit portion is formed at a position lower than the imaging portion of the semiconductor substrate. As a result, even when the peripheral circuit portion including the multilayer wiring and the imaging portion are formed on the same wafer, it is possible to suppress unevenness in the film thickness of the color filter or the like and maintain uniformity of sensitivity and color tone. it can.
In the subsequent manufacturing process, an upper film such as a transparent upper planarization layer or an optical layer can be formed at substantially the same height from the imaging unit to the peripheral circuit unit. As a result, the film thickness of the upper layer film is not greatly different between the part in the vicinity of the step part and the part in the vicinity of the step part, and the part in the vicinity of the step part due to the difference in the distance that the received light passes through the upper layer film. It is possible to prevent a difference in sensitivity of the imaging unit between a part separated from the step part. Therefore, the occurrence of uneven sensitivity in the solid-state image sensor is prevented.
Furthermore, by suppressing the increase in the thickness of the imaging unit, the optical path length in each layer is shortened, so that a decrease in light receiving performance such as vignetting can be suppressed, and a decrease in sensitivity and F value dependency can be eliminated.

A preferred embodiment of a solid-state imaging device according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a conceptual plan view of a solid-state imaging device according to the present invention, and FIG. 2 is a partially enlarged cross-sectional view showing a cross section AB of FIG.
As shown in FIG. 1, a solid-state imaging device 100 according to the present invention is formed on a semiconductor substrate 1 that is a silicon substrate, and a plurality of photoelectric conversion units (photodiodes) 11 and signal charges generated by each photoelectric conversion unit 11. A plurality of vertical charge transfer paths 13 for transferring each of them, a horizontal transfer path 15 for receiving and transferring signal charges transferred from the plurality of vertical charge transfer paths 13, and a terminal portion of the horizontal charge transfer path 15 The imaging unit 10 includes an output unit 17 that converts a signal charge that is connected and transferred into a voltage signal and outputs the voltage signal. In addition, the solid-state imaging device 100 includes a peripheral circuit unit 20 including a signal processing circuit that inputs drive signals for performing vertical transfer driving and horizontal transfer driving to the imaging unit 10 and outputs image signals from the imaging unit 10. Have. The peripheral circuit unit 20 is provided in the vicinity of the imaging unit 10 and has an input / output interface function and a signal processing function of the solid-state imaging device 100.

2, the peripheral circuit unit 20 of the solid-state imaging device 100 is formed at a lower position on the semiconductor substrate 1 than the imaging unit 10, and the imaging unit 10 and the peripheral circuit unit A connecting portion 30 is formed to connect different substrate heights to 20.
In the imaging unit 10, a charge transfer electrode 72 made of polysilicon is formed on the silicon substrate 1, and the uppermost layer is covered with the planarizing layer 3.
In the peripheral circuit unit 20, metal wirings 75 are provided on the planarizing layer 3 in a plurality of stages (three stages as an example in the illustrated example), and these metal wirings 75 are covered with an interlayer insulating film 77, and the uppermost layer metal. The wiring 75 is covered with an insulating film 79.

A field insulating film 81 that is a SiO ₂ film is formed on the silicon substrate 1 at the position of the connecting portion 30. The step portion 83 formed by the field insulating film 81 generates a difference between the substrate height H1 of the imaging unit 10 and the substrate height H2 of the peripheral circuit unit 20.

FIG. 3 is a cross-sectional view at the same position as FIG. 2 showing a state in which a plurality of step portions made of a field insulating film are formed.
In this case, the step portions 85 and 87 are formed by the formation of the field insulating film twice, so that the difference between the substrate height H1 of the imaging unit 10 and the substrate height H3 of the peripheral circuit unit 20 is expressed as H2 in FIG. Make it bigger.

Here, a method of making the substrate height H2 of the peripheral circuit unit 20 lower than the substrate height H1 of the imaging unit 10 by using the field insulating film as described above will be described.
FIG. 4 shows the steps (a) to (d) for forming the step portion by the field insulating film in the portions C and D of FIG.
As shown in FIG. 4A, a silicon oxide film 91 is formed on the silicon substrate 1 by thermal oxidation. Then, the silicon nitride film 93 is covered up to the position of the boundary D on the imaging unit 10 side, and the silicon substrate 1 is selectively thermally oxidized through the silicon oxide film 91 by using the silicon nitride film 93 as a mask, thereby LOCOS. A field insulating film 81A called (local oxidation of silicon) is formed.

  Next, as shown in FIG. 4B, all of the formed field insulating film 81, silicon oxide film 91, and silicon nitride film 93 are peeled to expose the surface of the silicon substrate 1 on which the stepped portion 85 is formed. .

  Then, as shown in FIG. 4C, the boundary is shifted from the aforementioned D position to the C position, and the field insulating film 81B is formed again by the same method as in FIG.

  Next, as shown in FIG. 4D, all the layers are peeled again to expose the surface of the silicon substrate 1 on which the new stepped portion 87 is formed.

  As described above, by setting the formation starting point of the field insulating film sequentially away from the imaging unit side every time the field insulating film is repeatedly formed, a stepped step can be formed on the silicon substrate 1. In the illustrated example, an example of two stages is shown. However, the present invention is not limited to this, and an arbitrary number of stages can be used as necessary. Since the stepping method by field oxidation causes little damage to the silicon substrate 1, even if the number of steps is increased, the device characteristics are not affected.

  According to this configuration, even when the peripheral circuit unit 20 is formed as a multilayer wiring due to function addition or the like, since the silicon substrate surface of the peripheral circuit unit 20 is formed in advance lower than the silicon substrate surface of the imaging unit 10, Even if the total film thickness of the circuit unit 20 increases, it is possible to prevent the upper layer film formed on the imaging unit 10 from being unnecessarily thick. As a result, there is no significant difference between the part near the step part and the part away from the step part, and the part near the step part and the part away from the step part due to the difference in the distance that the received light passes through the upper layer film. Therefore, it is possible to prevent a difference in sensitivity of the imaging unit. Therefore, the occurrence of uneven sensitivity in the solid-state image sensor is prevented. In addition, unevenness of color filters, lenses, and the like is reduced, and the sensitivity and color tone uniformity of the solid-state imaging device are improved.

  Since the wiring layer of the peripheral circuit unit 20 is covered from a deeper layer than the imaging unit 10 by a protective layer such as a flattening layer, even when the flattening layer is formed and etched back in the subsequent manufacturing process. The wiring layer of the peripheral circuit unit 20 is not exposed from the planarization layer. This makes it possible to reduce the thickness of the entire element without causing problems such as dielectric breakdown or damage to the wiring layer, and without changing to a manufacturing process that increases the thickness of film formation more than necessary.

  Furthermore, since the increase in the thickness of the imaging unit 10 is suppressed, although not shown, the distance from the photodiode as the light receiving unit to the microlens as the surface layer can be shortened, and the optical path length in each layer is shortened. Light absorption is reduced, and a decrease in light receiving performance such as light vignetting due to a light shielding film or a transfer electrode can be suppressed. Thereby, a sensitivity fall and F value dependency can be eliminated.

Further, by forming the connection portion 30 between the pixel portion 10 and the peripheral circuit portion 20, a wiring can be formed on the inclined surface of the connection portion 30. For example, a through hole is formed to achieve conduction. Compared with the configuration, the wiring structure can be greatly simplified.

  The above-mentioned effects are not limited to the CCD solid-state image sensor, but are the same for, for example, a CMOS solid-state image sensor.

Next, another embodiment of the solid-state imaging device according to the present invention will be described.
FIG. 5 is a cross-sectional view showing a state in which the end portion of the interlayer insulating film in the peripheral circuit portion shown in FIG. 3 is stepped.
As shown in FIG. 5, after the planarization layer 3 is formed as an insulation layer on the surface of the silicon substrate 1 from which the field insulation film has been removed, the imaging unit 10 is formed when an interlayer insulation film 77 is formed on the planarization layer 3. A stepped step is formed at the end of the interlayer wiring layer 77 between the peripheral circuit portion 20 and the peripheral circuit portion 20. That is, when the interlayer insulating film 77 is patterned by etching, the thick film is gradually formed from the imaging unit 10 toward the peripheral circuit unit 20 by performing mask processing while shifting the boundary position between the imaging unit 10 and the peripheral circuit unit 20. The step-like stepped portions E1, E2, E3 are formed.

  According to this configuration, the imaging unit 10 and the peripheral circuit unit 20 are smoothly connected macroscopically by the stepped portions E1, E2, and E3 of the interlayer insulating film 77. Thereby, local steps are reduced, film formation quality in the subsequent manufacturing process is improved, and sensitivity and color tone uniformity of the solid-state imaging device are further improved.

Here, FIG. 6 shows a configuration example in the vicinity of the output unit for the solid-state imaging device having the above configuration.
FIG. 6 is an enlarged plan view of the main part of the end portion of the horizontal transfer path 15 and the output unit 17 (see FIG. 1).
The channel region CH of the horizontal charge transfer path 15 gradually decreases in width as it approaches the end and eventually becomes a constant width so as to surround the high concentration impurity region 31 of the floating diffusion FD. A first polycrystalline silicon transfer electrode P1 and a second polycrystalline silicon transfer electrode P2 are disposed above the channel region CH.

An output gate electrode 33 is formed of a polycrystalline silicon layer on the left side of the leftmost first polycrystalline transfer electrode P1. An N ⁺ type high concentration impurity region 31 of the floating diffusion FD is formed in the channel region CH at a certain distance from the output gate 33. A silicon oxide layer is formed on the surface of the silicon substrate 1 and has an opening on the high concentration impurity region 31.

  On the other hand, a wiring 35 made of a buried impurity diffusion layer is formed at a position adjacent to the channel region CH. The high concentration impurity region 31 of the FD is connected to one end side of the gate electrode 37 through the opening of the silicon oxide layer, and the other end side of the gate electrode 37 is disposed on the wiring 35. The wiring 35 includes a wiring 35A connected to the source potential VSS and a wiring 35B to the output drain OD (drain potential VDD).

  Further, a reset transistor 39 is formed ahead of the high concentration impurity region 31 in order to reset and discard the charge transferred to the FD region. That is, the channel region CH extends beyond the high concentration impurity region 31, and the gate electrode 41 to the reset gate RS is formed so as to cross the extended channel region CH. A wiring 43 to the reset drain RD is formed on the left side of the channel region CH with the electrode 41 to the reset gate RS interposed therebetween. A wire 45 to the reset gate RS is connected to the end of the electrode 41 opposite to the channel region CH. By applying a voltage to the reset drain RD and applying a voltage to the reset gate RS to extract the charge of the floating diffusion FD, the charge of the floating diffusion FD is cleared. Note that the line width, shape, area, and the like of the gate electrode and wiring shown in FIG. 6 are conceptually shown and are not accurate.

  The wirings 35A, 35B, 43, and 45 extend to the peripheral circuit unit 20 through the connection unit 30, and are connected to the output drain OD, the reset drain RD, the reset gate RS, and the like in the peripheral circuit unit 20.

The connection part 30 between the imaging part 10 and the peripheral circuit part 20 is formed by ion implantation of As ⁺ or P ⁺ along the inclined surface of the silicon substrate formed by the field insulating film as described above. In addition, wirings 35A, 35B, 43, and 45 (these wirings are an example of an output unit, and there are a plurality of other wirings) made of an N-type high-concentration impurity diffusion layer. An appropriate insulating layer is interposed between the silicon substrate and the wirings 35A, 35B, 43, and 45.

Further, each of the wirings 35A, 35B, 43, and 45 is made of polysilicon, wiring made of metal wiring such as aluminum, refractory metal such as W, Mo, or a combination thereof, instead of wiring made of an impurity diffusion layer. It can also be formed. According to this configuration, the manufacturing process can be simplified.

  As described above, in the solid-state imaging device of the present invention, the peripheral circuit unit is formed at a position lower than the imaging unit of the semiconductor substrate, and the peripheral circuit unit including the stacked wiring and the imaging unit are formed on the same wafer. Even in this case, since the unevenness in the thickness of the color filter or the like can be suppressed by reducing the height difference in the chip, the sensitivity and color tone uniformity of the solid-state imaging device can be maintained. Further, it is possible to suppress a decrease in light receiving performance such as vignetting in the imaging unit, and it is possible to eliminate a sensitivity decrease and F value dependency. Therefore, the present invention can be applied to a solid-state imaging device such as a high-quality digital camera.

1 is a conceptual plan view of a solid-state imaging device according to the present invention. It is a partially expanded sectional view which shows the AB cross section shown in FIG. It is sectional drawing of the same position as FIG. 2 which shows a mode that multiple step parts by a field insulating film were formed. It is explanatory drawing which shows the formation procedure (a)-(d) of the step part by the field insulating film in the C, D part of FIG. It is sectional drawing which shows a mode that the edge part of the interlayer insulation film in the peripheral circuit part shown in FIG. 3 was made into step shape. It is a principal part enlarged plan view of the termination | terminus part and output part of a horizontal transfer path. It is sectional drawing which shows the structural example of the conventional solid-state image sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Flattening layer 10 Image pick-up part 11 Photoelectric conversion part 13 Vertical charge transfer path 15 Horizontal charge transfer path 17 Output part 20 Peripheral circuit part 30 Connection part 31 High concentration impurity area | region 33 Output gate electrode 35, 35A, 35B wiring 37 Gate electrode 39 Reset transistor 41 Gate electrode 43 Wiring to reset drain 45 Wiring to reset gate 75 Metal wiring 77 Interlayer insulating film 79 Insulating film 81 Field insulating film 83, 85, 87 Step 91 Silicon oxide film 93 Silicon nitride film 100 Solid-state image sensor CH channel region E1, E2, E3 Stepped part

Claims (7)

An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, and a peripheral that inputs / outputs a signal corresponding to the generated signal charge and an element driving signal to the imaging unit A solid-state imaging device comprising a circuit unit,
By forming a field insulating film on the surface of the semiconductor substrate between the imaging unit and the peripheral circuit unit and removing it, the substrate surface height of the peripheral circuit unit is made lower than the substrate surface height of the imaging unit A solid-state imaging device characterized by that. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a step portion is formed by lowering the substrate surface height of the peripheral circuit portion further than the substrate surface height of the imaging portion by forming and removing the field insulating film a plurality of times. The solid-state imaging device according to claim 1 or 2,
The solid-state imaging device, wherein the peripheral circuit portion has a plurality of wiring layers, and an end portion of the wiring layer on the imaging portion side forms a stepped stepped portion. An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, and a peripheral that inputs / outputs a signal corresponding to the generated signal charge and an element driving signal to the imaging unit A solid-state imaging device comprising a circuit unit,
Forming a field insulating film in a region including the peripheral circuit portion leaving the imaging portion on the surface of the semiconductor substrate;
Removing the formed field insulating film;
And a substrate surface height of the peripheral circuit portion is formed to be lower than a substrate surface height of the imaging portion. It is a manufacturing method of the solid-state image sensing device according to claim 4,
A method of manufacturing a solid-state imaging device, wherein the step of forming and removing the field insulating film is repeated a plurality of times. It is a manufacturing method of the solid-state image sensing device according to claim 5,
A method of manufacturing a solid-state imaging device, wherein the formation starting point of the field insulating film is set so as to be sequentially separated from the imaging unit side every time the field insulating film is repeatedly formed. It is a manufacturing method of the solid-state image sensing device according to any one of claims 4 to 6,
When forming an insulating layer on the surface of the semiconductor substrate from which the field insulating film has been removed and forming a wiring layer on the insulating layer, a staircase is provided at the end of the wiring layer between the imaging unit and the peripheral circuit unit. A method of manufacturing a solid-state imaging device, wherein the wiring layer is formed so that a stepped shape is formed.

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