JP2008191701A - Method of recovery from error and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it takes time to replace an error block of a NAND-type flash memory, thereby hindering high-speed reading of data stored in the flash memory. <P>SOLUTION: If the read data contains an error, it is corrected using redundant data stored together with the data, and error correction information is output including the data corrected and information for specifying the block that stores the data. A second application that is started later writes, in an available, unused block of the flash memory, the corrected data included in the error correction information, and replaces this error block with the unused block. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for recovering an error that has occurred in a NAND flash memory, and more particularly to an error recovery processing method when priority is given to a process for reading stored data.

  As a semiconductor storage medium for information equipment, a NAND flash memory that can easily be increased in capacity is used. In this type of flash memory, data is stored, read and erased in units of blocks. In addition, NAND flash memory has a limited number of rewrites due to its structure. For this reason, an ECC (Error Correcting Code) is added in order to compensate for stored data, and a mechanism is provided that can recover when an error is found in the read data. A block in which an error is found needs to be replaced with another block so that it is not used for data storage.

  However, it is not known that there is an error in the block unless it is read from the flash memory, and the replacement process for the block in which the error is found requires a write operation separately from the read operation, which takes extra time. Even if an error is detected at the time of reading, if a substitute process is performed each time, it takes a long time to read all necessary data, which may hinder high-speed processing.

  In addition, when reading software with a small footprint that omits the writing function, such as when starting up the OS, is necessary, the replacement process itself cannot be implemented, and if it is not read by another means after that, the opportunity to be restored is lost, As a result, there may be a case where reliability is lowered.

An invention has been disclosed in which, when an error is found in data stored in a NAND flash memory, data is read while the data is restored by ECC (see Patent Document 1).
JP-A-2005-190201

  The error block replacement process of the NAND flash memory takes time, and prevents data stored in the flash memory from being read at high speed.

  The present invention has been made in view of the above problems, and provides an error recovery processing method and an information processing apparatus capable of reading data stored in a NAND flash memory at a high speed without omitting a replacement process of a found error block. To do.

The error recovery processing method of the present invention
An error recovery processing method for an error block in a flash memory accessed in units of blocks, wherein the first application reads data stored in the flash memory by a first access driver, and the read data has an error. The first access driver corrects using the redundant data stored together with the data, and outputs error correction information including the correction data and information specifying the block in which the data is stored, If the error correction information exists, the second application started after the first application is included in the error free information in the unused block of the flash memory that is used by the second access driver. Write the correction data and correct this error And performing error block recovery process to replace the block of the flash memory that is identified in the block of the unused based on distribution.

If the information processing apparatus of the present invention is used,
When an error is found in the data of a block that has been accessed and read in block units, the information processing apparatus is equipped with a flash memory that requires recovery processing of the block, and reads the data stored in the flash memory If an error is found in the read data, this function corrects this data correctly and outputs error correction information including information that identifies the block in which this data was stored and the corrected data after correction A first access driver, processing means for reading predetermined data from the flash memory via the first access driver, and an unused block in the flash memory when the error correction information is present The correction data included in the error correction information is written in A second access driver that performs error block recovery processing for replacing the block of the flash memory specified based on error correction information with the unused block, and after the read processing by the processing means, An information processing apparatus is provided that performs error block recovery processing by the access driver.

  Provided are an error recovery processing method and an information processing apparatus capable of reading data at high speed without omitting a replacement process of a memory block in which an error is found.

  FIG. 1 is a diagram illustrating an example of a block configuration diagram of the information processing apparatus according to the present embodiment. In FIG. 1, a CPU 100, a NOR flash memory 101, a RAM 102, a NAND flash memory 104, an IO controller 105, and an internal bus 106 are shown.

  The CPU 100 is an arithmetic processing unit that performs predetermined processing in accordance with a program code created for the CPU (Central Processing Unit).

  The NOR flash memory 101 is a nonvolatile NOR flash memory. The NOR flash memory has a higher access speed than the NAND flash memory and can be randomly accessed in units of 1 byte. In this embodiment, a program code processed by the CPU 100 is stored in a small-capacity NOR flash memory 101 instead of a large-capacity storage device such as an HDD (Hard Disk Drive), thereby reducing power consumption, earthquake resistance, Improve the environment. Such a configuration is advantageous in mobile devices such as those for incorporation into specific devices and PDAs (Personal Digital Assistants).

  The RAM 102 is composed of a volatile semiconductor memory such as DRAM (Dynamic Random Access Memory). While large capacity and high-speed access are possible, the stored contents are lost when the power is turned off. It is mainly used as a temporary storage area when the CPU 100 processes the program code.

  The NAND flash memory 103 is a non-volatile NAND type flash memory. Unlike NOR-type flash memory, this flash memory is suitable for large capacity because it has a fast data erasing and writing speed. On the other hand, since access is performed in units of blocks, it is often used as a substitute for storage media such as HDDs. In addition, there is a limit to the number of times of rewriting data to be stored, and if it exceeds that, the stored data cannot be read normally. Therefore, for the block in which an error has occurred, the data stored in the block is moved to another vacant block, and thereafter a bad block mark is written as a mark not to be used for data writing. This series of processing is called error block recovery processing. In addition, it takes more time to complete data writing than reading stored data.

  The IO controller 104 has a function of controlling input / output of data to the NAND flash memory 103.

  The internal bus 105 has a function for connecting the above-described components and realizing data exchange between them.

  Next, the operation of the information processing apparatus will be described based on the drawings.

  FIG. 2 is a diagram for explaining a first operation of the module configuration diagram according to the present embodiment. FIG. 2 shows data and module configurations stored in each block shown in the block configuration diagram of the information processing apparatus according to the present embodiment.

  The boot loader 200 has a function of performing a minimum initial setting of each unit when starting up the information processing apparatus and loading an original program that runs on the information processing apparatus.

  The NAND access driver 201 has a function of reading data in the NAND flash memory 103 by controlling the IO controller 104. When reading data, the ECC stored in the NAND flash memory 103 is used to restore the data to be read as necessary. In addition, when data is repaired, it has a function of separately storing the repair block identification information and the repaired data.

  The OS image 202 is a program such as an OS (Operating System) that should be originally processed by the information processing apparatus, and can be executed by the CPU 100 with the support of the boot loader 200. For example, since the NAND flash memory 103 is accessed in units of blocks, the NAND flash memory 103 is not suitable for use as the main memory of the CPU 100 and needs to be once loaded into another memory.

  The NAND access driver 203 implements access to the NAND flash memory 103 in the same manner as the NAND access driver 201, but provides all functions necessary for the NAND flash memory 103 such as a write function and an error block recovery processing function in addition to the read function. I have.

  At the beginning of the boot of the information processing apparatus, the CPU 100 executes the boot loader 200 stored in the NOR flash memory 101 and completes various initial settings.

  FIG. 3 is a diagram for explaining a second operation of the module configuration diagram according to the present embodiment.

  After completing the initial setting, the boot loader 200 reads the OS image 202 stored in the NAND flash memory 103 via the NAND access driver 201, and restores the read data if necessary. This data is copied as an OS image 300 onto the RAM 102 via the internal bus 105.

  At this time, if there is data restored by the NAND access driver 201, the restored data and identification information of the block in which the NAND flash memory 103 has an error are recorded as ECC error correction information 302. In this embodiment, the ECC error correction information 302 is stored on the RAM 102, but may be stored anywhere as long as the storage medium can be accessed from the OS.

  FIG. 4 is a diagram for explaining a third operation of the module configuration diagram according to the present embodiment.

  When the boot loader 200 finishes copying the OS image 202 as the OS image 300, the boot loader 200 starts processing the OS image 300 copied to the RAM 102.

In the processing of the OS image 300, initial setting processing for starting up the OS is first executed. In this initial setting process, the NAND access driver 301 refers to the ECC error correction information 302 if necessary, and performs error block recovery processing of the NAND flash memory 103 including block replacement processing according to the identification information therein. To do.

  FIG. 5 is a diagram showing an example of ECC error correction information 302 according to the present embodiment.

The ECC error correction information 302 is mainly composed of two pieces of information. One is the number of pages in error (the number of error pages is 500), and the other is error page information. The number of error pages 500 is zero if there is no page that causes an error during reading. Alternatively, the ECC error correction information 302 itself is not created.

The error page information includes a set of a page identification number 501, redundant data 502 and corrected data 503. The page identification number 501 stores a page identification number indicating a page having an error. The corrected data 503 stores data after being repaired based on the ECC added to the page where the error is found. In the case of NAND flash memory, an area of 512 bytes length is usually taken. Redundant data 502 is an ECC for the repaired data stored in the corrected data 503. ECC usually takes an area of 16 bytes.

  At this time, when there are a plurality of pages where an error is found, the total number of repaired pages is stored in the error page number 500, and error page information is repeatedly stored by that number.

  FIG. 6 is a diagram illustrating an example of an operation flow of the information processing apparatus according to the present embodiment.

First, the CPU 100 executes the boot loader 200 stored in the NOR flash memory 101 (step S01).

Subsequently, one page of the OS image 202 stored in the NAND flash memory 103 is read via the NAND access driver 201 built in the boot loader 200 (step S02). At this time, it is determined whether or not an error has occurred in the read data based on the ECC (step S03).

If an error has occurred (Yes), a process of correcting the error using the ECC (ECC error correction process) is performed (step S04), and correct data is restored. Then, the identification information of the page in error, the restored data, and the ECC of the restored data are calculated, and ECC error correction information 302 is created (step S05). The restored data is copied to the RAM 102 (step S06).

  If no error occurs in step S03 (No), the read data is copied to the RAM 102 as it is (step S06).

  If a page for storing the OS image 202 remains (No in step S07), the process from step S02 is repeated to read the next page.

  When all pages have been read (Yes), the boot loader 200 starts processing the OS image 300 copied on the RAM (step S08).

  In the OS image 300, initial setting processing for operating the OS is first described. In this initial setting process, an error block recovery process is performed on the NAND flash memory 103 if necessary.

  First, it is determined whether ECC error correction information 302 has been created on the RAM 102 (step S09). If it has been created (Yes), the unused flash memory 103 is searched for available unused blocks by the number indicated by the number of error pages 500, and the redundant data 502 and post-correction data 503 of the read ECC error correction information 302 are searched. The data of the block including the page including the page is written (step S10) and replaced with the block including the page identification number 501. The original block including the page indicated by the page identification number 501 is determined to have low reliability, and a bad block mark is set so that it will not be used for data storage thereafter (step S11).

  When the initial setting process including the one process so far is completed, the function shifts to the original function of the OS (step S12).

  In the present embodiment, as described above, the data created as the ECC error correction information 302 after the restoration of the page having an error at the time of reading is used for the error block recovery process. As a result, it is possible to avoid the risk of having to read again the data of the unstable page of the flash memory that has once caused an error.

  By adopting such a series of configurations, an error recovery processing method and information processing apparatus that can read data stored in the NAND flash memory at high speed without omitting the replacement processing of the memory block in which the error is found are realized. can do.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a figure which shows an example of the block block diagram of the information processing apparatus concerning this embodiment. It is a figure explaining the 1st operation of the module block diagram concerning this embodiment. It is a figure explaining the 2nd operation of the module block diagram concerning this embodiment. It is a figure explaining the 3rd operation of the module block diagram concerning this embodiment. It is a figure which shows an example of the ECC error correction information concerning this embodiment. It is a figure which shows an example of the operation | movement flow of the information processing apparatus concerning this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... CPU, 101 ... NOR flash memory, 102 ... RAM, 103 ... NAND flash memory, 104 ... IO controller, 105 ... Internal bus, 200 ... Boot loader, 201. ..NAND access driver 202 ... OS image 203 ... NAND access driver 300 ... OS image 301 ... NAND access driver 302 ... ECC error correction information

Claims (5)

An error block error recovery processing method in flash memory accessed in block units,
The first application reads the data stored in the flash memory by the first access driver,
When there is an error in the read data, the first access driver corrects it using the redundant data stored together with the data, and includes the correction data and information for specifying the block in which the data is stored. Output error correction information,
When the error correction information is present, the second application started after the first application is included in the error free information in the unused block of the flash memory that is used by the second access driver. An error recovery processing method comprising writing the correction data, and performing error block recovery processing for replacing the block of the flash memory specified based on the error correction information with the unused block. When the first access driver outputs the error correction information, redundant data calculated from the correction data is further added to the error correction information;
2. The error recovery processing method according to claim 1, wherein when the second access driver performs the error block recovery process, the added redundant data is written as redundant data of the unused block. When an error is found in the data of a certain block that is accessed and read in block units, the information processing apparatus is equipped with a flash memory that requires recovery processing of the block,
A function for reading data stored in the flash memory is provided. When an error is found in the read data, the data is corrected correctly, and information for specifying the block in which the data is stored and correction after correction A first access driver that outputs error correction information including data;
Processing means for reading predetermined data from the flash memory via the first access driver;
When the error correction information exists, the correction data included in the error correction information is written to an available unused block of the flash memory, and the block of the flash memory specified based on the error correction information A second access driver that performs error block recovery processing for replacing the unused block with the unused block,
An information processing apparatus, wherein after the read processing by the processing means, error block recovery processing is performed by the second access driver.   4. The information processing apparatus according to claim 3, wherein the data correction performed by the first access driver is performed using redundant data added to data in which an error is found. When the first access driver outputs the error correction information, redundant data calculated from the correction data is further added to the error correction information;
4. The information processing apparatus according to claim 3, wherein when the second access driver performs the error block recovery process, the added redundant data is written as redundant data of the unused block.

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