JP2008181039A - Display device, method for driving display device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably write an input signal voltage while preventing a decrease in the luminance accompanying a decrease in a gate-source voltage in a drive transistor caused by coupling of a writing transistor in an off period. <P>SOLUTION: A power supply for a final stage buffer 431 is separated from a power supply for of a circuit section in the preceding stage in an output circuit 43 of a writing scanning circuit; a power supply voltage Vdd2 that slowly falls than the falling of an input pulse in the final stage buffer 431 is generated in a Vdd2 power supply circuit 83; the voltage is supplied as the power source of the final stage buffer 431 to generate writing pulses WS (WS1 to WSm) at a lower falling rate than the falling rate of the input pulse A; and an input signal voltage is sampled by the writing pulse WS. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, a display device driving method, and an electronic apparatus, and more particularly to a flat (flat panel) display device in which pixels including electro-optical elements are arranged in a matrix (matrix shape), and the display device And an electronic apparatus using the display device.

  In recent years, in the field of display devices that perform image display, a flat display device in which pixels (pixel circuits) including light emitting elements are arranged in a matrix, for example, as a light emitting element of a pixel, according to a current value flowing through the device. So-called current-driven electro-optic elements whose emission brightness changes, for example, organic EL display devices using organic EL (Electro Luminescence) elements utilizing the phenomenon of light emission when an electric field is applied to an organic thin film have been developed and commercialized. It is being advanced.

  This organic EL display device has low power consumption because the organic EL element can be driven with an applied voltage of 10 V or less, and is a self-luminous element. Therefore, a light source ( Compared with a liquid crystal display device that displays an image by controlling the light intensity from the backlight), the image is highly visible, and the liquid crystal display device does not require an illumination member such as a backlight. Easy to reduce weight and thickness. Furthermore, since the response speed of the element is as high as about several μsec, no afterimage is generated when displaying a moving image.

  In the organic EL display device, as in the liquid crystal display device, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although a simple matrix display device has a simple structure, there is a problem that it is difficult to realize a large and high-definition display device. Therefore, in recent years, the current flowing through the electro-optical element is controlled by an active element provided in the same pixel circuit as the electro-optical element, for example, an insulated gate field effect transistor (generally, a TFT (Thin Film Transistor)). Active matrix display devices have been actively developed.

  By the way, it is generally known that the IV characteristic (current-voltage characteristic) of the organic EL element is deteriorated with time (so-called deterioration with time). In a pixel circuit using an N-channel TFT as a transistor for driving an organic EL element with current (hereinafter referred to as “driving transistor”), the organic EL element is connected to the source side of the driving transistor. When the IV characteristic of the organic EL element deteriorates with time, the gate-source voltage Vgs of the driving transistor changes, and as a result, the emission luminance of the organic EL element also changes.

  This will be described more specifically. The source potential of the drive transistor is determined by the operating point between the drive transistor and the organic EL element. When the IV characteristic of the organic EL element deteriorates, the operating point of the driving transistor and the organic EL element fluctuates. Therefore, even if the same voltage is applied to the gate of the driving transistor, the source potential of the driving transistor changes. . As a result, since the source-gate voltage Vgs of the drive transistor changes, the value of the current flowing through the drive transistor changes. As a result, since the value of the current flowing through the organic EL element also changes, the light emission luminance of the organic EL element changes.

  In addition, in a pixel circuit using a polysilicon TFT, in addition to the deterioration over time of the IV characteristics of the organic EL element, the threshold voltage Vth of the driving transistor and the mobility μ of the semiconductor thin film constituting the channel of the driving transistor are changed over time. The threshold voltage Vth and the mobility μ vary from pixel to pixel due to variations in manufacturing processes (individual transistor characteristics vary). When the threshold voltage Vth and mobility μ of the driving transistor are different, the current value flowing through the driving transistor varies, so even if the same voltage is applied to the gate of the driving transistor, the light emission luminance of the organic EL element varies between pixels. Variations occur and the uniformity of the screen is lost.

  Therefore, even if the IV characteristic of the organic EL element deteriorates with time, or the threshold voltage Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element is not affected by those effects. In order to keep constant, the compensation function for the characteristic variation of the organic EL element, the correction for the variation of the threshold voltage Vth of the driving transistor (hereinafter referred to as “threshold correction”), the mobility μ of the driving transistor Each pixel circuit is provided with a correction function for correction of fluctuations (hereinafter referred to as “mobility correction”) (see, for example, Patent Document 1).

JP 2006-133542 A

  In the prior art described in Patent Document 1, each pixel circuit is provided with a compensation function for a characteristic variation of the organic EL element and a correction function for a variation in threshold voltage Vth and mobility μ of the drive transistor, so that Even if the IV characteristics deteriorate over time or the threshold voltage Vth and mobility μ of the driving transistor change over time, the light emission luminance of the organic EL element can be kept constant without being affected by them. .

  By the way, the writing of the input signal voltage is performed by the writing transistor sampling the input signal voltage under the driving by the writing pulse. However, when the falling speed of the writing pulse is fast (the writing pulse becomes steep). When the write transistor is turned off, the gate potential of the drive transistor is drastically lowered due to coupling when the write transistor is turned off, and the gate-source voltage Vgs of the drive transistor is lowered (shrinks) accordingly. Therefore, there is a problem in that the luminance is reduced by the amount of decrease in the gate-source voltage Vgs.

  Therefore, the present invention can stably perform input signal voltage writing while preventing a decrease in luminance due to a decrease in gate-source voltage of the driving transistor due to coupling when the writing transistor is turned off. An object is to provide a display device, a driving method of the display device, and an electronic device using the display device.

  In order to achieve the above object, in the present invention, an electro-optic element, a write transistor that samples and writes an input signal voltage, a storage capacitor that holds the input signal voltage written by the write transistor, and the storage capacitor A pixel array unit in which pixels including a driving transistor for driving the electro-optic element based on the held input signal voltage are arranged in a matrix, and a final stage buffer in which a power supply is separated from a circuit part on the previous stage side And a scanning circuit that selectively scans each pixel of the pixel array unit in a row unit by applying a write pulse based on the input pulse of the final stage buffer to the write transistor. Supply the power supply voltage of the falling speed slower than the falling speed to the power supply of the last stage buffer So as to fall the write pulse at the fall of the supply voltage by Rukoto.

  In the display device having the above-described configuration and the electronic apparatus using the display device, the falling speed of the power supply voltage supplied to the power supply of the final stage buffer is made slower than the falling speed of the input pulse of the final stage buffer. The falling speed of the write pulse output from the final stage buffer becomes slower than the falling speed of the input pulse, that is, the write pulse falls gently. Accordingly, a decrease in the gate potential of the drive transistor due to coupling when the write transistor is turned off can be suppressed, so that a decrease in the gate-source voltage of the drive transistor can be suppressed.

  According to the present invention, since it is possible to suppress a decrease in the gate-source voltage of the driving transistor due to the coupling when the writing transistor is turned off, it is possible to prevent a decrease in luminance due to the decrease in the gate-source voltage. However, the input signal voltage can be stably written.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a system configuration diagram showing an outline of the configuration of an active matrix display device according to an embodiment of the present invention. Here, as an example, a case of an active matrix type organic EL display device using a current-driven electro-optical element whose emission luminance changes according to a current value flowing through the device, for example, an organic EL element as a pixel light-emitting element is taken as an example. Will be described.

  As shown in FIG. 1, the organic EL display device 10 according to this embodiment includes a pixel array unit 30 in which pixels (PXLC) 20 are two-dimensionally arranged in a matrix (matrix shape), and the pixel array unit 30. A driving unit that is arranged in the periphery and drives each pixel 20, for example, a writing scanning circuit 40, a power supply scanning circuit 50, and a horizontal driving circuit 60 is configured.

  The pixel array unit 30 is provided with scanning lines 31-1 to 31-m and power supply lines 32-1 to 32-m for each pixel row with respect to a pixel array of m rows and n columns. The signal lines 33-1 to 33-n are wired.

  The pixel array unit 30 is usually formed on a transparent insulating substrate such as a glass substrate, and has a flat (flat) panel structure. Each pixel 20 of the pixel array unit 30 can be formed using an amorphous silicon TFT (Thin Film Transistor) or a low-temperature polysilicon TFT. When the low-temperature polysilicon TFT is used, the scanning circuit 40, the power supply scanning circuit 50, and the horizontal driving circuit 60 can also be mounted on the display panel (substrate) 70 that forms the pixel array section 30.

  The writing scanning circuit 40 is configured by a shift register or the like, and sequentially supplies scanning signals WS1 to WSm to the scanning lines 31-1 to 31-m when writing video signals to the respective pixels 20 of the pixel array unit 30. 20 is line-sequentially scanned in units of rows.

  The power supply scanning circuit 50 is constituted by a shift register or the like, and is synchronized with the line sequential scanning by the write scanning circuit 40 and switches between a first potential Vccp and a second potential Vini lower than the first potential Vccp. DS1 to DSm are supplied to the power supply lines 32-1 to 32-m. Here, the second potential Vini is a potential sufficiently lower than the offset voltage Vofs given from the horizontal drive circuit 60.

  The horizontal drive circuit 60 appropriately selects one of the signal voltage Vsig and the offset voltage Vofs of the video signal according to the luminance information supplied from a signal supply source (not shown), and the signal lines 33-1 to 33-33. For example, data is written all at once to each pixel 20 of the pixel array unit 30 via n. That is, the horizontal drive circuit 60 employs a line-sequential writing drive mode in which the input signal voltage Vsig is written all at once in a row (line) unit.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating a specific configuration example of the pixel (pixel circuit) 20. As shown in FIG. 2, the pixel 20 includes a current-driven electro-optical element, for example, an organic EL element 21, whose light emission luminance changes according to a current value flowing through the device, and the organic EL element 21 includes In addition, the driving transistor 22, the writing transistor 23, the storage capacitor 24, and the auxiliary capacitor 25 are provided.

  Here, N-channel TFTs are used as the drive transistor 22 and the write transistor 23. However, the combination of the conductivity types of the driving transistor 22 and the writing transistor 23 here is only an example, and is not limited to these combinations.

  The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all the pixels 20. The drive transistor 22 has a source connected to the anode electrode of the organic EL element 21 and a drain connected to the power supply line 32 (32-1 to 32-m).

  The writing transistor 23 has a gate connected to the scanning line 31 (31-1 to 31-m), a source connected to the signal line 33 (33-1 to 33-n), and a drain connected to the gate of the driving transistor 22. Has been. The storage capacitor 24 has one end connected to the gate of the drive transistor 22 and the other end connected to the source of the drive transistor 22 (the anode electrode of the organic EL element 21).

  The auxiliary capacitor 25 has one end connected to the source of the drive transistor 22 and the other end connected to the cathode electrode (common potential supply line 34) of the organic EL element 21. The auxiliary capacitor 25 is connected in parallel to the organic EL element 21 to compensate for the capacity shortage of the organic EL element 21. That is, the auxiliary capacitor 25 is not an essential component, and the auxiliary capacitor 25 can be omitted when the capacity of the organic EL element 21 is sufficient.

  In the pixel 20 having such a configuration, the writing transistor 23 is supplied from the horizontal driving circuit 60 through the signal line 33 by being turned on in response to the scanning signal WS applied to the gate from the writing scanning circuit 40 through the scanning line 31. The input signal voltage Vsig or the offset voltage Vofs of the video signal corresponding to the luminance information is sampled and written into the pixel 20. The written input signal voltage Vsig or offset voltage Vofs is held in the holding capacitor 24.

  When the potential DS of the power supply line 32 (32-1 to 32-m) is at the first potential Vccp, the driving transistor 22 is supplied with current from the power supply line 32 and is held in the storage capacitor 24. By supplying the organic EL element 21 with a drive current having a current value corresponding to the voltage value of the input signal voltage Vsig, the organic EL element 21 is driven by current.

(Pixel structure)
FIG. 3 shows an example of a cross-sectional structure of the pixel 20. As shown in FIG. 3, in the pixel 20, an insulating film 202 and a window insulating film 203 are formed on a glass substrate 201 on which pixel circuits such as a driving transistor 22 and a writing transistor 23 are formed, and a concave portion of the window insulating film 203 is formed. The organic EL element 21 is provided in 203A.

  The organic EL element 21 includes an anode electrode 204 made of metal or the like formed on the bottom of the recess 203A of the window insulating film 203, and an organic layer (electron transport layer, light emitting layer, hole transport) formed on the anode electrode 204. Layer / hole injection layer) 205 and a cathode electrode 206 made of a transparent conductive film or the like formed on the organic layer 205 in common for all pixels.

  In the organic EL element 21, the organic layer 208 is formed by sequentially depositing a hole transport layer / hole injection layer 2051, a light emitting layer 2052, an electron transport layer 2053 and an electron injection layer (not shown) on the anode electrode 204. It is formed. Then, current flows from the drive transistor 22 to the organic layer 205 through the anode electrode 204 under current drive by the drive transistor 22 in FIG. 2, whereby electrons and holes are recombined in the light emitting layer 2052 in the organic layer 205. It is designed to emit light.

  As shown in FIG. 3, after the organic EL elements 21 are formed on the glass substrate 201 on which the pixel circuit is formed via the insulating film 202 and the window insulating film 203 in units of pixels, the organic EL element 21 is interposed via the passivation film 207. The sealing substrate 208 is bonded by the adhesive 209, and the organic EL element 21 is sealed by the sealing substrate 208, whereby the display panel 70 is formed.

(Threshold correction function)
Here, the power supply scanning circuit 50 supplies power while the horizontal drive circuit 60 supplies the offset voltage Vofs to the signal lines 33 (33-1 to 33-n) after the writing transistor 23 is turned on. The potential DS of the line 32 is switched between the first potential Vccp and the second potential Vini. By switching the potential DS of the power supply line 32, a voltage corresponding to the threshold voltage Vth of the drive transistor 22 is held in the holding capacitor 24.

  The voltage corresponding to the threshold voltage Vth of the driving transistor 22 is held in the holding capacitor 24 for the following reason. Due to variations in the manufacturing process of the drive transistor 22 and changes over time, transistor characteristics such as the threshold voltage Vth and mobility μ of the drive transistor 22 vary for each pixel. Due to this variation in transistor characteristics, even if the same gate potential is applied to the drive transistor 22, the drain-source current (drive current) Ids varies from pixel to pixel, resulting in variations in light emission luminance. In order to cancel (correct) the influence of the variation in threshold voltage Vth for each pixel, a voltage corresponding to the threshold voltage Vth is held in the holding capacitor 24.

  The threshold voltage Vth of the driving transistor 22 is corrected as follows. That is, by holding the threshold voltage Vth in the storage capacitor 24 in advance, the threshold voltage Vth of the drive transistor 22 is held in the storage capacitor 24 when the drive transistor 22 is driven by the input signal voltage Vsig. In other words, the threshold voltage Vth is corrected.

  This is the threshold correction function. With this threshold correction function, even if the threshold voltage Vth varies or changes with time for each pixel, the light emission luminance of the organic EL element 21 can be kept constant without being influenced by the threshold voltage Vth. The principle of threshold correction will be described in detail later.

(Mobility correction function)
The pixel 20 shown in FIG. 2 has a mobility correction function in addition to the threshold correction function described above. That is, the scanning signal WS (WS1 to WS1) output from the writing scanning circuit 40 during the period in which the horizontal driving circuit 60 supplies the signal voltage Vsig of the video signal to the signal lines 33 (33-1 to 33-n). When the input signal voltage Vsig is held in the storage capacitor 24 in a period in which the write transistor 23 is turned on in response to (WSm), that is, in the mobility correction period, the drain-source current Ids of the drive transistor 22 corresponds to the mobility μ. Mobility correction is performed to cancel the dependency. The specific principle and operation of this mobility correction will be described later.

(Bootstrap function)
The pixel 20 shown in FIG. 2 further has a bootstrap function. That is, the horizontal drive circuit 60 cancels the supply of the scanning signals WS (WS1 to WSm) to the scanning lines 31 (31-1 to 31-m) at the stage where the input signal voltage Vsig is held in the holding capacitor 24, and the writing is performed. The transistor 23 is turned off to electrically disconnect the gate of the drive transistor 22 from the signal line 33 (33-1 to 33-n). Thereby, since the gate potential Vg of the drive transistor 22 is interlocked with the fluctuation of the source potential Vs, the gate-source voltage Vgs of the drive transistor 22 can be kept constant.

(Circuit operation)
Next, the circuit operation of the organic EL display device 10 according to the present embodiment will be described based on the timing chart of FIG. 4 and the operation explanatory diagrams of FIGS. In the operation explanatory diagrams of FIGS. 5 and 6, the write transistor 23 is illustrated by a switch symbol for simplification of the drawing. In addition, the organic EL element 21 has a parasitic capacitance, and the parasitic capacitance and the auxiliary capacitance 25 are illustrated as a combined capacitance Csub.

  In the timing chart of FIG. 4, with a common time axis, the change in potential (scanning signal) WS of the scanning line 31 (31-1 to 31-m) at 1H (H is the horizontal scanning time), the power supply line 32 ( 32-1 to 32 -m), and changes in the gate potential Vg and the source potential Vs of the driving transistor 22. Until time t2, the waveform of the potential (scanning signal) WS of the scanning line 31 is indicated by a one-dot chain line, and the potential DS of the power supply line 32 is indicated by a dotted line so that the two can be identified. After time t3, both are indicated by solid lines.

<Light emission period>
In the timing chart of FIG. 4, before the time t1, the organic EL element 21 is in a light emission state (light emission period). In this light emission period, the potential DS of the power supply line 32 is at the high potential Vccp (first potential), and the drive current is supplied from the power supply line 32 to the organic EL element 21 through the drive transistor 22 as shown in FIG. Since (drain-source current) Ids is supplied, the organic EL element 21 emits light with a luminance corresponding to the drive current Ids.

<Threshold correction preparation period>
Then, at time t1, a new field of line sequential scanning is entered, and as shown in FIG. 5B, the potential DS of the power supply line 32 is sufficiently lower than the offset voltage Vofs of the signal line 33 from the high potential Vccp. When transitioning to Vini (second potential), the source potential Vs of the drive transistor 22 also starts to decrease toward the low potential Vini.

  Next, at time t2, the scanning signal WS is output from the writing scanning circuit 40, and the potential WS of the scanning line 31 shifts to the high potential side, so that the writing transistor 23 is in a conductive state as illustrated in FIG. It becomes. At this time, since the offset voltage Vofs is supplied from the horizontal drive circuit 60 to the signal line 33, the gate potential Vg of the drive transistor 22 becomes the offset voltage Vofs. Further, the source potential Vs of the drive transistor 22 is at a potential Vini that is sufficiently lower than the offset voltage Vofs.

  Here, the low potential Vini is set so that the gate-source voltage Vgs of the drive transistor 22 is larger than the threshold voltage Vth of the drive transistor 22. In this way, the gate voltage Vg of the drive transistor 22 is initialized to the offset voltage Vofs and the source potential Vs is initialized to the low potential Vini, whereby the preparation for the threshold voltage correction operation is completed.

<Threshold correction period>
Next, at time t3, as shown in FIG. 5D, when the potential DS of the power supply line 32 is switched from the low potential Vini to the high potential Vccp, the source potential Vs of the drive transistor 22 starts to rise. Eventually, the gate-source voltage Vgs of the drive transistor 22 becomes the threshold voltage Vth of the drive transistor 22, and a voltage corresponding to the threshold voltage Vth is written into the storage capacitor 24.

  Here, for convenience, a period during which a voltage corresponding to the threshold voltage Vth is written to the storage capacitor 24 is referred to as a threshold correction period. In the threshold correction period, the common power supply line 34 is set so that the organic EL element 21 is cut off in order to prevent the current from flowing exclusively to the storage capacitor 24 side and to the organic EL element 21 side. The potential Vcath is set in advance.

  Next, at time t4, the potential WS of the scanning line 31 shifts to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. At this time, the gate of the driving transistor 22 is in a floating state, but the driving transistor 22 is in a cutoff state because the gate-source voltage Vgs is equal to the threshold voltage Vth of the driving transistor 22. Therefore, the drain-source current Ids does not flow.

<Writing period / mobility correction period>
Next, at time t5, as shown in FIG. 6B, the potential of the signal line 33 is switched from the offset voltage Vofs to the signal voltage Vsig of the video signal. Subsequently, at time t6, the potential WS of the scanning line 31 transitions to the high potential side, so that the writing transistor 23 becomes conductive as shown in FIG. 6C, and the signal voltage Vsig of the video signal is sampled. To do.

  By sampling the input signal voltage Vsig by the write transistor 23, the gate potential Vg of the drive transistor 22 becomes the input signal voltage Vsig. At this time, since the organic EL element 21 is initially in a cut-off state (high impedance state), the drain-source current Ids of the drive transistor 22 flows into the combined capacitor Csub connected in parallel to the organic EL element 21. Charging of the combined capacity Csub is started.

  Due to the charging of the composite capacitor Csub, the source potential Vs of the drive transistor 22 starts to rise, and the gate-source voltage Vgs of the drive transistor 22 eventually becomes Vsig + Vth−ΔV. That is, the increase ΔV of the source potential Vs is subtracted from the voltage (Vsig + Vth) held in the holding capacitor 24, in other words, acts to discharge the charged charge of the holding capacitor 24, and negative feedback is applied. It will be. Therefore, the increase ΔV of the source potential Vs becomes a feedback amount of negative feedback.

  As described above, the drain-source current Ids flowing through the drive transistor 22 is negatively fed back to the gate input of the drive transistor 22, that is, the gate-source voltage Vgs, so that the drain-source current Ids of the drive transistor 22 is reduced. Mobility correction is performed to cancel the dependence on the mobility μ, that is, to correct the variation of the mobility μ for each pixel.

  More specifically, since the drain-source current Ids increases as the signal voltage Vsig of the video signal increases, the absolute value of the feedback amount (correction amount) ΔV of negative feedback also increases. Therefore, the mobility correction according to the light emission luminance level is performed. Further, when the signal voltage Vsig of the video signal is constant, the absolute value of the feedback amount ΔV of the negative feedback increases as the mobility μ of the driving transistor 22 increases, so that variation in the mobility μ for each pixel is removed. Can do.

<Light emission period>
Next, at time t7, the potential WS of the scanning line 31 shifts to the low potential side, so that the writing transistor 23 is turned off (off) as illustrated in FIG. 6D. As a result, the gate of the drive transistor 22 is disconnected from the signal line 33. At the same time, the drain-source current Ids starts to flow through the organic EL element 21, whereby the anode potential of the organic EL element 21 rises according to the drain-source current Ids.

  The increase in the anode potential of the organic EL element 21 is nothing but the increase in the source potential Vs of the drive transistor 22. When the source potential Vs of the drive transistor 22 rises, the gate potential Vg of the drive transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24. At this time, the increase amount of the gate potential Vg is equal to the increase amount of the source potential Vs. Therefore, the gate-source voltage Vgs of the drive transistor 22 is kept constant at Vsig + Vth−ΔV during the light emission period. At time t8, the potential of the signal line 33 is switched from the signal voltage Vsig of the video signal to the offset voltage Vofs.

  As apparent from the series of circuit operations described above, the scanning signal WS output from the writing scanning circuit 40 is driven by the writing transistor 23 to sample the offset voltage Vofs and write the first half of the writing pulse and the signal voltage. It includes a write pulse in the latter half of sampling and writing Vsig (see FIG. 4).

(Principle of threshold correction)
Here, the principle of threshold correction of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. As a result, a constant drain-source current (drive current) Ids given by the following equation (1) is supplied from the drive transistor 22 to the organic EL element 21.
Ids = (1/2) · μ (W / L) Cox (Vgs−Vth) ² (1)
Here, W is the channel width of the drive transistor 22, L is the channel length, and Cox is the gate capacitance per unit area.

  FIG. 7 shows the characteristics of the drain-source current Ids of the drive transistor 22 versus the gate-source voltage Vgs. As shown in this characteristic diagram, if correction for variation in the threshold voltage Vth of the drive transistor 22 is not performed, when the threshold voltage Vth is Vth1, the drain-source current Ids corresponding to the gate-source voltage Vgs becomes Ids1. On the other hand, when the threshold voltage Vth is Vth2 (Vth2> Vth1), the drain-source current Ids corresponding to the same gate-source voltage Vgs is Ids2 (Ids2 <Ids). That is, when the threshold voltage Vth of the driving transistor 22 varies, the drain-source current Ids varies even if the gate-source voltage Vgs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above-described configuration, as described above, the gate-source voltage Vgs of the driving transistor 22 at the time of light emission is Vsig + Vth−ΔV. Then, the drain-source current Ids is
Ids = (1/2) · μ (W / L) Cox (Vsig−ΔV) ² (2)
It is represented by

  That is, the term of the threshold voltage Vth of the drive transistor 22 is canceled, and the drain-source current Ids supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage Vth of the drive transistor 22. As a result, the drain-source current Ids does not vary even if the threshold voltage Vth of the drive transistor 22 varies for each pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time. The emission brightness does not change.

(Principle of mobility correction)
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 8 shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the driving transistor 22 and a pixel B having a relatively low mobility μ of the driving transistor 22 are compared. When the driving transistor 22 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

  For example, when the input signal voltage Vsig of the same level is written to both the pixels A and B in a state where the mobility μ is varied between the pixel A and the pixel B, the mobility μ is not corrected. A large difference is generated between the drain-source current Ids1 ′ flowing in the pixel A having a large value and the drain-source current Ids2 ′ flowing in the pixel B having the small mobility μ. Thus, if a large difference occurs between the pixels in the drain-source current Ids due to the variation in the mobility μ, the uniformity of the screen is impaired.

  Here, as is clear from the transistor characteristic equation of Equation (1), the drain-source current Ids increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 8, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel V having a low mobility. Therefore, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the input signal voltage Vsig side by the mobility correction operation, the larger the mobility μ, the more negative feedback is applied. Can be suppressed.

  Specifically, when the feedback amount ΔV1 is corrected in the pixel A having a high mobility μ, the drain-source current Ids greatly decreases from Ids1 ′ to Ids1. On the other hand, since the feedback amount ΔV2 of the pixel B having a low mobility μ is small, the drain-source current Ids decreases from Ids2 ′ to Ids2, and does not decrease that much. As a result, since the drain-source current Ids1 of the pixel A and the drain-source current Ids2 of the pixel B are substantially equal, the variation in the mobility μ is corrected.

  In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is smaller than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current Ids. That is, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the input signal voltage Vsig side, the current value of the drain-source current Ids of the pixels having different mobility μ is made uniform. Variation in degree μ can be corrected.

  Here, in the pixel (pixel circuit) 20 shown in FIG. 2, the relationship between the signal potential (sampling potential) Vsig of the video signal and the drain-source current Ids of the drive transistor 22 depending on the presence or absence of threshold correction and mobility correction. This will be described with reference to FIG.

  In FIG. 9, (A) does not perform both threshold correction and mobility correction, (B) does not perform mobility correction, and performs only threshold correction, (C) performs threshold correction and mobility correction. Each case is shown. As shown in FIG. 9A, when neither threshold correction nor mobility correction is performed, the drain-source current Ids is caused by variations in the threshold voltage Vth and the mobility μ for each of the pixels A and B. A large difference occurs between the pixels A and B.

  On the other hand, when only the threshold correction is performed, as shown in FIG. 9B, although the variation in the drain-source current Ids can be reduced to some extent by the threshold correction, the pixels A and B having the mobility μ The difference between the drain-source current Ids between the pixels A and B due to the variation of each pixel remains. Then, by performing both the threshold correction and the mobility correction, as shown in FIG. 9C, the drain between the pixels A and B due to the variation of the threshold voltage Vth and the mobility μ for each of the pixels A and B. Since the difference between the source currents Ids can be almost eliminated, the luminance variation of the organic EL element 21 does not occur at any gradation, and a display image with good image quality can be obtained.

(Characteristics of this embodiment)
As described above, the input signal voltage Vsig is sampled and written by the write transistor 23 under the drive by the write pulse (second half scanning signal WS), and the drive current corresponding to the written signal voltage Vsig is supplied to the organic EL element 21. In the organic EL display device 10 that emits light to drive the organic EL element 21 by flowing, in this embodiment, the falling waveform of the write pulse is made gentle (the transient response of the write pulse is delayed), so that the write transistor 23 The writing of the input signal voltage Vsig is stabilized while suppressing the decrease in the gate-source voltage Vgs of the driving transistor 22 due to the coupling at the time of off, and preventing the luminance from decreasing due to the decrease in the gate-source voltage Vgs. It is characterized by being able to do it.

[Example]
Hereinafter, a specific embodiment for making the falling waveform of the write pulse (second-half scanning signal WS) for writing the input signal voltage Vsig gentle will be described.

  As described above, the scanning signal WS (WS 1 to WSm) is output from the writing scanning circuit 40. As shown in FIG. 10, the write scanning circuit 40 includes a shift register 41, a logic circuit 42, and an output circuit 43 including a plurality of stages of buffers for each pixel row. It is mounted on the display panel 70 as a drive unit for driving.

  For example, a timing signal and a power supply voltage are supplied to the writing scanning circuit 40 from a control board 80 provided outside the display panel 70 via, for example, a flexible cable 90. Specifically, a timing generation circuit 81, a Vdd1 power supply circuit 82, a Vdd2 power supply circuit 83, and the like are provided on the control board 80.

  The timing generation circuit 81 generates a clock pulse CK serving as a reference for the operation of the shift register 41 and a start pulse ST for instructing the start of the shift operation of the shift register 41 and supplies the generated start pulse ST to the shift register 41. An enable pulse WSEN that determines the pulse width is generated and supplied to the logic circuit 42.

  The Vdd1 power supply circuit 82 generates a DC power supply voltage Vdd1. The power supply voltage Vdd1 is supplied as a positive power supply voltage to the buffers except the shift register 41, the logic circuit 42, and the final stage buffer 431 of the output circuit 43 via the flexible cable 90.

  The Vdd2 power supply circuit 83 is output from each stage of the shift register 41 and is faster than the falling speed of the shift pulse (input pulse) that is input to the final stage buffer 431 via the logic circuit 43 and the front stage portion of the output circuit 43. The power supply voltage Vdd2 that falls at a slow falling speed is generated in synchronization with, for example, the enable pulse WSEN. This power supply voltage Vdd2 is preferably set to have a voltage value higher than that of the power supply voltage Vdd1, and is supplied to the final stage buffer 431 of the output circuit 43 as its positive power supply voltage.

  In this way, the power supply voltage Vdd2 that falls at a falling speed slower than the falling speed of the shift pulse input to the final stage buffer 431 (that is, the falling waveform is gentle) is supplied to the final stage of the output circuit 43. A feature of this embodiment is that the buffer 431 is supplied as a power supply voltage on the positive side.

(Circuit configuration of the output circuit)
FIG. 11 is a circuit diagram showing an example of the circuit configuration of the output circuit 43 in a certain pixel row. Here, an output circuit having a two-stage configuration including the last-stage buffer 431 and the preceding-stage buffer 432 is shown as an example, but the present invention is not limited to the two-stage configuration.

  The final stage buffer 431 has a CMOS inverter configuration composed of a P-channel MOS transistor P11 and an N-channel MOS transistor N11 having gates and drains connected in common. Then, the power supply voltage Vdd2 having a gentle falling waveform is applied to the source of the MOS transistor P11, and the DC power supply voltage Vss is applied to the source of the MOS transistor N11.

  The front-stage buffer 432 has a CMOS inverter configuration including a P-channel MOS transistor P12 and an N-channel MOS transistor N12 whose gates and drains are connected in common. A DC power supply voltage Vdd1 is applied to the source of the MOS transistor P12, and a DC power supply voltage Vss is applied to the source of the MOS transistor N12.

(Circuit operation of the output circuit)
Next, the circuit operation of the output circuit 43 configured as described above will be described with reference to the timing waveform diagram of FIG.

  In the output circuit 43, the shift pulse output from the shift register 41 is input to the preceding buffer 432 via the logic circuit 42 as the input pulse A that rises at time t11 and falls at time t13. When this input pulse A passes through the circuit portions of the shift register 41 and the logic circuit 42, the rising and falling waveforms are rounded, and rises gently and falls gently.

  The input pulse A is inverted in polarity by the preceding buffer 432 and further inverted in polarity by the final buffer 431 to become an output pulse B. At this time, a power supply voltage Vdd2 that falls at time t12 and whose falling speed is slower than the falling speed of the input pulse A is provided on the control board 80 as the positive power supply voltage of the final stage buffer 431. Applied from the Vdd2 power supply circuit 83 via the flexible gable 90.

  When the power supply voltage Vdd2 falling at a falling speed slower than the falling speed of the input pulse A is supplied to the final stage buffer 431 as the positive side power supply voltage, the falling of the output pulse B becomes the power supply voltage Vdd2. Since it is determined by the falling edge, the falling waveform of the output pulse B, which is the writing pulse of the input signal voltage Vsig, becomes gentler than the falling waveform of the input pulse A.

(Operational effect of this embodiment)
As described above, the falling speed of the write pulse, which is the output pulse B of the final stage buffer 431, becomes slower than the falling speed of the input pulse A, that is, the write pulse is slower than the input pulse A (for example, τ = 100 As a result of the fall, the coupling by the storage capacitor 24 when the write transistor 23 is turned off decreases as shown in FIG. This can be suppressed as compared with the case where the pulse falls at the falling speed of the input pulse A.

  As a result, the decrease in the gate-source voltage Vgs of the drive transistor 22 due to the coupling when the write transistor 23 is off can be suppressed as compared with the case where the write pulse falls at the falling speed of the input pulse A. Therefore, writing of the input signal voltage Vsig can be performed stably while preventing a decrease in luminance due to a decrease in the gate-source voltage Vgs.

  Here, as another method of making the falling waveform of the write pulse gentle (transient response is smoothed), the characteristics of the circuit elements constituting the final stage buff 431 are changed in each final stage buff 431, for example, N It is conceivable to adopt a method such as reducing the size of the channel MOS transistor N11.

  However, in the case where the method of gradually reducing the falling waveform of the write pulse for each final stage buffer 431 is employed, if there is a characteristic variation in the circuit elements constituting the final stage buffer 431 for each stage of the write scanning circuit 40, the characteristics thereof Due to the variation, the falling waveform of the write pulse varies for each stage of the write scanning circuit 40, and there is a concern that the variation becomes uneven and deteriorates the image quality.

  In contrast, the falling speed of the power supply voltage Vdd2 commonly supplied as the positive power supply to the final stage buffer 431 of each stage of the write scanning circuit 40 is the falling speed of the input pulse A of the final stage buffer 431. Is set later than that, and the write pulse of each stage is lowered at the fall of the power supply voltage Vdd2, so that the fall waveform of the write pulse at each stage is uniformly determined by the fall waveform of the power supply voltage Vdd2. .

  As a result, there is no waveform variation at each stage in the falling waveform of the write pulse, and the occurrence of uneven stripes due to the waveform variation at each stage can be suppressed. Can be planned.

  In this embodiment, the case where the positive logic output pulse B that is active at the “H” level is generated as the write pulse (scanning signal WS) has been described as an example. However, it is active at the “L” level. The same applies to the case of generating a negative logic output pulse B ′. In this case, the negative power supply of the final stage buffer 431 of the output circuit 43 is separated from other circuit portions, and the power supply voltage Vss2 rising at a rising speed slower than the rising speed of the input pulse A ′ is supplied as the negative power supply. By doing so, the rising waveform of the negative logic output pulse B ′ can be smoothed (transient response of the output pulse B ′ can be delayed).

(Circuit configuration of Vdd2 power supply circuit)
FIG. 14 is a circuit diagram showing an example of the circuit configuration of the Vdd2 power supply circuit 83. Here, a circuit configuration that generates the power supply voltage Vdd2 having, for example, two falling points in the falling waveform will be described as an example, but the number of falling points in the falling waveform is not limited to two.

  As shown in FIG. 14, the Vdd2 power supply circuit 83 includes a P-channel MOS transistor P21, resistors R21 and R22, N-channel MOS transistors N21, N22, and N23 and variable resistors VR21 and VR22.

  The source of the P channel MOS transistor P21 is connected to the power supply line of the power supply voltage Vdd1. Resistor R11 is connected between the source and gate of P-channel MOS transistor P21. One end of the resistor R21 is connected to the gate of the P-channel MOS transistor P21.

  The N-channel MOS transistor N21 is connected between the other end of the resistor R21 and the ground as a reference node, and the first control pulse DCP1 is input to the gate. One end of each of variable resistors VR21 and VR22 is commonly connected to the drain of P-channel MOS transistor P21.

  The N-channel MOS transistor N22 is connected between the other end of the variable resistor VR21 and the ground, and the second control pulse DCP2 is input to the gate. The N-channel MOS transistor N23 is connected between the other end of the variable resistor VR22 and the ground, and the third control pulse DCP3 is input to the gate.

(Circuit operation of Vdd2 power supply circuit)
Next, the circuit operation of the Vdd2 power supply circuit 83 configured as described above will be described with reference to the timing waveform diagram of FIG.

  FIG. 15 shows the timing relationship of the enable pulse WSEN, the first, second and third control pulses DCP1, DCP2, DCP3 and the output pulse B of the final-stage buff 431, which are write pulses, given from the timing generation circuit 82 of FIG. Is shown.

  The enable pulse WSEN is in an active (“H” level) state during a period from time t11 to time t14. The first control pulse DCP1 transitions from the active state to the inactive ("L" level) state at time t10 prior to time t11, and from the inactive state at time t16 after the active period of the enable pulse WSEN has elapsed. Transition to the active state. The second control pulse DCP2 becomes active during the period from time t12 to time t13 within the active period of the enable pulse WSEN. The third control pulse DCP3 becomes active at time t12 and becomes inactive at time t15 after the active period of the enable pulse WSEN has elapsed.

  Since the first control pulse DCP1 is in an active state until time t10 and the N-channel MOS transistor N21 is in an on state, the power supply voltage Vdd1 is output as the power supply voltage Vdd2 because the P-channel MOS transistor P21 is in an on state. The Here, since the display panel 70 to which the power supply voltage Vdd2 is supplied can be regarded as a large capacitance component, the first control pulse DCP1 transitions from the active state to the inactive state at time t10, and the P-channel MOS transistor P21. Even after turning off, the level of the power supply voltage Vdd1 is maintained as the power supply voltage Vdd2.

  At time t12, when the second and third control pulses DCP2 and DCP3 are activated and the N-channel MOS transistors N22 and N23 are turned on, the combined resistance value of the variable resistors VR21 and VR22, the capacitance component of the display panel 70, and the like. The power supply voltage Vdd2 falls at a determined time constant.

  Next, when the second control pulse DCP2 becomes inactive at time t13, the N-channel MOS transistor N22 is turned off, and only the N-channel MOS transistor N23 is turned on, the power supply voltage Vdd2 is changed from the break point O11 to the variable resistance. It falls slowly with a time constant determined by the resistance value of VR22 and the capacitance component of the display panel 70.

  Next, the enable pulse WSEN becomes inactive at time t14, and then, at time t15, when the third control pulse DCP3 transitions from the active state to the inactive state and the N-channel MOS transistor N23 is turned off, the break point O12 is reached. The power supply voltage Vdd2 becomes a substantially constant level.

  At time t16, when the first control pulse DCP1 transitions from the inactive state to the active state and the N-channel MOS transistor N21 is turned on, the P-channel MOS transistor P21 is turned on, so that the power supply voltage Vdd2 is the power supply voltage Vdd1. Get up gradually toward.

  Thus, for example, the falling characteristic power supply voltage Vdd2 having two break points O11 and O12 is output from the Vdd2 power supply circuit 83 on the control board via the flexible cable 90 in FIG. 43 is supplied to the final stage buffer 431 as its positive power source. At this time, the power supply voltage Vdd2 has a waveform as shown by a one-dot chain line in FIG. 15 due to the influence of the wiring resistance and parasitic capacitance of the power supply path to the final buffer 431.

  The power supply voltage Vdd2 is supplied as power for the final stage buffer 431 of the output circuit 43, and the shift pulse output from each stage of the shift register 41 is passed through the logic circuit 42 during the active period of the enable pulse WSEN. As an input pulse A (see FIG. 12) is input to 431, an output pulse B that rises when the input pulse A rises and falls when the power supply voltage Vdd2 falls, that is, a write pulse WS is generated.

  In the Vdd2 power supply circuit 83 configured as described above, by changing the resistance values of the variable resistors VR1 and VR2, in the falling characteristics of the power supply voltage Vdd2, the inclination angle from the falling start point to the break point O11, and the break point Since the inclination angle from O11 to the break point O12 can be adjusted, the falling characteristic of the power supply voltage Vdd2 can be arbitrarily set by adjusting the resistance values of the variable resistors VR1 and VR2.

  Therefore, even if the optimum signal writing period (mobility correction period) differs for each display panel 70, the resistance values of the variable resistors VR1 and VR2 are changed for each display panel 70 to adjust the falling characteristics of the writing pulse. As a result, the falling characteristics of the write pulse WS that are suitable for the display panel 70 can be set, so that an optimum signal writing period can be set for each display panel 70.

  In the above, the case where the pixel 20 has two transistors of the driving transistor 22 and the writing transistor 23 and is applied to an organic EL display device configured to perform mobility correction simultaneously in the writing period of the input signal voltage Vsig is taken as an example. As described above, the present invention is not limited to this application example. For example, as described in Patent Document 1, the present invention further includes a switching transistor directly connected to the driving transistor 22, and the switching transistor is used as an organic material. The present invention can be similarly applied to an organic EL display device configured to control light emission / non-light emission of the EL element 21 and perform mobility correction prior to writing of the input signal voltage Vsig.

(Another effect of this embodiment)
However, when applied to an organic EL display device having a configuration in which writing of the input signal voltage Vsig and mobility correction are performed simultaneously as in the organic EL display device 10 according to the present embodiment, the following specific operational effects are obtained. Can be obtained.

  In other words, since the falling edge of the write pulse is not steep and gentle like a rectangular wave, the mobility correction period can be optimized even in gray to black gradations, that is, the optimum mobility correction period corresponding to each gradation. Can be set. This will be specifically described below.

  As the gray and black gradations and the input signal voltage Vsig become lower than the white gradation, the optimum mobility correction time becomes longer. As shown in FIG. 16, since the initial current flowing through the driving transistor 22 is smaller than that of the white gradation in the gray gradation, this is necessary for mobility correction due to the operating point of the driving transistor 22. This is because the mobility correction time is longer than the white gradation.

  Here, in the case where the writing of the input signal voltage Vsig and the mobility correction are performed at the same time, the ON period of the writing transistor 23 becomes the mobility correction period (signal writing period). The write transistor 23 is turned on when the level difference between the input signal voltage Vsig and the write pulse WS is equal to or higher than the threshold voltage. Therefore, it can be said that the ON period of the write transistor 23, that is, the mobility correction period, depends on the falling waveform of the write pulse WS.

  Therefore, when the input signal voltage Vsig is large as in the white gradation, the write transistor WS is turned off at a high level of the fall of the write pulse WS because the write pulse WS gradually falls. When a short time is set as the mobility correction period of the white gradation and the input signal voltage Vsig is small as in the gray gradation, the writing transistor 23 is turned off at a low level of the writing pulse WS. A long time is set as the mobility correction period for the gray gradation.

  That is, in the organic EL display device 10 configured to simultaneously write the input signal voltage Vsig and correct the mobility, the input signal is input by the write transistor 23 under the control of the write pulse with a gentle falling waveform (slow transient response). By sampling and writing the voltage Vsig, it is possible to set the optimum mobility correction time corresponding to each gradation corresponding to the difference in the optimum mobility correction time between the gray gradation and the white gradation.

  In this way, by setting the optimal mobility correction time corresponding to each gradation, mobility correction that removes the variation in mobility μ for each pixel can be performed over all gradations from white gradation to black gradation. Since it can be performed reliably, it is possible to achieve higher image quality of the display image.

  In the above embodiment, the case where the present invention is applied to an organic EL display device using an organic EL element as the electro-optical element of the pixel circuit 20 has been described as an example. However, the present invention is not limited to this application example. In addition, the present invention can be applied to all display devices using current-driven electro-optic elements (light-emitting elements) whose light emission luminance changes according to the value of current flowing through the device.

[Application example]
The display device according to the present invention described above is input to various electronic devices shown in FIGS. 17 to 21 such as a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, and a video camera. The present invention can be applied to display devices for electronic devices in various fields that display a video signal or a video signal generated in the electronic device as an image or video. An example of an electronic device to which the present invention is applied will be described below.

  Note that the display device according to the present invention includes a module-shaped one having a sealed configuration. For example, a display module formed by being affixed to an opposing portion such as transparent glass on the pixel array portion 30 is applicable. The transparent facing portion may be provided with a color filter, a protective film, and the like, and further, the above-described light shielding film. Note that the display module may be provided with a circuit unit for inputting / outputting a signal and the like from the outside to the pixel array unit, an FPC (flexible printed circuit), and the like.

  FIG. 17 is a perspective view showing a television to which the present invention is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to the present invention as the video display screen unit 101.

  18A and 18B are perspective views showing a digital camera to which the present invention is applied. FIG. 18A is a perspective view seen from the front side, and FIG. 18B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present invention as the display unit 112.

  FIG. 19 is a perspective view showing a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like. It is produced by using.

  FIG. 20 is a perspective view showing a video camera to which the present invention is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using such a display device.

  FIG. 21 is a perspective view showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which (A) is a front view in an opened state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. And the sub display 145 is manufactured by using the display device according to the present invention.

1 is a system configuration diagram illustrating an outline of a configuration of an organic EL display device according to an embodiment of the present invention. It is a circuit diagram which shows the specific structural example of a pixel (pixel circuit). It is sectional drawing which shows an example of the cross-sectional structure of a pixel. It is a timing chart with which it uses for operation | movement description of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 1) of circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 2) of the circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the threshold voltage Vth of a drive transistor. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the mobility (mu) of a drive transistor. FIG. 10 is a characteristic diagram for explaining the relationship between the signal voltage Vsig of the video signal and the drain-source current Ids of the drive transistor depending on whether threshold correction and mobility correction are performed. It is a block diagram which shows an example of a structure of a writing scanning circuit. It is a circuit diagram which shows an example of the circuit structure of the output circuit of a certain pixel row. FIG. 6 is a timing waveform diagram for explaining the circuit operation of the output circuit. FIG. 6 is a timing waveform diagram for explaining an operation when a write transistor is off. It is a circuit diagram which shows an example of a circuit structure of a Vdd2 power supply circuit. FIG. 6 is a timing waveform diagram for explaining the circuit operation of the Vdd2 power supply circuit. It is a characteristic view with which it uses for description of the optimal mobility correction | amendment time according to a gradation. It is a perspective view which shows the television to which this invention is applied. It is the perspective view which shows the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view showing a notebook personal computer to which the present invention is applied. It is a perspective view which shows the video camera to which this invention is applied. It is a perspective view showing a cellular phone to which the present invention is applied, (A) is a front view in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. FIG. 5 is a timing waveform diagram for explaining a problem when a write transistor is off.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Organic EL display device, 20 ... Pixel (pixel circuit), 21 ... Organic EL element, 22 ... Drive transistor, 23 ... Write transistor, 24 ... Retention capacity, 25 ... Auxiliary capacity, 30 ... Pixel array part, 31 (31 -1 to 31-m) ... scanning lines, 32 (32 to 1 to 32-m) ... power supply lines, 33 (33-1 to 33-n) ... signal lines, 34 ... common power supply lines, 40 ... write Scanning circuit 50 ... Power supply scanning circuit 60 ... Horizontal drive circuit 70 ... Display panel 80 ... Control board 81 ... Timing generating circuit 82 ... Vdd1 power supply circuit 83 ... Vdd2 power supply circuit 90 ... Flexible cable

Claims (5)

An electro-optic element; a writing transistor that samples and writes an input signal voltage; a holding capacitor that holds the input signal voltage written by the writing transistor; and the electro-optic device based on the input signal voltage held in the holding capacitor A pixel array unit in which pixels including drive transistors for driving elements are arranged in a matrix;
A last stage buffer having a power supply separated from the circuit part on the previous stage side is provided, and each pixel of the pixel array section is selectively scanned in units of rows by applying a write pulse based on an input pulse of the last stage buffer to the write transistor. And a scanning circuit that
The final stage buffer is configured to cause the write pulse to fall at the falling edge of the power supply voltage when a power supply voltage having a falling speed slower than the falling speed of the input pulse is supplied to its own power supply. Display device. Each pixel of the pixel array unit has a drain-source current of the driving transistor by negatively feeding back the drain-source current of the driving transistor to the gate input side during the writing period of the input signal voltage by the writing transistor. The display device according to claim 1, wherein a correction operation is performed to cancel the dependence on the mobility of the display device. The display device according to claim 1, wherein the power supply voltage is commonly supplied as each power supply voltage of the final stage buffer of each stage of the scanning circuit. An electro-optic element; a writing transistor that samples and writes an input signal voltage; a holding capacitor that holds the input signal voltage written by the writing transistor; and the electro-optic device based on the input signal voltage held in the holding capacitor A pixel array unit in which pixels including drive transistors for driving elements are arranged in a matrix;
A last stage buffer having a power supply separated from the circuit part on the previous stage side is provided, and each pixel of the pixel array section is selectively scanned in units of rows by applying a write pulse based on an input pulse of the last stage buffer to the write transistor. In a display device comprising a scanning circuit for
Driving the display device, wherein the write pulse is lowered at the falling edge of the power supply voltage by supplying a power supply voltage having a falling speed slower than the falling speed of the input pulse to the power supply of the final stage buffer. Method. An electro-optic element; a writing transistor that samples and writes an input signal voltage; a holding capacitor that holds the input signal voltage written by the writing transistor; and the electro-optic device based on the input signal voltage held in the holding capacitor A pixel array unit in which pixels including drive transistors for driving elements are arranged in a matrix;
A last stage buffer having a power supply separated from the circuit part on the previous stage side is provided, and each pixel of the pixel array section is selectively scanned in units of rows by applying a write pulse based on an input pulse of the last stage buffer to the write transistor. And a scanning circuit that causes the write pulse to fall at the falling edge of the power supply voltage when a power supply voltage having a falling speed slower than the falling speed of the input pulse is supplied to the power supply of the final stage buffer. An electronic device comprising a display device.

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