JP2008180592A - Test pattern generating circuit and test circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that existing test pattern circuit can not arbitrary set the combination of random number sequences to be generated. <P>SOLUTION: A test pattern generating circuit, connected with a bus wiring, is a test pattern generating circuit outputting a test pattern to an interface circuit 14 inputting/outputting multi bit data in parallel. This circuit includes: a plurality of pseudo random number generating circuits 13_1-13_n, set corresponding to the signal lines in a bus wiring respectively, with predetermined first initial values, each of them showing the same value, and generating pseudo random numbers with the initial value set as a start value according to the inputted first clock signals CLK_1-CLK_2; and a clock control circuit 11 arbitrary determining the output starting timing of the first clock signals CLK_1-CLK_n to be given to the plurality of pseudo random number generating circuits 13_1-13_n respectively according to the control signal values. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The test pattern generation circuit and the test circuit according to the present invention particularly relate to a test pattern generation circuit and a test circuit that provide a pseudo random number as a test pattern to an interface circuit having a multi-bit configuration.

  In recent years, a defect in an interface circuit connected to a bus wiring has become a problem as one of the defects in a semiconductor device. In the interface circuit connected to the bus wiring, random data transmission / reception is performed with respect to the bus wiring. Depending on the arrangement of data to be transmitted / received, data interference may occur in the interface circuit, resulting in a problem that an error occurs in the data to be transmitted / received. The interface circuit is required to perform good transmission / reception with respect to various data that may cause the above-described problems. Therefore, a test circuit and a test pattern generation circuit for testing the interface circuit with such data are desired, and circuits as shown in Patent Documents 1 to 4 below have been proposed.

  FIG. 18 shows a block diagram of a test circuit 110 disclosed in Patent Document 1 (hereinafter referred to as Conventional Example 1). The test circuit 110 is built in the semiconductor device 101 and generates a random test pattern and a test pattern signature input via the interface circuit 120. At this time, the test circuit 110 performs a random test pattern using the pattern generator 111 and the shift register 112. The pattern generation unit 111 includes an LFSR (Linear Feedback Shift Register) 116 that generates a pseudo random number starting from a predetermined seed value (hereinafter referred to as Seed value), and generates a pseudo random number serially. The shift register 112 rearranges serial pseudo-random numbers by flip-flops connected in series and converts them into parallel pseudo-random numbers. Then, the test pattern having randomness is input to the interface circuit 120 connected to the bus wiring by inputting the output of the pattern generation unit 111 and the output of the shift register 112 in parallel to the data connection unit 113. Thus, the test circuit 110 can input a data string having randomness to the interface circuit 120.

  Another example of the interface circuit test is disclosed in Patent Document 2 (hereinafter referred to as Conventional Example 2). In the test circuit according to Conventional Example 2, a test pattern generator and a semiconductor device to be tested are prepared separately. The test pattern generator generates a pseudo random number having a predetermined seed value as a start value, and outputs the pseudo random number to the semiconductor device. The semiconductor device has an expected value generation circuit having a circuit configuration corresponding to the test pattern generator. Then, the test pattern input via the interface circuit built in the semiconductor device and the output of the expected value generation circuit are compared by a comparator. Thus, in the conventional example 2, the interface circuit is tested with a random data string.

Conventional examples 1 and 2 use pseudo-random numbers as test patterns. Other examples of circuits that generate such pseudo-random numbers are disclosed in Patent Documents 3 and 4 (hereinafter referred to as conventional examples 3 and 4, respectively). It is disclosed.
JP 2006-78447 A JP 2005-339675 A JP-A-11-85475 JP 2003-330704 A

  By using Conventional Examples 1 to 4, the randomness of the data is ensured in the data string direction. However, since the pattern generation circuits or pattern generation units of the conventional examples 1 to 4 cannot set a large number of seed values, only pseudo-random numbers based on the circuit configuration can be generated. Therefore, combinations of data between signal lines in the bus wiring (hereinafter referred to as the bus width direction) are limited. For example, a test pattern having a predetermined combination cannot be created intentionally. Therefore, the conventional examples 1 to 4 have a problem that the test coverage in the bus width direction cannot be improved in the interface circuit test.

  A test pattern generation circuit according to the present invention is a test pattern generation circuit that outputs a test pattern to an interface circuit that is connected to a bus wiring and performs input / output of multi-bit data in parallel. A first initial value which is provided corresponding to each of the signal lines and has the same value is set in advance, and the first initial value is set as a start value according to the input first clock signal. A plurality of pseudo-random number generation circuits for generating random numbers, and a clock control circuit for arbitrarily determining an output start timing of the first clock signal to be given to each of the plurality of pseudo-random number generation circuits according to a value of the control signal; It is what has.

  According to the test pattern generation circuit of the present invention, it is possible to arbitrarily set operation start timings of a plurality of pseudo random number generation circuits having the same first initial value. This makes it possible to arbitrarily set a combination of patterns generated by a plurality of pseudo random number generation circuits at a predetermined time.

  In addition, the test circuit according to the present invention compares the test pattern generation circuit according to the present invention with the pseudorandom numbers input via the interface circuit and the pseudorandom numbers output from the plurality of pseudorandom number generation circuits. And a result holding circuit for holding the test result output from the comparator and outputting the test result. With this test circuit, it is possible to perform a feedback test with high test coverage.

  According to the test pattern generation circuit and the test circuit of the present invention, it is possible to perform a feedback test with high test coverage by improving both the randomness in the data string direction and the randomness of the data combination in the bus width direction. It is.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a test pattern generation circuit 1 according to the present invention. As shown in FIG. 1, the test pattern generation circuit 1 includes a clock control circuit 11 and pseudo-random number generation circuits (PRBS in the figure) 13_1 to 13_n, and the outputs of the pseudo-random number generation circuits correspond to the corresponding interfaces. Connected to the channel. In the following description, n and m represent integers. Further, a clock generation circuit 10 and an interface circuit 14 are connected to the test pattern generation circuit 1.

  The clock generation circuit 10 outputs a reference clock having a predetermined frequency. In the present embodiment, it is assumed that the clock generation circuit 10 outputs a reference clock after a reset signal RST described later changes from a low level to a high level.

  The interface circuit 14 is a circuit under test and is connected to a bus wiring (not shown). The test pattern generation circuit and the interface circuit 14 to be tested by the test circuit according to the present invention have a plurality of channels, and each channel includes a transmission circuit and a reception circuit.

  The clock control circuit 11 has a first clock control circuit 12. The first clock control circuit 12 generates a plurality of first clock signals CLK1_1 to CLK1_n according to the reference clock. Further, the first clock control circuit 12 arbitrarily sets the output start timings of the plurality of first clock signals based on the value of the first control signal. Then, the first clock signals CLK1_1 to CLK1_n are input as clocks to pseudo random number generation circuits 13_1 to 13_n provided corresponding to the first clock signals CLK1_1 to CLK1_n, respectively. The first control signal is a multi-bit control signal (for example, m bits). In the present embodiment, the first clock control circuit 12 sets the output start timing of the first clock signals CLK1_1 to CLK1_n according to the value represented by m bits. The first clock control circuit 12 receives a reset signal RST. The reset signal RST is also supplied to each of the pseudo random number generation circuits 13_1 to 13_n. The reset signal RST will be described later.

  Each of the pseudo-random number generation circuits 13_1 to 13_n is, for example, a circuit shown in FIG. 6 of Reference 4, and the same seed value (hereinafter referred to as a first initial value) having the same value is the same as a start value. A pseudo-random data sequence (a data sequence called PRBS (Pseudo Random Binary Sequence)) is output. In the present embodiment, the pseudo-random number generation circuits 13_1 to 13_n have therein a shift register (LFSR: Linear Feedback Shift Register) that is fed back via an exclusive OR (ExOR) circuit. . Each of the pseudo random number generation circuits 13_1 to 13_n initializes its internal register (LFSR) and has a first initial value when reset (while the reset signal RST is at low level). Then, after the reset is released, pseudo random numbers are generated and output according to the first clock signals CLK1_1 to CLK1_n as described above. Further, since the pseudo random number generation circuits 13_1 to 13_n are provided corresponding to the channels of the interface circuit 14, respectively, they are provided corresponding to the signal lines of the bus wiring connected to the interface circuit 14. . That is, the number of pseudo random number generation circuits 13_1 to 13_n is the same as the number of signal lines of the bus wiring.

  Here, the first clock control circuit 12 will be described in more detail. A block diagram of the first clock control circuit 12 is shown in FIG. As shown in FIG. 2, the first clock control circuit includes counters 17_2 to 17_n, clock gating circuits 16_2 to 16_n, and comparators 18_2 to 18_n.

  In the present embodiment, the first clock control circuit 12 outputs the input reference clock as the first clock signals CLK1_1 to CLK1_n. The counters 17_2 to 17_n receive the reset signal RST, and the value of the counter remains the initial value “0” while the reset signal RST is at the low level. Then, after the reset signal RST becomes high level, the counters 17_2 to 17_n count the number of clocks of the corresponding first clock signals CLK1_1 to CLK1_n−1, respectively. For example, the counter 17_2 provided corresponding to the clock gating circuit 16_2 that outputs the first clock signal CLK1_2 counts the number of clocks of the first clock signal CLK1_1. The comparators 18_2 to 18_n compare the count value output from the counter provided corresponding thereto with the value of the first control signal, and when the count value matches the value of the first control signal, the enable signal EN_2. ~ EN_n is output. For example, the comparator 18_2 compares the count value output from the counter 17_2 with the value of the first control signal, and outputs the enable signal EN_2 when the count value matches the value of the first control signal. Note that the counters 17_2 to 17_n in the present embodiment hold the values after the count value matches the value of the first control signal.

  The clock gating circuits 16_2 to 16_n are AND gates or the like, and correspond to the first clock signals CLK1_1 to CLK1_n-1 corresponding to the corresponding enable signals EN_2 to EN_n, respectively. Output as ~ CLK1_n. For example, when the enable signal EN_2 is at a high level, the clock gating circuit 16_2 outputs the first clock signal CLK1_1 as the first clock signal CLK1_2. On the other hand, when the enable signal EN_2 is at the low level, the clock gating circuit 16_2 sets the output to the low level and does not output the clock.

  Hereinafter, the interface circuit 14 has 4 channels (n = 4), the pseudo random number generation circuit has the 7th order (the order k = 7, that is, is configured by a 7-stage register), and the first control signal has 6 bits (m = Consider the case of 6). At this time, one pseudo random number generation circuit 13_1 creates a pseudo random number sequence of 2 7 −1 = 127. That is, a pseudo-random number having one cycle is generated at 127 clocks. Further, the first clock control circuit 12 sets the output start timing of the first clock signals CLK1_1 to CLK1_n according to a value represented by 6 bits.

  The timing chart of the operation of the first clock control circuit 12 in this case is shown in FIGS. The timing chart shown in FIG. 3 shows the operation of the first clock control circuit 12 when the first control signal indicates “1” (for example, “000001”). The timing chart shown in FIG. 4 shows the operation of the first clock control circuit 12 when the first control signal indicates “4” (for example, “000100”). In FIGS. 3 and 4, since n = 4, the first clock control circuit 12 outputs the first clock signals CLK1_1 to CLK1_4. The operation of the first clock control circuit 12 will be described with reference to FIGS.

  First, the operation shown in FIG. 3 will be described. The first clock control circuit 12 sets the count value of the counters 17_2 to 17_n (n = 4 in this description) to “0” by setting the reset signal RST to the low level in the state before the operation starts. Then, the reset signal RST is set to the high level to release the reset. After the reset is released, the reference clock is input from the clock generation circuit 10. When the reset is released and the reference clock is applied, the first clock control circuit 12 outputs the reference clock as the first clock CLK1_1. (Timing T11).

  Further, since the value of the first control signal is “1”, when the count value of the counter 17_2 reaches “1”, the comparator 18_2 sets the enable signal EN_2 to the high level. Accordingly, the clock gating circuit 16_2 starts outputting the first clock signal CLK1_2 with a delay from the first clock signal CLK1_1 by a time corresponding to one clock of the reference clock (timing T12).

  After that, the first clock signal CLK1_3 and the first clock signal CLK1_4 are output in the same manner as the first clock signal CLK1_2. That is, output of the first clock signal CLK1_3 is delayed by a time corresponding to one clock of the reference clock from the first clock signal CLK1_2 (timing T13). The output of the first clock signal CLK1_4 is delayed from the first clock signal CLK1_3 by a time corresponding to one clock of the reference clock (timing T14). That is, the first clock signals CLK1_1 to CLK1_4 are sequentially output with a delay of the number of clocks corresponding to the value of the first control signal.

  Here, the timing T15 is set after the timing T14 (including T14) when the first clock signal is finally input to the pseudo-random number generation circuit. After timing T15, the first clock signals CLK1_1 to CLK1_4 are applied to all the pseudo random number generation circuits for one cycle or more, and a test pattern used for an actual test is generated after timing T15. Here, the period of timing T11 to T15 in FIG. 3 is hereinafter referred to as a test pattern initial value setting period.

  Next, the operation shown in FIG. 4 will be described. In FIG. 4, since the value of the first control signal is “4”, when the count value of the counter 17_2 reaches “4”, the comparator 18_2 sets the enable signal EN_2 to the high level. Therefore, the clock gating circuit 16_2 starts outputting the first clock signal CLK1_2 with a delay from the first clock signal CLK1_1 by a time corresponding to four clocks of the reference clock (timing T22). Other operations are the same as those in FIG. 3, and timings T21, T22, T23, T24, and T25 correspond to timings T11, T12, T13, T14, and T15, respectively. Note that the timing T25 is set after the timing T24 (including T24) when the first clock signal is finally input to the pseudo-random number generation circuit, similarly to the timing T15.

  In this way, the first clock control circuit sets the output start timing of the first clock signals CLK1_1 to CLK1_n according to the value of the first control signal. The test pattern generation circuit 1 according to the present exemplary embodiment has a random number generation start value (hereinafter referred to as a second initial value) at the start of the test of the pseudo random number generation circuits 13_1 to 13_n by the operation of the first clock control circuit. Set. That is, as described above, the initial value (second initial value) of the test pattern used for the actual test is generated and set at the timings T15 and T25.

  Here, the setting operation of the second initial value and the test pattern used during the test will be described. First, the setting operation of the second initial value will be described. Since the pseudo random number generation circuits 13_1 to 13_n according to the present embodiment output the 7th-order PRBS, the data string to be output has 127 data. Assuming that each data of this data string is D1 to D127, when the start value is the first initial value, the pseudo random number generation circuits 13_1 to 13_n use the data D1 as the data at the start of operation, and the data D1 to the data D127. Output repeatedly in order.

  When the first clock signals CLK1_1 to CLK1_n output from the first clock control circuit 12 are supplied to the pseudo random number generation circuits 13_1 to 13_n, for example, at the timing T14 illustrated in FIG. 3, the pseudo random number generation circuits 13_1 to 13_1 are provided. The outputs OUT1 to OUT4 of 13_4 are “D4, D3, D2, D1” in order from OUT1. When the timing T15 is set to be the same as the timing T14, the outputs OUT1 to OUT4 of the pseudo random number generation circuits 13_1 to 13_4 are “D4, D3, D2, D1” sequentially from OUT1, and the reference clock is 127 clocks from the timing T11. If it is set at the place where minutes have passed, it becomes “D127, D126, D125, D124”. In this embodiment, as described above, the initialization of the pseudorandom number generation circuits 13_1 to 13_4 is completed at the timing T15, and the values of OUT1 to OUT4 at the timing T15 are given as the second initial values. In the example shown in FIG. 4, the second initial values of the test patterns TP1 to TP4 are “D13, D9, D5, D1” in order from the test pattern TP1 if the timing T25 is set to be the same as the timing T24. If the reference clock is set at the point where 127 clocks have elapsed from the timing T21, "D127, D123, D119, D115" are obtained in order from the test pattern TP1. After the timing T15, an actual test pattern for the interface circuit 14 is obtained. Therefore, in the test state, the test patterns output from the pseudo random number generation circuits 13_1 to 13_4 after the timing T15 are sequentially given to the interface circuit 14.

  From the above description, in the test pattern generation circuit 1 according to the present embodiment, the clock control circuit 11 changes the output start timings of the plurality of first clock signals to be output based on the value of the first control signal. Is possible. In addition, by operating a plurality of pseudo random number generation circuits based on the plurality of first clock signals, the number of clocks of the first clock signal given to the plurality of pseudo random number generation circuits during the test pattern initial value setting period is set. Each can be different. Then, the second initial value is set based on the values output from the plurality of pseudo random number generation circuits at the end of the test pattern initial value setting period. That is, the second initial values set in the plurality of pseudo-random number generation circuits are different depending on the value of the first control signal, and after starting the test, the pseudo initial value is set to the second initial value. Generate a random data sequence. That is, the test pattern generation circuit 1 according to the present embodiment has a function corresponding to a function of arbitrarily setting the seed values of a plurality of pseudo random number generation circuits.

  Thereby, the test pattern generation circuit 1 according to the present embodiment can arbitrarily set a combination in the bus width direction of data output from a plurality of pseudo random number generation circuits at a predetermined time after the start of the test. . Therefore, according to the test pattern generation circuit 1 according to the present embodiment, a test pattern having high randomness in the data string direction and high randomness in the bus width direction can be given to the interface circuit 14.

  In addition, since the test pattern generation circuit 1 has a plurality of pseudo-random number generation circuits, it can generate a random pattern at high speed. In Conventional Example 1, one out of four random patterns output from the LFSR is transmitted to the interface circuit. On the other hand, the random pattern output from the test pattern generation circuit 1 can be continuously supplied to the interface circuit 14 without being thinned out.

  In the embodiment described above, the first clock control circuit 12 has described the example in which the plurality of first clock signals are output at different output start timings. However, when “0” is set as the value of the first control signal, the plurality of first clock signals are output at substantially the same timing. As a result, the test pattern output from the pseudo random number generation circuit can be made the same data at any time. That is, the test pattern generation circuit 1 according to the present embodiment can combine data in the bus width direction with a high degree of freedom. That is, the test pattern generation circuit 1 can intentionally create a test pattern having a predetermined combination.

  Here, the setting of the timings T15 and T25 of the test pattern generation circuit 1 and the setting of the bit width of the first control signal will be described. Timings T15 and T25 are timings at which the first clock signals CLK1_1 to CLK1_4 are applied to all the pseudorandom number generation circuits for one cycle or more, and pseudorandom numbers can be generated respectively. In the present invention, since the interface circuit has n channels and the first control signal has m bits, at least after the timing when the reference clock of (2 to the power of m−1) × (n−1) cycles is applied. You only have to set it.

  The first control signal indicates a clock shift (delay) between the first clock signals adjacent to each other in the first clock signals CLK1_1 to CLK1_n. If each of the pseudo random number generation circuits 13_1 to 13_n is k-th order, it is only necessary that the first control signal can show a shift of 2 k-1 at the maximum. That is, the bit width of the first control signal may be k. Even if the value is smaller than k, the effect of the present invention can be obtained.

Embodiment 2
In the first embodiment, using the reference clock, generation of a seed value (second initial value) for a test pattern for testing the interface circuit 14 and generation of an actual test pattern after generation of the second initial value are performed. An example in which the reference clock is used is shown. However, it is also possible to prepare a separate test clock, generate the second initial value using the reference clock, and use this test clock to generate the actual test pattern after the second initial value is generated. .

  An embodiment corresponding to such a case is shown in FIGS. FIG. 5 is a block diagram of the test pattern generation circuit 1 ′ according to the second embodiment, and FIG. 6 is a block diagram of the first clock control circuit 12 ′. In the second embodiment, selectors 31_1 to 31_n are further provided in the first embodiment (FIG. 1), and the first clock signals CLK1_1 to CLK1_n, which are the outputs of the first clock control circuit 12 ′, and the test clock are provided. Switching is performed using the selection signal SEL. Then, the first clock signals CLK1_1 ′ to CLK1_n ′ are output to the pseudo random number generation circuits 13_1 to 13_n. Further, the first clock control circuit 12 ′ is obtained by replacing the first clock control circuit 12 shown in FIG. 2 with a circuit shown in FIG.

  The first clock control circuit 12 ′ shown in FIG. 6 is different from the first clock control circuit 12 shown in FIG. 2 in that it includes a counter 15 and a clock gating circuit 16_1. The clock gating circuit 16_1 has a function of stopping the output of the first clock signal CLK1_1 by the stop signal of the counter 15. The configuration of the first clock control circuit 12 ′ is the same as that of the first clock control circuit 12 except for the differences described above.

  The counter 15 is a Ct-bit counter that counts the number of reference clocks applied during the test pattern initial value setting period, for example, as described above. The counter 15 receives a reference clock and a reset signal RST. When the reset signal RST is low level, it is initialized (count value is “0”), and the reference clock input after the reset signal RST becomes high level is counted. When the count value reaches Ct, a stop signal is output to the clock gating circuit. In this embodiment, it is assumed that the stop signal is supplied to the clock gating circuit 16_1 with the operation state being high level and the stop state being low level. The counter 15 holds the low level until it is reset after the stop signal is once switched to the low level.

  The clock gating circuit 16_1 outputs the reference clock as the first clock signal CLK1_1 while the reset signal RST and the stop signal are at the high level. Then, when the count value of the counter 15 becomes Ct and the stop signal is set to the low level, the output is stopped (fixed to the low level).

  FIG. 7 is a timing chart showing the operation of the second embodiment. When the count value of the counter 15 reaches Ct at timing T35, the stop signal is switched from the high level to the low level. As a result, a second initial value is set. In addition, the first clock control circuit 12 ′ stops outputting the first clock signals CLK1_1 to CLK1_n to the pseudo random number generation circuits 13_1 to 13_n. At this time, the selection signal SEL is at the low level until the timing T35, and the selectors 31_1 to 31_n use the first clock signals CLK1_1 to CLK1_n, which are the outputs of the first clock control circuit 12 ′, as pseudo random number generation circuits 13_1 to 13_n. Are output as first clock signals CLK1_1 ′ to CLK1_n ′. Subsequently, the selection signal SEL is set to the high level at an arbitrary timing after the timing T35. Accordingly, the selectors 31_1 to 31_n output the test clocks to the pseudo random number generation circuits 13_1 to 13_n as the first clock signals CLK1_1 ′ to CLK1_n ′ (timing T36 in the drawing).

  Here, Ct which is the maximum count value of the counter 15 defines the timing T35. That is, the second initial value of the test pattern generation circuit according to the present invention is set at the timing T35.

  When the reference clock and the test clock are input simultaneously, there is a problem that noise is generated at the timing of switching between the reference clock and the test clock, and a clock that becomes unnecessary after switching (here, the reference clock) becomes a noise source. There's a problem. In order to avoid such a problem, in the above embodiment, the first clock control circuit 12 ′ shown in FIG. 6 is used in place of the first clock control circuit 12 shown in FIG. However, if the clock switching timing or noise generated between the clocks does not matter, the first clock control circuit 12 may be used as it is in the second embodiment.

  In the second embodiment, a high-speed clock can be used as a test clock. It is also possible to use the internal clock of the LSI on which the test pattern generation circuit according to the present invention is mounted as it is as a test clock.

Embodiment 3
FIG. 8 is a block diagram of the test pattern generation circuit 2 according to the third embodiment. As shown in FIG. 8, the clock control circuit 21 of the test pattern generation circuit 2 has a second clock control circuit 22 in addition to the first clock control circuit 12 (FIG. 2). The test pattern generation circuit 2 includes pseudo random number generation circuits 23_1 to 23_n corresponding to the second clock control circuit 22. The pseudo random number generation circuits 23_1 to 23_n are substantially the same as the pseudo random number generation circuits 13_1 to 13_n according to the first embodiment. Each of the interface circuits 14 and 24 is a circuit under test and is connected to a bus wiring (not shown).

  Here, the second clock control circuit 22 will be described in detail. The second clock control circuit 22 receives the first clock signals CLK1_1 to CLK1_n output from the first clock control circuit 12. Then, the second clock control circuit 22 outputs the first clock signals CLK2_1 to CLK2_n based on the input first clock signals CLK1_1 to CLK1_n. At this time, the second clock control circuit 22 determines whether to shift the output start timing of the first clock signals CLK1_1 to CLK1_n and the output start timing of the second clock signals CLK2_1 to CLK2_n based on the second control signal. decide. The second control signal is a 1-bit signal and has two states of “0” (low level) and “1” (high level).

  A block diagram of the second clock control circuit 22 is shown in FIG. As shown in FIG. 9, the second clock control circuit 22 includes counters 25_1 to 25_n, comparators 26_1 to 26_n, and clock gating circuits 27_1 to 27_n. The counters 25_1 to 25_n are provided corresponding to the first clock signals CLK1_1 to CLK1_n, respectively, and count the number of clocks of the first clock signals CLK1_1 to CLK1_n. When the value of the second control signal is “0”, the comparators 26 </ b> _ <b> 1 to 26 </ b> _n output a high level upon reset release without depending on the count value. When the value of the second control signal is “1”, the comparators 26 </ b> _ <b> 1 to 26 </ b> _n compare the count values output from the corresponding counters 25 </ b> _ <b> 1 to 25 </ b> _n with the preset mask values, When the values coincide with the mask values, the corresponding enable signals EN2_1 to EN2_n are set to the high level. On the other hand, when the count value is smaller than the mask value, the comparators 26_1 to 26_n set the corresponding enable signals EN2_1 to EN2_n to the low level. The clock gating circuits 27_1 to 27_n output the first clock signals CLK1_1 to CLK1_n as the first clock signals CLK2_1 to CLK2_n when the enable signals EN2_1 to EN2_n are at a high level. On the other hand, when the enable signals EN2_1 to EN2_n are at the low level, the clock gating circuits 27_1 to 27_n block the first clock signals CLK1_1 to CLK1_n and output the low level. Note that the counters 25_2 to 25_n in the present embodiment hold the values after the count value matches the mask value.

  The operation of the second clock control circuit 22 will be described. FIG. 10 shows a timing chart of the operation of the second clock control circuit 22 when the second control signal is “1”, and FIG. 11 shows the case where the second control signal is “0”. 6 shows a timing chart of the operation of the second clock control circuit 22. 10 and 11 show examples corresponding to the case where the circuits under test 14 and 24 each have a 4-channel configuration. Further, the first clock signals CLK1_1 to CLK1_4 in FIGS. 10 and 11 are output by the first clock control circuit 12 when the value of the first control signal is “1”. 10 and 11, the mask value set in the comparators 26_1 to 26_4 is “4”, and the second clock control circuit 22 outputs the first clock signals CLK2_1 to CLK2_4.

  In the example shown in FIG. 10, the first clock signals CLK1_1 to CLK1_4 are output at timings T41 to T44, respectively. At this time, the counter 25_1 counts the number of clocks of the first clock signal CLK1_1. When this count value becomes “4”, the enable signal EN2_1 output from the comparator 26_1 becomes high level. Then, output of the first clock signal CLK2_1 is started at timing T45. The difference between the timing T45 and the timing T41 is a time corresponding to four clocks of the reference clock. Similarly to the first clock signal CLK2_1, the output of the first clock signals CLK2_2 to CLK2_4 is delayed from the corresponding first clock signals CLK1_2 to CLK2_4 by a time corresponding to four clocks of the reference clock. (Timing T46-T48).

  In the example shown in FIG. 11, the first clock signals CLK1_1 to CLK1_4 are output at timings T51 to T54, respectively. At this time, the counter 25_1 counts the number of clocks of the first clock signal CLK1_1, but the enable signal EN2_1 output from the comparator 26_2 is at a high level regardless of the count value. Therefore, the output of the first clock signal CLK2_1 is started at substantially the same timing as the first clock signal CLK1_1 (timing T51). Similarly to the first clock signal CLK2_1, the output of the first clock signals CLK2_2 to CLK2_4 is started at substantially the same timing as the corresponding first clock signals CLK1_2 to CLK1_4 (timing T52 to T54). That is, in the case of FIG. 11 (when the second control signal is “0” (low level)), the mask value is synonymous with “0”.

  From the above description, the second clock control circuit 22 sets the value of the second control signal between the output start timing of the first clock signals CLK1_1 to CLK1_n and the output start timing of the first clock signals CLK2_1 to CLK2_n. Based on this, it is determined whether or not to have a predetermined deviation amount. That is, by adding the second clock control circuit 22 in addition to the first clock control circuit 12, the clock control circuit 21 can output the first clock signal with more variations than the clock control circuit 11. Can be set. As a result, the test pattern generation circuit 2 according to the third exemplary embodiment can realize a variety of combinations of data in the bus width direction that are more varied than the test pattern generation circuit 1 according to the first exemplary embodiment.

  Note that T49 and T55, which are the timings for setting the second initial value, are applied to all the pseudo random number generation circuits for at least one cycle, as in the first embodiment, and each of the pseudo initial values CLK1_1 to CLK1_4 is simulated. This is the timing at which a random number can be generated. In the present embodiment, if the interface circuits 14 and 24 are n channels, the first control signal is m bits, and the mask value of the second control circuit is L, at least (2 to the power of m−1) × ( It may be set after the timing at which the reference clock for n-1) + L cycles is applied.

  It is also possible to input the first control signal to the second clock control circuit. A block diagram of the test pattern generation circuit 2a in this case is shown in FIG. The test pattern generation circuit 2a shown in FIG. 12 has a second clock control circuit 22a. The second clock control circuit 22a employs a comparator built in the first clock control circuit as a built-in comparator.

  A timing chart of the operation of the second clock control circuit 22a is shown in FIG. The timing chart shown in FIG. 13 shows a case where the value of the first control signal is “1”. As shown in FIG. 13, in this case, the output of the first clock signal CLK2_1 is delayed by a time corresponding to one clock of the reference clock from the first clock signal CLK1_1 (timing T62). The outputs of the first clock signals CLK2_2 to CLK2_4 are also delayed by a time corresponding to one clock of the reference clock from the first clock signals CLK1_1 to CLK1_4 that are the corresponding inputs (timing T63 to T65).

  As described above, even when the first control signal is input to the second clock control circuit, it is possible to have many variations in the output start timing of the first clock signal. In other words, the first clock control circuit and the second clock control circuit constituting the clock control circuit can be controlled by the first control signal having a multi-bit configuration or by the second control signal having a 1-bit configuration. However, it is only necessary to have a clock control circuit based on at least one of the control signals.

Embodiment 4
In the test pattern generation circuit 3 according to the fourth exemplary embodiment, selectors 31_1 to 31_n and 32_1 to 32_n are added to the test pattern generation circuit 2 according to the third exemplary embodiment, and the first clock control circuit 12 is illustrated in the second exemplary embodiment. The first clock control circuit 12 ′ is changed. A block diagram of the test pattern generation circuit 3 is shown in FIG. The selectors 31_1 to 31_n and 32_1 to 32_n are connected to the output terminals of the clock control circuit 21 ′, respectively. The output terminals of the selectors 31_1 to 31_n and 32_1 to 32_n are connected to the corresponding pseudorandom number generation circuits 13_1 to 13_n and 23_1 to 23_n, respectively. The selectors 31_1 to 31_n and 32_1 to 32_n select and output one of the two input signals according to the value of the selection signal SEL.

  In this embodiment, the first clock signals CLK1_1 to CLK1_n and CLK2_1 to CLK2_n are input to one input of the selectors 31_1 to 31_n and 32_1 to 32_n, and the test clock is input to the other input. The test clock may be the same as the reference clock as in the first embodiment, or may be a high-speed clock. Here, in this embodiment, a high-speed clock is applied as a test clock, and an operation clock (for example, a communication clock speed with an external memory) in a normal use state of a semiconductor device on which the test pattern generation circuit 3 is mounted as a high-speed clock. = 533 MHz). The high-speed clock is one in which the skew of the clock that reaches each pseudo-random number generator is adjusted.

  Here, a timing chart showing the operation of the test pattern generation circuit 3 is shown in FIG. In the example shown in FIG. 15, since the selection signal SEL is at the low level until the timing T49, the clock control circuit 21 ′ operates in the same manner as the timing chart shown in FIG. Then, when the second initial values of the pseudo random number generation circuits 13_1 to 13_n and 23_1 to 23_n are set at the timing T49, the selection signal SEL is set to the high level before the test is started at the timing T71. A high-speed clock input after timing T71 is supplied to the pseudo-random number generation circuits 13_1 to 13_n and 23_1 to 23_n. As a result, the pseudo random number generation circuits 13_1 to 13_n and 23_1 to 23_n output pseudo random number data strings in synchronization with the high-speed clock.

  When the timing design of the selection signal SEL with respect to the high-speed clock can be successfully performed, the high-speed clock is continuously applied to the selectors 31_1 to 31_n and 32_1 to 32_n from the beginning, and is switched in synchronization with the high-speed clock at timing T71. May be. Further, as in the third embodiment, as a built-in comparator, a comparator built in the second clock control circuit 22 is replaced with a comparator built in the first clock control circuit 12 ′. The first clock control circuit and the third clock control circuit may be controlled by the first control signal. On the other hand, as a built-in comparator, a fourth clock control circuit in which the comparator built in the first clock control circuit 12 ′ is replaced with a comparator built in the second clock control circuit 22 is configured. However, both the second clock control circuit and the fourth clock control circuit may be controlled by the second control signal.

  From the above description, the test pattern generation circuit 3 can generate a test pattern at a clock frequency corresponding to the operating speed of the semiconductor device. As a result, the actual operation of the semiconductor device can be confirmed, and the reliability of the semiconductor device can be improved.

Embodiment 5
In the fifth embodiment, a test circuit 4 having the test pattern generation circuit 1 according to the first embodiment will be described. FIG. 16 shows the test circuit 4. In addition to the test pattern generation circuit 1, the test circuit 4 includes an interface circuit 14, comparators 43_1 to 43_n, a result holding circuit 44, and a test terminal 45.

  The interface circuit 14 includes a transmission circuit 41 and a reception circuit 42. The transmission circuit 41 and the reception circuit 42 are connected by a wiring FL. As a result, the signal transmitted from the transmission circuit 41 is received by the reception circuit 42.

  The comparators 43_1 to 43_n are provided corresponding to the signal lines of the bus wiring connected to the interface circuit 14. That is, the number of the comparators 43_1 to 43_n and the number of the pseudo random number generation circuits 13_1 to 13_n are the same. The comparators 43_1 to 43_n compare the test pattern output from the pseudo random number generation circuits 13_1 to 13_n with the test pattern input via the interface circuit 14. The result holding circuit 44 holds the test result for each test pattern. The test terminal 45 is a terminal for taking out a test result.

  The operation of the test circuit 4 will be described. First, the test pattern generation circuit 1 completes the setting of the second initial value. Thereafter, when the test is started, the comparators 43_1 to 43_n output the test results based on the comparison result between the test pattern output from the pseudo random number generation circuits 13_1 to 13_n and the test pattern input via the interface circuit 14. Output. The test result is OK if the values of the two patterns match, and NG if the values do not match. The test result is held in the result holding circuit 44. The held test result is output via the test terminal 45 after the test is completed.

  From the above description, according to the test circuit according to the present embodiment, a test pattern having high randomness in the data string direction and the bus width direction generated in the test pattern generation circuit 1 can be used. As a result, it is possible to perform a test with high test coverage including detection of not only circuit failure but also crosstalk failure. Note that the test pattern generation circuit 1 ′, the test pattern generation circuit 2, or the test pattern generation circuit 3 may be adopted as the test circuit 4. As an example, FIG. 17 shows a block diagram when the test pattern generation circuit 2 is employed in the test circuit 4. In the third, fourth, and fifth embodiments, there are two circuits under test (interface circuits 14 and 24), but by adding first and second clock control circuits according to the number of circuits under test, It is possible to generate and provide test patterns for an arbitrary number of circuits under test.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1 is a block diagram of a test pattern generation circuit according to a first embodiment; FIG. 3 is a block diagram of a first clock control circuit according to the first exemplary embodiment; FIG. 6 is a timing chart showing an operation when the value of the first control signal is “1” in the first clock control circuit according to the first exemplary embodiment; FIG. 6 is a timing chart showing an operation when the value of the first control signal is “4” in the first clock control circuit according to the first exemplary embodiment; FIG. 3 is a block diagram of a test pattern generation circuit according to a second exemplary embodiment. FIG. 3 is a block diagram of a first clock control circuit according to a second exemplary embodiment; FIG. 10 is a timing chart showing an operation when the value of the first control signal is “1” in the first clock control circuit according to the second exemplary embodiment; FIG. 6 is a block diagram of a test pattern generation circuit according to a third exemplary embodiment. FIG. 10 is a block diagram of a second clock control circuit according to the third exemplary embodiment; FIG. 10 is a timing chart illustrating an operation when the value of the second control signal is “1” in the second clock control circuit according to the third embodiment; FIG. 10 is a timing chart illustrating an operation when the value of the second control signal is “0” in the second clock control circuit according to the third embodiment; FIG. 10 is a block diagram showing another example of the test pattern generation circuit according to the third exemplary embodiment. FIG. 14 is a timing chart showing an operation when the value of the first control signal is “1” in another example of the second clock control circuit according to the third exemplary embodiment; FIG. 6 is a block diagram of a test pattern generation circuit according to a fourth exemplary embodiment. 6 is a timing chart illustrating an operation of a test pattern generation circuit according to a fourth embodiment; FIG. 10 is a block diagram of a test circuit according to a fifth embodiment; FIG. 10 is a block diagram when a test pattern generation circuit 2 is employed in a test circuit according to a fifth embodiment; It is a block diagram of a test circuit according to Conventional Example 1.

Explanation of symbols

1, 1 ′, 2, 2a, 3 Test pattern generation circuit 4, 4a Test circuit 10 Clock generation circuit 11, 11 ′, 21, 21 ′ Clock control circuit 12, 12 ′ First clock control circuit 13_1 to 13_n, 23_1 ˜23_n Pseudorandom number generation circuit 14, 24 Interface circuit 15, 17_2˜17_n, 25_1˜25_n Counter 16_1˜16_n, 27_1˜27_n Clock gating circuit 18_2˜18_n, 26_1˜26_n, 43_1˜43_n Comparators 22, 22a Second Clock control circuit 31_1 to 31_n, 32_1 to 32_n selector 41, 51 transmission circuit 42, 52 reception circuit 44, 54 result holding circuit 45, 55 test terminal

Claims (11)

A test pattern generation circuit that outputs a test pattern to an interface circuit that is connected to a bus wiring and inputs / outputs multi-bit data in parallel,
A first initial value provided corresponding to each of the signal lines in the bus wiring and having the same value is set in advance, and the first initial value is set according to the input first clock signal. A plurality of pseudo-random number generators for generating a pseudo-random number as a start value;
A test pattern generation circuit comprising: a clock control circuit that arbitrarily determines an output start timing of the first clock signal given to each of the plurality of pseudo-random number generation circuits according to a value of the control signal.   The test pattern generation circuit according to claim 1, wherein the pseudo-random number generation circuit is configured by a shift register that is fed back through an exclusive OR circuit.   The clock control circuit uses a reference clock as an input signal, and sets a supply start timing deviation amount of the first clock signal to the plurality of pseudo-random number generation circuits based on a value of the control signal, or a reference clock It is determined whether to output the reference clock signal with a preset supply start timing deviation amount based on the control signal as an input signal, and based on the determination, the first pseudo-random number generation circuit to the first pseudo random number generation circuit The test pattern generation circuit according to claim 2, further comprising a first clock control circuit that sets a supply start timing deviation amount of the clock signal.   The clock control circuit uses the first clock signal as an input signal and sets a supply start timing deviation amount of the first clock signal to the plurality of pseudo-random number generation circuits based on a value of the control signal, or , Using the first clock signal as an input signal, determining whether to output the reference clock signal with a preset supply start timing deviation based on the control signal, and determining the plurality of pseudo-random numbers based on the determination The test pattern generation circuit according to claim 3, further comprising a second clock control circuit that sets a supply start timing deviation amount of the first clock signal to the generation circuit.   5. The test pattern generation circuit according to claim 3, wherein the clock control circuit is connected to a circuit under test corresponding to each of the first clock control circuit and the second clock control circuit. The first clock control circuit includes a first counter and a clock gating circuit,
The first counter counts the number of clocks of the input reference clock, and outputs a stop signal when the counted value reaches a predetermined value,
6. The test pattern generation circuit according to claim 3, wherein the clock gating circuit receives the input reference clock and outputs the reference clock signal as the first clock signal until the stop signal is received. .   5. The test pattern generation circuit according to claim 4, wherein the second clock control circuit receives the first clock signal output from the first clock control circuit. 6. The control signal includes at least one of a first control signal and a second control signal;
When the clock control circuit is controlled based on the first control signal, the supply start timing deviation amount of the first clock signal to the plurality of pseudo-random number generation circuits is set to the value of the first control signal. 3. The test pattern generation circuit according to claim 2, wherein the test pattern generation circuit determines whether to output the reference clock signal with a preset supply start timing deviation when the control is performed based on the second control signal. .   9. The device according to claim 1, further comprising: a selector that selects one of the first clock signal and the second clock signal and supplies the selected clock signal to the plurality of pseudo-random number generation circuits. Test pattern generation circuit described in 1.   Each of the plurality of pseudo-random number generation circuits is set with a second initial value that is an arbitrary value based on the first initial value and the first clock signal, and the second initial value is used as a start value. The test pattern generation circuit according to claim 1, wherein the pseudo random number is output as the test pattern. A test pattern generation circuit according to claim 1;
A comparator that compares a pseudo-random number input via the interface circuit and a pseudo-random number output by the plurality of pseudo-random number generation circuits;
A test circuit having a result holding circuit for holding the test result output from the comparator and outputting the test result;

Images