JP2008172049A - Manufacturing method of chip parts - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a chip component having a separation process, where the deformation of the chip component is suppressed. <P>SOLUTION: The method for manufacturing the chip component includes: a process for separating a plurality of chip components 7 connected at a frame-like post section 8 mutually; a process for forming the plurality of chip components 7 connected at the frame-like post section 8 mutually on a substrate 9 on which a sacrifice layer 10 made of a metal thin film, where at least not less than two layers are laminated, is formed; and a process for removing the frame-like post section 8 by etching before removing the sacrifice layer 10 by etching for dividing into individual pieces. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a chip component used in various electronic devices.

  Hereinafter, a conventional method of manufacturing a chip component will be described with reference to the drawings.

  FIG. 15 is a manufacturing process diagram showing a conventional chip component manufacturing method, and FIG. 16 is an enlarged exploded perspective view of a portion B in FIG.

  As shown in FIG. 15, the conventional chip component manufacturing process includes a sheet forming process (a), a coil part forming process (b), an element body separating process (c), and an electrode forming process (d). I have.

  First, as shown in FIG. 15A, a plurality of green sheets 100 are formed (sheet forming step (a)).

  Next, as shown in FIGS. 15B and 16, arc-shaped conductors 102 made of a conductive paste such as Ag are printed on a plurality of green sheets 100, and these green sheets 100 are laminated to form a spiral shape. A coil part 103 made of a conductor is formed (coil part forming step (b)). At this time, the arcuate conductors 102 printed on the vertically adjacent green sheets 100 are electrically connected to each other through through holes 104 formed in the green sheet 100 to form a coil portion 103.

  Next, as shown in FIG. 15C, the adjacent element body 105 is cut by a cutting machine 106 using a dicing cutting method, a Thomson cutting method, or the like to form a plurality of chip parts 107 (element body separation step). (C)).

  Then, a terminal electrode or the like is formed on the chip component 107 and fired to produce a finished product 108 (electrode forming step (d)).

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP 11-186084 A

  However, in the above-described conventional configuration, since the adjacent element body 105 is cut by the cutting machine 106 using a dicing cutting method, a Thomson cutting method, or the like in the element body separating step (c), the thickness of the blade of the cutting machine 106 is cut. As much as the cutting width is required, the wear or dimensional distortion of the blade of the cutting machine 106 directly affects the dimensional accuracy, making it difficult to achieve the high dimensional accuracy that is essential for small chip components. Yes.

  If the cutting width of the cutting machine 106 is reduced in order to increase the number of chip parts to be taken per unit area of the green sheet 100, the cutting stress by the cutting machine 106 is easily applied to the chip parts 107, and the chip parts 107 are deformed. It had the problem of producing.

  SUMMARY OF THE INVENTION It is an object of the present invention to provide a chip component manufacturing method that suppresses deformation of chip components and achieves high dimensional accuracy and is suitable for large size and high stacking. Yes.

  In order to solve the above-mentioned conventional problems, the present invention forms a plurality of chip components connected to each other at a frame-shaped post portion on a substrate on which a sacrificial layer made of a metal thin film laminated in two or more layers is formed. And removing the sacrificial layer by etching after removing the frame-shaped post portion by etching.

  In the method of manufacturing a chip component according to the present invention, a sacrificial layer laminated in two or more layers and a frame-shaped post portion are connected to each other in advance, and after removing the frame-shaped post portion by etching, the sacrificial layer is removed. Thus, a plurality of chip parts connected to each other are separated into individual pieces, so that chip parts with high dimensional accuracy can be manufactured. That is, it is possible to provide a manufacturing method of a chip component that achieves high dimensional accuracy in which deformation of the chip component is suppressed and is suitable for large size and high stacking.

(Embodiment 1)
Hereinafter, a method of manufacturing a chip component according to Embodiment 1 of the present invention will be described with reference to the drawings.

  1 is a perspective view of a chip component comprising an LC filter including a coil element and a capacitor element according to Embodiment 1 of the present invention, and FIG. 2 is a post in which a plurality of chip components formed on a substrate having a sacrificial layer are frame-shaped. FIG. 3 is an enlarged view of the coil portion in the inner layer portion of the portion A in FIG. 2, and FIG. 4 is an enlarged view of the capacitor portion. 5 to 14 are cross-sectional process diagrams for explaining a method of manufacturing a chip component made of an LC filter.

  1 to 4, the chip component 7 according to the first embodiment of the present invention is a chip LC filter, in which only the terminal electrode 2 is exposed on one surface of the chip component, and a dielectric material made of a metal oxide and A rectangular element 1 whose constituent material other than an electrode material made of metal is made of a photosensitive resin material, and a coil part 4 and a capacitor part 5 made of a spiral metal 3 embedded in the element 1 are arranged in the stacking direction. The element body 1 is formed by laminating an insulating resin layer 6 made of a cured photosensitive resin obtained by curing a photosensitive resin.

  Furthermore, the minimum distance (end surface margin) between the spiral metal 3 on the outermost periphery of the coil portion 4 and the side surface of the element body 1 is 5 to 50 μm, the maximum diameter of the coil portion 4 is 5 μm to 150 μm, The minimum distance (end surface margin) between the outer periphery and the side surface of the element body 1 is set to 20 to 50 μm. Further, the height of the element body composed of the plurality of laminated insulating resin layers 6 is set to 0.30 to 1.5 mm.

  Next, the manufacturing process of the chip component 7 will be described with reference to FIGS.

  As shown in FIG. 2, the chip component 7 has a plurality of chip components 7 connected to each other by a frame-shaped post portion 8, and a sacrificial layer 10 composed of at least two metal thin film layers. A large number of chips are formed on a silicon substrate and the like. Finally, after separating a plurality of chip components 7 connected by a frame-like post portion 8, the sacrificial layer 10 is etched into individual pieces. This is a method for manufacturing a chip component.

  First, as shown in FIG. 5, for example, an aluminum thin film having a thickness of 80 to 100 nm is formed on a substrate 9 made of a silicon wafer having a thickness of 0.2 to 1.0 mm by plating, sputtering, vapor deposition, or the like. The sacrificial layer 10a is formed.

  Next, a titanium thin film having a thickness of 20 nm is formed on the first sacrificial layer 10a as the second sacrificial layer 10b. The sacrificial layer 10 having a two-layer structure of the first sacrificial layer 10a and the second sacrificial layer 10b is preferable. At this time, the first sacrificial layer 10a is a metal thin film having excellent adhesion to the substrate 9 and having excellent etching properties when the chip component 7 is separated into pieces, and the second sacrificial layer 10b is formed with the insulating resin layer 6. By forming a metal thin film having excellent adhesion strength, it is possible to realize a laminated structure with excellent adhesion even when the thickness of the lamination is increased and the stress is increased. It is possible to provide a method of manufacturing a chip component that can be realized.

  Further, by making the thickness of the first sacrificial layer 10a thinner than the thickness of the second sacrificial layer 10b, the sacrificial layer 10 having excellent adhesion can be formed without sacrificing the etching property. In particular, aluminum is preferable for the first sacrificial layer 10a from the viewpoint of adhesion and etching with the substrate 9, and titanium is particularly preferable for the second sacrificial layer 10b from the viewpoint of adhesion with the insulating resin layer 6. preferable.

  As described above, a sacrificial layer 10 that is a laminated film made of at least two different metal thin films on the substrate 9 is used to provide a chip component manufacturing method capable of realizing large-format and high-stacking with high productivity. can do.

  The thickness of the sacrificial layer 10 is preferably in the range of 20 to 120 nm. If the thickness is less than 20 nm, it is difficult to cover the surface of the substrate 9 uniformly, which is problematic from the viewpoint of flatness. If the thickness exceeds 120 nm, the etching rate is slowed, and the productivity is lowered.

  The substrate 9 is preferably made of silicon, glass or quartz. These materials are preferable from the viewpoints of flatness, surface roughness and material availability. In particular, silicon wafers are the optimal material for this purpose.

  Next, a photosensitive epoxy acrylate resin is formed on the sacrificial layer 10 by using a coating machine such as a spin coater, and then a gap for forming the frame-shaped post portion 8 by photolithography. 11 is formed. The epoxy acrylate resin forming the insulating resin layer 6 is a photosensitive resin material (chemically amplified negative resist agent) having excellent characteristics when forming an electrode pattern having a high aspect ratio. Can be formed. Then, the gap 11a is formed by developing the insulating resin layer 6 by photolithography.

  Next, as shown in FIG. 6, the metal layer 12 is formed using a plating method or the like. The metal layer 12 is formed thicker than a predetermined thickness.

  Thereafter, as shown in FIG. 7, at least the upper surface of the insulating resin layer 6 is removed by using a polishing method or a grinding method. By controlling to a predetermined thickness by such a method, the frame-shaped post portion 8 made of a thin metal material having excellent flatness and dimensional accuracy can be formed.

  Thus, after forming this metal layer 12 thicker than a predetermined thickness, by laminating a method of polishing to at least the upper surface of the insulating resin layer 6 by polishing, a chip excellent in stacking accuracy and dimensional accuracy is obtained. A method for manufacturing a component can be realized.

  From the viewpoint of productivity, the metal layer 12 is preferably formed by a plating method.

  In addition, after forming a base layer by electroless plating, sputtering, or a vapor deposition method, you may form on this base layer by the electrolytic plating method. By using such a method, chip parts having a fine electrode pattern can be manufactured in a lump.

  Then, after forming the insulating resin layer 6 having the void portions 11a, 11b, and 11c on the insulating resin layer 6 having a predetermined pattern as shown in FIG. 8 using a photolithography method, these void portions are formed. 11a, 11b, and 11c are laminated while forming a metal material such as copper using a plating method and a polishing method so that a predetermined pattern of the predetermined spiral metal 3 and the frame-shaped post portion 8 overlaps with high accuracy. By repeating the above, a laminated body in which the coil part 4 made of the spiral metal 3 is formed inside the frame-like post part 8 can be produced. The coil part 4 in FIG. 8 has a two-layer laminated structure consisting of a coil part 4a and a coil part 4b, and this coil part 4 is determined by the inductance value. Thus, the coil part 4 having a predetermined inductance value can be designed.

  The design of the coil unit 4 in the first embodiment is 6.2 nH when the chip size is length; 1.00 × width; 0.50 × thickness; 0.40 mm (1005 size).

  Further, the gap portion 11 includes a plurality of frame-like gap portions 11a for forming the frame-like post portion 8, a spiral void portion 11b disposed inside the frame-like gap portion 11a, and a through hole The frame-shaped gap portion 11a is laminated so as to function as the frame-shaped post portion 8.

  Then, the coil portion 4 made of the spiral metal 3 is formed in the spiral gap portion 11b, the through-hole electrode 15 made of metal is formed in the through-hole gap portion 11c, and the two-layer coil portions 4a and 4b are passed through the through-hole. Conduction is performed by the electrode 15. These gaps 11a, 11b, and 11c can be appropriately arranged in an arbitrary layer to form a desired circuit configuration.

  The width of the post portion 8 is preferably 100 μm or less (not including 0).

  If the width of the post portion 8 exceeds 100 μm, the time required for etching becomes long, and this is not preferable because productivity is lowered and the number of substrates 9 taken per sheet is lowered. And the range of 5-100 micrometers is especially preferable. If it is narrower than 5 μm, photolithographic processing becomes difficult.

  The coil part 4 can be formed in the inner layer part of the insulating resin layer 6 by the process as described above. As a result, the coil portion 4 having a predetermined inductance value of 6.2 nH can be manufactured.

  Thereafter, as shown in FIG. 9, after forming a metal layer 12 made of copper on the base, an aluminum thin film having a thickness of 1000 to 3000 mm is formed as an electrode layer 13a, and silicon dioxide is sputtered on the electrode layer 13a. It is used to form the dielectric layer 14 having a thickness of 0.3 to 1.0 μm. Further, an aluminum thin film similar to the above is formed on the dielectric layer 14 as the electrode layer 13b.

  Next, as shown in FIG. 10, the lower electrode layer 5c, the dielectric layer 5b, and the upper electrode layer 5a constituting the capacitor unit 5 are formed by performing etching while patterning each using a photolithography method. As a result, a 6.2 pF capacitor portion 5 can be manufactured.

  In addition, as the dielectric layer 5b, a capacitor part 5 having desired dielectric characteristics is formed by appropriately selecting a dielectric material made of a metal oxide such as titanium oxide, tantalum oxide, strontium titanate, and forming a thin film. be able to.

  Thereafter, as shown in FIG. 11, the capacitor portion 5 is embedded, and a plurality of layers for forming an electrode pattern for wiring are formed.

  Next, as shown in FIG. 12, a resist pattern 16 is formed by photolithography to protect it from an etching process for individualization in a later step.

  After that, as shown in FIG. 13, the frame-shaped post portion 8 is dissolved and removed by the etching solution, and the sacrifice formed on the substrate 9 using the etching solution that has entered from the gap portion 11 formed by the etching. The layer 10 is removed, and the chip component 7 can be separated into a predetermined chip shape by separating and peeling.

  The main part of the post portion 8 is copper, and the sacrificial layer 10 is composed of a first sacrificial layer 10a made of a metal thin film mainly containing titanium and a second sacrificial layer 10b made of a metal thin film mainly containing aluminum. By using a laminated film, it is possible to realize a chip component manufacturing method that is excellent in large size and high lamination. When the element body 1 having this structure is etched, the post portion 8 made of copper is etched with a ferric chloride aqueous solution, and then the second sacrificial layer 10b made of titanium is made of caustic soda and hydrogen peroxide solution. It is preferable that the first sacrificial layer 10a made of aluminum is etched using a mixed aqueous solution of caustic soda and hydrogen peroxide or a ferric chloride aqueous solution. As a result, it is possible to realize a chip component manufacturing method that enables large size and high stacking and is excellent in etching efficiency and dimensional accuracy.

  Further, by making the main component of the post portion 8 silver and the sacrificial layer 10 having the same configuration as described above, it is possible to achieve a configuration in which both good conductivity and etching properties can be achieved. Thereby, the coil part 4 excellent in electrical characteristics can be formed.

  When etching the element body 1 having this structure, the post portion 8 made of silver is etched using an etching solution made of a mixed acid aqueous solution made of phosphoric acid, acetic acid and nitric acid as an etching solution, and thereafter made of titanium. The second sacrificial layer 10b is etched using a mixed aqueous solution of caustic soda and hydrogen peroxide, and then the first sacrificial layer 10a made of aluminum is mixed using a mixed aqueous solution of sodium hydroxide and hydrogen peroxide or an aqueous ferric chloride solution. Etching is preferable.

  As a result, it is possible to realize a chip component manufacturing method that enables large size and high stacking and is excellent in etching efficiency and dimensional accuracy.

  Next, after removing the resist pattern 16 as shown in FIG. 14, the terminal electrode 2 excellent in mountability is formed by forming an Sn plating electrode on the surface of the exposed terminal electrode 2. Although this terminal electrode 2 takes the structure of a lower surface electrode, the structure of a terminal electrode can be changed as needed.

  By manufacturing chip components through the manufacturing processes as described above, it is possible to realize a manufacturing process that hardly causes etching damage to the substrate 9 in addition to realizing an increase in size and stacking of the substrate 9. In addition, it is possible to provide a chip component manufacturing method capable of significantly increasing the reuse rate of the substrate 9.

  Further, when hydrofluoric acid or the like is used, the etching solution may enter the coil part 4 or the capacitor part 5 to cause a quality problem. By adopting the manufacturing process according to the first embodiment, the coil part 4 or the capacitor is used. It is also possible to suppress the adverse effect of the etching liquid on the portion 5.

  Thus, the first step of forming the sacrificial layer 10 composed of at least the first sacrificial layer 10a and the second sacrificial layer 10b on the substrate 9, and the substrate 9 on which the sacrificial layer 10 is formed. A second step of forming the insulating resin layer 6 having the gap 11, a third step of forming the metal layer 12 on the gap 11 and the insulating resin layer 6, and an upper surface of the insulating resin layer 6. The coil part 4 was included by a manufacturing method including a fourth step of polishing the metal layer 12 until the coil part 4 made of the frame-shaped post part and / or the spiral metal 3 was formed in the gap part 11. By manufacturing a chip component, it is possible to provide a method for manufacturing a chip component that is excellent in dimensional accuracy with reduced processing distortion. Accordingly, it is possible to form a small coil portion 4 having high conductivity and high space factor, and it is possible to provide a chip component manufacturing method capable of realizing highly accurate electrical characteristics with little variation.

  In this manufacturing method, the metal layer 12 is preferably a highly conductive metal such as copper, silver, or an alloy of the metal.

  The insulating resin layer 6 is made of a transparent cured photosensitive resin obtained by curing a photosensitive resin, and the insulating resin layer 6 is particularly preferably an epoxy acrylate resin. This resin can form the insulating resin layer 6 having a high aspect ratio, and can exhibit excellent characteristics when the coil portion 4 is formed with a high space factor. The insulating resin layer 6 is processed into a predetermined shape by a photolithography method, but unlike a resist used in a general photolithography method, it is a resin that constitutes the element body 1 of the final chip component 7. In particular, since static electricity is likely to be generated, a resin layer that suppresses the generation of static electricity may be coated on the surface layer, or a structure that dissipates static electricity may be added.

  As a polishing method for polishing the excess metal layer 12, CMP (Chemical Mechanical Polishing) polishing using a CMP slurry may be used. Since only the metal can be selectively polished while etching the metal layer 12 by CMP polishing, the thickness accuracy is improved. As another polishing method, mechanical polishing using diamond slurry or alumina slurry may be used, but it is disadvantageous in comparison with CMP polishing in terms of accuracy. When a metal layer 12 that is not suitable for etching is used, the portion may be polished by mechanical polishing.

  With the above-described configuration, the plurality of chip components 7 are formed on the substrate 9 which is connected to each other in advance by the frame-shaped post portion 8 and on which the sacrificial layer 10 made of at least two layers of metal thin films is formed. The sacrificial layer 10 is peeled off and the plurality of chip components 7 connected to each other by the frame-like post portion 8 are separated, so that cutting stress is hardly generated in the chip components 7. That is, the chip component 7 can be manufactured while suppressing the deformation of the chip component 7.

  In addition, since the frame-like post portion 8 and the spiral metal 3 are formed by a photolithography method and an individualization process in which stress is hardly generated is performed, the end surface margin from the end surface of the chip component 7 can be minimized, and the chip component Therefore, it is possible to design with good conductor position accuracy utilizing the size of 7 to the maximum. Therefore, the smaller the chip component size is, for example, 1005, 0603, etc., the greater the influence of the end face margin (W) from the end face. In the case of a chip inductor, for example, the inductance value and the Q value are Higher performance than the construction method.

  In particular, the metal layer 12 is formed on the frame-shaped gap 11a and the insulating resin layer 6, and the metal layer 12 is polished to at least the upper surface of the insulating resin layer 6 to form the chip component 7 in the frame-shaped gap 11a. Since the frame-shaped post portion 8 made of a metal connecting the two is formed, the frame-shaped post portion 8 can be easily formed with high accuracy.

  In addition, it is also possible to easily realize the chamfered shape or other shapes of the inner peripheral corner of the frame-shaped gap portion 11a.

  Further, since the insulating resin layer 6 is formed by a photolithography method, the conductor position accuracy, the chip dimensional accuracy, etc. can be easily formed with high accuracy.

  Moreover, by using a transparent photosensitive resin for the insulating resin layer 6, the element body 1 becomes transparent, and the appearance inspection of the conductor is facilitated for each layer.

  Further, the metal layer 12 has an underlayer formed by an electroless plating method, a sputtering method, or a vapor deposition method, and the coil portion 4 having a large space factor is formed by forming an electroplating method on the underlayer. It can be formed easily.

  In the first embodiment, the manufacturing method of the chip component has been described using the LC filter as an example, but the same applies to a chip component such as a chip coil, a multilayer chip capacitor, or a composite component obtained by combining these by the same method. Can be produced.

  As described above, the method for manufacturing a chip component according to the present invention can suppress the deformation of the chip component, realize a large size and high stacking, and realize a chip component manufacturing method with excellent dimensional accuracy. Applicable to equipment.

The perspective view of the chip component in Embodiment 1 of this invention Top view of multiple chip components formed on the same substrate The enlarged plan view of the coil part in the inner layer part of A part of FIG. FIG. 2 is an enlarged plan view of the capacitor portion in the inner layer portion of portion A. Cross-sectional process drawing showing the manufacturing process of the chip component Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Cross-sectional process drawing Manufacturing process diagram for explaining a conventional chip component manufacturing method FIG. 15 is an enlarged exploded perspective view of part B of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Element body 2 Terminal electrode 3 Spiral metal 4, 4a, 4b Coil part 5 Capacitor part 5a Upper electrode layer 5b Dielectric layer 5c Lower electrode layer 6 Insulating resin layer 7 Chip component 8 Post part 9 Substrate 10 Sacrificial layer 10a First Sacrificial layer 10b second sacrificial layer 11, 11a, 11b, 11c gap 12 metal layer 15 through-hole electrode 16 resist pattern

Claims (15)

The step of separating a plurality of chip components connected to each other at the frame-shaped post portion is connected to each other at the frame-shaped post portion on a substrate on which a sacrificial layer made of a metal thin film laminated at least two layers is formed. A method of manufacturing a chip component, comprising: a step of forming a plurality of the chip components; and a step of removing the sacrificial layer by etching after removing the frame-shaped post portion by etching. The chip part manufacturing method according to claim 1, wherein the post portion has a width of 100 μm or less. The method for manufacturing a chip component according to claim 1, wherein the thickness of the sacrificial layer is 20 to 120 nm. 2. The post sacrificial layer is made of copper, the first sacrificial layer is a metal thin film mainly composed of aluminum, and the second sacrificial layer is a metal thin film mainly composed of titanium. Manufacturing method of chip parts. The method for manufacturing a chip part according to claim 4, wherein the thickness of titanium is made thinner than the thickness of aluminum. Etching of the post portion is performed with an aqueous ferric chloride solution, etching of the second sacrificial layer is performed with a mixed aqueous solution of hydrogen peroxide and caustic soda, and etching of the first sacrificial layer is performed with hydrogen peroxide. The manufacturing method of the chip components of Claim 4 performed by the mixed aqueous solution of water and caustic soda, or ferric chloride aqueous solution. The main component of the post portion is silver, the first sacrificial layer is a metal thin film containing aluminum as a main component, and the second sacrificial layer is a metal thin film containing titanium as a main component. Manufacturing method of chip parts. The method for manufacturing a chip part according to claim 7, wherein the thickness of titanium is thinner than the thickness of aluminum. Etching the post portion with a mixed acid aqueous solution of phosphoric acid, acetic acid and nitric acid, etching the second sacrificial layer with a mixed aqueous solution of hydrogen peroxide and caustic soda, and etching the first sacrificial layer. The manufacturing method of the chip components of Claim 7 performed by the mixed aqueous solution of hydrogen oxide water and caustic soda, or ferric chloride aqueous solution. The method of manufacturing a chip component according to claim 1, wherein the substrate is made of silicon, glass, or quartz. A first step of forming a sacrificial layer made of a metal thin film laminated in at least two layers on a substrate, and a second step of forming an insulating resin layer having a gap on the substrate on which the sacrificial layer is formed And a third step of forming a metal layer on the gap and the insulating resin layer, and polishing the metal layer up to the upper surface of the insulating resin layer to form a frame-shaped post portion and / or a plurality of gap portions The chip part manufacturing method according to claim 1, further comprising a fourth step of forming a coil portion made of a spiral metal. The method for manufacturing a chip component according to claim 11, wherein the main component of the metal layer is copper or silver. The manufacturing method of the chip component of Claim 11 which formed the metal layer with the plating method. The method for manufacturing a chip part according to claim 11, wherein the insulating resin layer is made of a cured photosensitive resin obtained by curing a photosensitive resin. The manufacturing method of the chip component of Claim 14 which used the photosensitive resin hardened | cured material as the epoxy acrylate resin.

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