JP2008166749A - Thin film transistor and its manufacturing method, as well as semiconductor device having the thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor having reduced gate leakage failures occurring on an edge of a semiconductor film to have its gate breakdown voltage improved, and to provide its manufacturing method. <P>SOLUTION: The thin film transistor has an island-like semiconductor film with its side end surface having a tapered form, a gate insulation film provided in contact with the surface and the side end surface of the semiconductor film, a gate electrode layer provided on the semiconductor film via the gate insulation film, an insulation film having an aperture provided on the gate electrode layer, and source electrode and drain electrode layers provided in contact with the insulation film having the aperture and connected with the semiconductor film through the aperture. Part of the gate insulation film in contact with the side end surface of the semiconductor film contains halogen and is thicker than a part in contact with the surface of the semiconductor film. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a thin film transistor and a manufacturing method thereof. Further, the present invention relates to a semiconductor device having the thin film transistor.

  In recent years, thin film transistors (also referred to as TFTs) are formed over a substrate having an insulating surface (such as a glass substrate) and a semiconductor device using the TFT as a switching element or the like has been actively manufactured. Yes. In a TFT, a semiconductor film is formed on a surface of an insulating substrate by a CVD method or the like, an island-shaped semiconductor film having a desired pattern is formed by a photolithography process or the like, and one of the island-shaped semiconductor films is formed. The portion is used as a channel formation region (for example, Patent Document 1).

  A schematic diagram of a general TFT is shown in FIG. In FIG. 3, a top-gate thin film transistor 1105 is provided over a substrate 1100. A base film 1101 is provided over a substrate 1100 having an insulating surface, and an island-shaped semiconductor film 1102 is provided through the base film 1101 functioning as a gate insulating film so as to cross the island-shaped semiconductor film 1102 A first conductive film 1104 is provided over the insulating film 1103. An insulating film 1106 is provided over the first conductive film 1104. In addition, the semiconductor film 1102 includes a channel formation region 1102A formed in a region overlapping with the first conductive film 1104 and an impurity region 1102B forming a source region or a drain region. In addition, a second conductive film 1107 is provided which is electrically connected to the impurity region 1102B. 3B and 3C show cross-sectional structures between CD and EF in FIG. 3A, respectively.

In addition, along with demands for higher functionality, higher added value, and smaller size of semiconductor devices, miniaturization of elements included in the semiconductor devices is progressing. In a miniaturized element included in a semiconductor device, when a semiconductor film is thinned, a gate insulating film provided in contact with the semiconductor film according to a design rule is also thinned, and a breakdown voltage of the gate insulating film is lowered. Yes.
JP-A-8-18055

  FIG. 3 shows a conventional thin film transistor. In the top-gate thin film transistor illustrated in FIG. 3, the insulating film 1103 and the first conductive film 1104 are formed in an end portion of the semiconductor film 1102 which is not a source region or a drain region (a region 1108 indicated by a dotted line in FIG. 3C). However, it will overcome the step caused by the thickness of the semiconductor film. Therefore, a CVD method, a sputtering method, or the like can be used for forming the gate insulating film. However, the insulating film formed by these methods does not have good step coverage (also referred to as step coverage). In the case where the step coverage is not good, the thickness of the gate insulating film in the region 1108 is thinner than the thickness of the gate insulating film over the channel formation region of the semiconductor film. As a technique for improving the decrease in the coverage of the gate insulating film due to the step at the end of the semiconductor film, a method in which the end of the active layer is tapered is known, but it is not sufficient. This problem is particularly noticeable when the thickness of the gate insulating film is reduced to several tens of nm.

  In addition, when the thickness of the gate insulating film is not uniform, electric field concentration occurs in a portion where the gate insulating film is thin. When electric field concentration occurs, the leakage current increases and the power consumption of the device increases. Furthermore, when the electric field concentration is excessive, electrostatic breakdown of the gate insulating film occurs and a gate leak defect occurs. As a result, the gate breakdown voltage decreases. These are particularly noticeable when the gate insulating film is thin.

  In view of the above problems, the present invention provides a TFT having a gate insulating film different from the conventional one in a region in contact with a side surface of a semiconductor film and a method for manufacturing a TFT having the gate insulating film. Furthermore, an electronic device having these TFTs is provided.

  The present invention provides a method for manufacturing a thin film transistor, which is a thin film transistor having a halogen in a side end region of a semiconductor film and in which a halogen is added to the side end region of the thin film transistor by a simple method.

  According to one aspect of the present invention, an island-shaped semiconductor film having a tapered side end region, a gate insulating film provided in contact with a surface of the semiconductor film and the side end region, and the gate insulating film on the semiconductor film A gate electrode layer provided through the gate electrode layer, an insulating film having an opening provided on the gate electrode layer, and an insulating film having the opening provided in contact with the semiconductor through the opening. A source electrode and a drain electrode layer connected to the film, wherein the portion of the gate insulating film that contacts the side end region of the semiconductor film contains halogen and is thicker than the portion that contacts the surface of the semiconductor film It is a thin film transistor characterized by this.

  Alternatively, according to one aspect of the present invention, an island-shaped semiconductor film having a tapered side edge region provided on a substrate, and a gate insulating film provided in contact with the surface and the side edge region of the semiconductor film, A gate electrode layer provided on the semiconductor film via the gate insulating film; an insulating film having an opening provided on the gate electrode layer; and an insulating film having the opening. A source electrode and a drain electrode layer connected to the semiconductor film through the opening, a portion of the gate insulating film in contact with a side end region of the semiconductor film containing halogen, and the semiconductor film The thin film transistor is thicker than a portion in contact with the surface of the thin film transistor.

  In the present invention having the above structure, a glass substrate or an SOI substrate can be used as the substrate.

  In the present invention configured as described above, the halogen is preferably fluorine.

  In the present invention having the above structure, the semiconductor film is preferably a crystalline silicon film.

  In the present invention configured as described above, the gate insulating film is preferably a silicon oxide film.

  One aspect of the present invention is a semiconductor device including the thin film transistor of the present invention having the above structure.

  According to one aspect of the present invention, a first resist is formed over a semiconductor film, an island-shaped semiconductor film is formed using the first resist, and a second resist is formed from the first resist. Halogen is added to the side end region of the island-shaped semiconductor film using the second resist, the second resist is removed, and the surface and the side end region of the island-shaped semiconductor film are oxidized to form a gate insulating film Forming a gate electrode layer on the gate insulating film, covering the gate electrode layer, forming an insulating film, and forming a source electrode and a drain electrode layer on the insulating film This is a manufacturing method.

  According to one embodiment of the present invention, a first resist is formed over a semiconductor film, an island-shaped semiconductor film is formed using the first resist, a second resist is formed, and the second resist is used. Halogen is added to the side end region of the island-shaped semiconductor film, the second resist is removed, the surface of the island-shaped semiconductor film and the side end region are oxidized to form a gate insulating film, and the gate A thin film transistor manufacturing method is characterized in that a gate electrode layer is formed over an insulating film, an insulating film is formed to cover the gate electrode layer, and a source electrode and a drain electrode layer are formed over the insulating film.

  In the present invention configured as described above, the second resist is preferably formed by processing the first resist using oxygen gas.

In the present invention having the above structure, it is preferable to use CHF ₃ plasma treatment for the addition of the halogen.

  In the present invention having the above structure, the insulating film is preferably formed by high density plasma.

  In the present specification, the selection ratio is an etching selection ratio. “Etching selectivity can be taken” means that, for example, when a stacked structure having an A layer and a B layer is etched, there is a sufficient difference between the etching rate of the A layer and the etching rate of the B layer. Further, the etching rate refers to the amount to be etched per unit time.

  Note that in this specification, a side end region refers to a region to which a halogen is added at an end portion of a semiconductor film.

  In the semiconductor device of the present invention, the insulating film having a low dielectric constant is formed thicker than the insulating film in contact with the semiconductor film surface so as to be in contact with the side surface of the semiconductor film. Therefore, the gate breakdown voltage in the semiconductor film side end region of the thin film transistor is improved, and the gate leakage defect is reduced. Furthermore, since the electric field strength is reduced in the side end region, the so-called parasitic transistor effect is suppressed.

  The gate insulating film included in the semiconductor device of the present invention is provided by subjecting the semiconductor film to plasma treatment with high-density plasma and oxidizing it. Therefore, interface characteristics between the semiconductor film and the gate insulating film are improved. The high density plasma is preferably surface wave plasma.

  By using the present invention, a thin film transistor with a thin gate insulating film can be manufactured with high yield and high reliability and high reliability.

  Furthermore, since the insulating film in contact with the side surface of the semiconductor film has a lower dielectric constant and is formed thicker than the conventional thin film transistor, it is possible to effectively prevent electrostatic breakdown of the gate insulating film in the end region on the semiconductor film side. it can.

  Furthermore, since halogen is added by plasma treatment using the same resist as that used for etching the semiconductor film, the above-described effect can be produced without complicating the manufacturing process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not interpreted as being limited to the description of this embodiment mode. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings.

(Embodiment 1)
In this embodiment, an example of a semiconductor device of the present invention and a manufacturing method thereof will be described with reference to FIGS.

  FIG. 1 illustrates one mode of a semiconductor device described in this embodiment. 1A is a top view of the semiconductor device described in this embodiment, FIG. 1B is a cross-sectional view taken along line D-E in FIG. 1A, and FIG. A cross-sectional view taken along line FG in A) is shown in FIG.

  The semiconductor device illustrated in FIG. 1 includes a thin film transistor 105 formed over a substrate 100 with a base film 101 interposed therebetween. The thin film transistor 105 includes a first conductive film 104 functioning as a gate electrode formed over the semiconductor film 102 via an insulating film 103 functioning as a gate insulating film, and an insulating film formed over the first conductive film 104. 106, and a second conductive film 107 formed over the insulating film 106. The semiconductor film 102 includes a channel formation region 102A and an impurity region 102B functioning as a source region or a drain region, and a side end region 102C is provided in contact with a side surface of the impurity region 102B of the semiconductor film 102. In the insulating film 103, the thickness of the portion in contact with the side end region 102C is thicker than the region in contact with the channel formation region 102A.

  In this embodiment, a glass substrate is used as the insulating substrate for the substrate 100. The glass substrate is not limited to a specific one. As an example of a glass substrate that can be used, aluminosilicate glass, quartz glass that is alkali-free glass, borosilicate glass, or aluminosilicate glass may be used. The substrate 100 only needs to have heat resistance or the like necessary in the process of forming a thin film, which will be described later.

  Furthermore, an SOI (Silicon On Insulator) substrate, a silicon substrate, or the like can be used as a substrate on which a thin film transistor to which the present invention is applied is formed. By using an SOI substrate or a silicon substrate, a single crystal semiconductor can be used as a semiconductor film, so that high-speed operation is possible and a more highly functional circuit configuration can be realized.

  The SOI substrate may be formed by a method of bonding wafers or a method called SIMOX in which an insulating film is formed inside by implanting oxygen ions into the Si substrate.

  Care must be taken when using borosilicate glass. Borosilicate glass and the like contain some amount of impurities such as sodium (Na) and potassium (K). When these impurities diffuse around the channel formation region 102A, a parasitic channel region is formed at the interface between the channel formation region 102A and the base film 101 or at the interface between the channel formation region 102A and the insulating film 103. Formation of a parasitic channel causes an increase in leakage current generated when the thin film transistor 105 is operated. These diffused impurities also cause a shift in the threshold voltage of the thin film transistor.

  Therefore, when a TFT is manufactured over a glass substrate, a structure in which an insulating film called a base film is sandwiched between the glass substrate and the TFT is preferable. The insulating film called a base film is required to have a function of preventing diffusion of impurities contained in the glass substrate and a function of improving adhesion with a thin film deposited on the insulating film. The material used for the base film is not limited to a specific material, and may be a silicon oxide material or a silicon nitride material. Note that the silicon oxide-based material is silicon oxide (SiOx) containing oxygen and silicon as main components, or silicon oxynitride (SiOxNy) in which silicon oxide contains nitrogen and the oxygen content is higher than the nitrogen content. (0 <y <x)). The silicon nitride-based material is silicon nitride (SiNx) mainly containing nitrogen and silicon, or silicon nitride oxide (SiOxNy (0 <x) in which silicon nitride contains oxygen and the nitrogen content is higher than the oxygen content). <Y)). Or the structure which laminated | stacked the film | membrane which consists of these materials may be sufficient. In the case of stacking and forming, a material that prevents diffusion of impurities from the glass substrate as a blocking layer is used for the lower layer portion that is in close contact with the glass substrate, and the upper layer portion is in close contact with the thin film deposited on the underlying film. It is preferable to use a material that enhances the properties. Thus, in order for the lower layer portion to function as a blocking layer and the upper layer portion to function as a layer that improves adhesion to a thin film (in this embodiment, a semiconductor film) deposited thereon, the lower layer portion is formed of silicon nitride. Preferably, the upper layer portion is a silicon oxide material.

  In view of the above, in this embodiment, the base film 101 is formed as a base film over the substrate 100. Here, the base film 101 is formed by stacking a silicon oxynitride film over a silicon nitride oxide film. The base film 101 can be formed by a method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. Note that in the case where a quartz substrate is used as the substrate, the base film is not particularly necessary and thus may not be formed.

The semiconductor film 102 included in the thin film transistor 105 is preferably crystalline. The semiconductor film 102 includes a channel formation region 102A in a region overlapping with the first conductive film 104, and an impurity region 102B functioning as a source region or a drain region adjacent to the channel formation region 102A. The semiconductor film 102 is formed using a material containing silicon as a main component. Examples of the material containing silicon as a main component include silicon (Si) and silicon germanium (Si _x Ge _1-x ). In this embodiment mode, a polycrystalline silicon film is used as the semiconductor film 102. The semiconductor film 102 may be formed to have a thickness of 50 nm or less, preferably 10 nm to 50 nm. More preferably, it is formed to be 10 nm or more and 30 nm or less.

However, the present invention is not limited to this, and an amorphous semiconductor may be used as the semiconductor film, or a semi-amorphous semiconductor (hereinafter referred to as SAS) may be used. Good. Note that a SAS is a semiconductor having an intermediate structure between an amorphous semiconductor and a semiconductor having a crystal structure (including single crystal and polycrystal). This SAS is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline semiconductor having a short-range order and having a lattice distortion, and having a grain size of 0.5 to 20 nm. It can be dispersed in the crystalline semiconductor film. In SAS, the Raman spectrum is shifted to a lower wavenumber than 520 cm ⁻¹ , and diffraction peaks of (111) and (220) that are derived from the Si crystal lattice are observed in X-ray diffraction. In addition, in order to terminate dangling bonds (dangling bonds), at least 1 atomic% or more of hydrogen or halogen is included. In this specification, such a semiconductor is referred to as a SAS for convenience. Furthermore, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, a SAS having improved stability and good characteristics can be obtained. Note that microcrystalline semiconductors (microcrystalline semiconductors) are also included in SAS. SAS can be obtained by glow discharge decomposition of a gas containing silicon. As a typical gas containing silicon, silane (SiH ₄ ) can be used, and Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can also be used. In addition, the gas containing silicon and at least one kind of rare gas element selected from helium, argon, krypton, and neon is used by diluting the gas containing silicon to facilitate the formation of the SAS. It can be. It is preferable to dilute the gas containing silicon so that the dilution rate becomes 2 to 1000 times. Furthermore, by mixing a gas containing silicon, a carbide gas such as CH ₄ and C ₂ H ₆ , a germanium gas such as GeH ₄ and GeF ₄ , F _2, etc., the energy bandwidth is 1.5 to You may adjust to 2.4 eV or 0.9-1.1 eV.

In forming the crystalline semiconductor film 102, an amorphous semiconductor film of silicon is first formed. When forming the amorphous semiconductor film, it is preferably formed by using a semiconductor material gas such as monosilane (SiH ₄ ) by LPCVD (Low Pressure CVD) method, plasma CVD method, vapor phase growth method or sputtering method. . In addition, disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used.

Before the amorphous semiconductor film is crystallized, a dehydrogenation step may be performed as necessary. When a normal CVD method using silane (SiH ₄ ) is applied in forming the amorphous semiconductor film, hydrogen remains in the film. When the semiconductor film is irradiated with laser light in a state where hydrogen remains in the film in this manner, the film disappears due to laser light having an energy value about half of the energy value optimum for crystallization. Therefore, it is preferable to go through a dehydrogenation step. The dehydrogenation step is performed by heating the substrate on which the amorphous semiconductor film is formed in a nitrogen (N ₂ ) atmosphere. By this step, hydrogen remaining in the film can be removed. In the case where the amorphous semiconductor film is formed by the LPCVD method or the sputtering method, the dehydrogenation step is not necessarily required.

  Moreover, you may perform channel dope as needed. Channel doping means that an impurity having a predetermined concentration is added to a channel formation region of a semiconductor film, the threshold voltage of the thin film transistor is intentionally shifted, and the threshold value of the thin film transistor is controlled to a desired value. For example, when the threshold voltage is shifted to the negative side, a p-type impurity element is added as a dopant. When the threshold voltage is shifted to the positive side, an n-type impurity element is added to the dopant. Examples of the p-type impurity element include phosphorus (P) and arsenic (As), and examples of the n-type impurity element include boron (B) and aluminum (Al).

  Here, the amorphous semiconductor film is crystallized. Although heat energy and light energy can be used for crystallization of the amorphous semiconductor film, laser light is used for crystallization of the amorphous semiconductor film in this embodiment mode. By irradiating with laser light, the heat necessary for crystallization is supplied to the amorphous semiconductor film. By using laser light, the amorphous semiconductor film can be locally heated. When glass is used for the substrate, the amorphous semiconductor film is set so that the temperature of the substrate is lower than the strain point of the glass. Can be crystallized.

  The laser is composed of a laser medium, an excitation source, and a resonator. Lasers can be classified into gas lasers, liquid lasers, and solid-state lasers according to the medium. Free lasers, semiconductor lasers, and X-ray lasers can be classified according to the characteristics of oscillation. In the present invention, any laser is used. Also good. Note that a gas laser or a solid laser is preferably used, and a solid laser is more preferably used.

  Gas lasers include helium neon laser, carbon dioxide laser, excimer laser, and argon ion laser. The excimer laser includes a rare gas excimer laser and a rare gas halide excimer laser. A rare gas excimer laser has oscillation by three types of excited molecules, argon, krypton, and xenon. Argon ion lasers include rare gas ion lasers and metal vapor ion lasers.

  Liquid lasers include inorganic liquid lasers, organic chelate lasers, and dye lasers. Inorganic liquid lasers and organic chelate lasers use rare earth ions such as neodymium, which are used in solid-state lasers, as laser media.

A laser medium used by a solid-state laser is obtained by doping a solid matrix with an active species that acts as a laser. The solid matrix is a crystal or glass. The crystal is YAG (yttrium / aluminum / garnet crystal), YLF, YVO ₄ , YAlO ₃ , sapphire, ruby, or alexandride. In addition, the active species having a laser action are, for example, trivalent ions (Cr ³⁺ , Nd ³⁺ , Yb ³⁺ , Tm ³⁺ , Ho ³⁺ , Er ³⁺ , Ti ³⁺ ).

  The laser used in this embodiment mode only needs to emit laser light having a wavelength that is absorbed by the amorphous semiconductor film. In this embodiment mode, since silicon is used for the amorphous semiconductor film, the wavelength of the laser light used may be 800 nm or less, more preferably about 350 to 550 nm, which is absorbed by silicon.

  A thermal crystallization method using an element that promotes crystallization, such as nickel (Ni), may be used for crystallization of the amorphous semiconductor film.

The crystallized semiconductor film is selectively etched and removed. For etching the semiconductor film, a resist pattern is selectively formed on the semiconductor film and dry etching is performed. Here, the etching gas to be used is not limited to a specific one, but at least the etching selectivity with respect to the base film needs to be sufficient. In other words, a material having a low etching rate for the base film and a high etching rate for the semiconductor film may be used. As an example of a gas used for etching a semiconductor film, a chlorine-based gas such as Cl ₂ , BCl ₃ , or SiCl ₄ , or a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , CHF ₃ , or CF ₄ is used. Can do.

  Further, the semiconductor film formed in this embodiment has a tapered side end region. A method for manufacturing a semiconductor film having a tapered shape is described with reference to FIGS.

First, a first resist 131 is formed at a desired position on the semiconductor film 130 formed over the entire surface (see FIG. 4A). Next, dry etching is performed with the first resist 131 formed. As the etching gas used at this time, a gas having a low etching rate for the base film 101 and a high etching rate for the first resist 131 and the semiconductor film 130 is selected. By using such a gas, the semiconductor film 130 can be etched without removing the base film 101 by etching, and the first resist 131 is retracted along with the etching of the semiconductor film 130 and the second film is removed. The resist 133 can be obtained. Therefore, a difference occurs in the etching depth of the semiconductor film 130 which is a film to be etched, and the side edge of the formed semiconductor film 132 can be tapered with a taper angle θ (see FIG. 4B). .) As an example of the gas that can be used here, a mixed gas of CF ₄ and O ₂ or a mixed gas of SF ₆ and O ₂ can be given. CF ₄ and SF ₆ have a high etching rate with respect to silicon forming the semiconductor film, and O ₂ recedes the resist. Therefore, the taper angle θ can be adjusted by adjusting the gas ratio of these mixed gases. That is, when the gas ratio of CF ₄ or SF ₆ is increased, the etching rate of silicon increases, and when the gas ratio of O ₂ is increased, the receding of the resist proceeds. Therefore, when the gas ratio of CF ₄ or SF ₆ is increased, the taper angle is increased. When the gas ratio of O ₂ is increased, the taper angle tends to decrease. Therefore, the gas ratio may be adjusted as appropriate according to the desired taper angle.

Next, plasma treatment is performed in order to add halogen to the side edge of the semiconductor film 132 with the second resist 133 left (see FIG. 4C). In this embodiment mode, fluorine (F) is used as a halogen to be added. Examples of the gas used for the plasma treatment include a mixed gas of C ₂ F ₆ and H _2, a mixed gas of C ₄ F ₈ and H ₂ , or a mixed gas of CHF ₃ and He. Here, CHF ₃ and He are used. The mixed gas is used. As an example, the gas flow ratio is 7.5: 142.5 (sccm), the pressure in the chamber is 5.5 Pa, and 475 W of RF (13.56 MHz) power is applied to the coil-type electrode. Plasma treatment can be performed by applying 300 W of RF (13.56 MHz) power to the substrate side. More preferably, the gas flow ratio is 56: 144 (sccm), the pressure in the chamber is 7.5 Pa, and 25 W of RF (13.56 MHz) power is applied to the coiled electrode to generate plasma. The plasma treatment is preferably performed by supplying 425 W of RF (13.56 MHz) power to the substrate side. By performing the treatment under such conditions, fluorine (F) can be added to the side end region surface of the semiconductor film 132. After the plasma treatment, light ashing is performed with O ₂ plasma, and the resist is removed by peeling using a predetermined chemical solution (see FIG. 4D).

Note that since CHF ₃ is used in the above plasma treatment, the base film in a region which does not overlap with the semiconductor film 132 can be slightly etched. Therefore, it is preferable to adjust plasma generation conditions so that etching of the base film 101 does not progress.

Next, the insulating film 103 is formed. The insulating film 103 is formed by plasma treatment and is formed using silicon oxide (SiO _x ) (see FIG. 4E).

Since the side end region 132C of the semiconductor film 132 containing fluorine (F) has a high oxidation rate, the oxidation proceeds preferentially in the side end region 132C of the semiconductor film 132. In the case of forming a silicon oxide (SiO _x ) film or a silicon oxynitride (SiN _x O _y (x>y> 0)) film as the gate insulating film, it is compared with the oxidation rate of the surface of the semiconductor film in contact with the gate insulating film. Since the oxidation rate of the side end region 132C of the semiconductor film 132 is high, the gate insulating film in the side end region can be formed thick. Note that the side end region 132C may contain chlorine (Cl).

  Note that since the plasma treatment is performed from the surface of the semiconductor film 132, not only the side end region 132C of the semiconductor film 132 but also the surface of the semiconductor film 132 in contact with the insulating film 103 is oxidized. Accordingly, an insulating film is also formed on the surface of the semiconductor film 132 in contact with the insulating film 103.

As described above, the insulating film 103 can be formed using a single layer or a stacked layer of a silicon oxide (SiO _x ) film and a silicon oxynitride (SiO _x N _y ) (x>y> 0) film.

Note that as the atmosphere containing oxygen (O ₂ ), for example, oxygen and hydrogen (H ₂ ) in a mixed gas atmosphere of oxygen and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe). And a rare gas mixed gas atmosphere, a mixed gas atmosphere of dinitrogen monoxide (N ₂ O) and a rare gas, or a mixed gas atmosphere of dinitrogen monoxide, hydrogen, and a rare gas. . For example, a mixed gas containing oxygen, hydrogen, and argon (Ar) can be used. In that case, a mixed gas containing 0.1 to 100 sccm of oxygen, 0.1 to 100 sccm of hydrogen, and 100 to 5000 sccm of argon can be used. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

Note that the plasma treatment is performed using plasma with an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of 1.5 eV or less in the atmosphere of the gas. More specifically, plasma having an electron density of 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and an electron temperature of 0.5 eV to 1.5 eV is used. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor film 132) formed on the substrate is low, damage to the object to be processed can be prevented. it can. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or nitride film formed by oxidizing an object to be irradiated using plasma treatment can be formed by CVD or sputtering. Compared with a film formed by a method or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, sufficient oxidation can be performed even if the plasma treatment is performed at a temperature 100 degrees or more lower than the strain point of the glass substrate. As a frequency for forming plasma, a high frequency such as a microwave (2.45 GHz) can be used.

Note that nitriding treatment may be performed by plasma after the insulating film 103 is formed. As an atmosphere containing nitrogen, for example, a mixture of nitrogen, hydrogen, and a rare gas in a mixed gas atmosphere of nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) The reaction can be performed in a gas atmosphere or a mixed gas atmosphere of ammonia (NH ₃ ) and a rare gas.

  Side end region 132C in the present embodiment contains fluorine (F). Therefore, oxidation is promoted, and the thickness of the portion of the gate insulating film in this embodiment in contact with the side end region 132C of the semiconductor film 132 is larger than that in contact with the surface of the semiconductor film 132. Furthermore, since the side end region 132C of the semiconductor film 132 contains fluorine (F), a SiOF film or a film close to the SiOF film is formed. Since the SiOF film is a low-k film, the dielectric constant is smaller than the dielectric constant at the position overlapping the surface of the semiconductor film. By forming the gate insulating film in this way, a low dielectric constant insulating film is formed so as to be in contact with the side surface of the semiconductor film, so that a film having a high withstand voltage in the side end region of the semiconductor film and a low leakage current is formed. can do. Further, since the insulating film formed by plasma treatment has a uniform thickness and is dense, an insulating film with high withstand voltage and low leakage current can be formed.

  Alternatively, chlorine (Cl) may be used as the halogen added to the side end region 132C. By using chlorine as an element added to the side end region 132C, participation of the side end region 132C is promoted, and the thickness of the portion of the semiconductor film 132 in contact with the side end region 132C is larger than the position overlapping the surface of the semiconductor film 132. A gate insulating film can be formed to be large.

  Note that in the semiconductor device of this embodiment, by reducing the taper angle of the side end region of the semiconductor film included in the thin film transistor, the area of the semiconductor film end exposed to the halogen can be increased, and the side end region can be increased. Halogen can be easily added to 132C. Furthermore, by reducing the taper angle of the side end region, step coverage (step coverage) of the first conductive film formed on the side end region can be improved. However, the present invention is not limited to this, and the taper angle may be 45 ° or more and 90 ° or less.

FIG. 14 shows two thin film transistors having different taper angles in the side end regions of the semiconductor film. The taper angle (θ ₁ ) of the side end region 140C of the semiconductor film 140 in FIG. 14A is smaller than the taper angle (θ ₂ ) of the side end region 141C of the semiconductor film 141 in FIG. 14B. Therefore, compared with the semiconductor device illustrated in FIG. 14B, the semiconductor device illustrated in FIG. 14A has a step coverage of the gate insulating film formed over the semiconductor film and the second conductive film over the gate insulating film. Will be better. Further, a shape having a small taper angle is preferable because halogen can be easily added to the side end region of the semiconductor film even in the formation process.

  Next, the first conductive film 104 functioning as a gate electrode is selectively formed. The first conductive film 104 can be formed by forming a film using a CVD method, a sputtering method, a droplet discharge method, or the like, and performing etching so that a desired pattern is obtained. The first conductive film 104 includes tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), nickel ( One or a plurality of elements selected from Ni) and neodymium (Nd), or an alloy material or a compound material containing the element as a main component may be used. When aluminum (Al) is used as the first conductive film 104, hillocks are suppressed by using an Al—Ta alloy that is alloyed by adding tantalum (Ta). In addition, it is preferable to use an Al—Nd alloy obtained by adding neodymium (Nd) because not only hillocks are suppressed but also low-resistance wiring can be formed. Alternatively, a semiconductor film typified by polycrystalline silicon doped with an impurity element such as phosphorus (P) or an AgPdCu alloy may be used. Further, it may be a single layer or a stacked layer. For example, a two-layer structure including a titanium nitride film and a molybdenum film, or a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum / silicon alloy film, and a 30 nm-thickness titanium nitride film are stacked. It is good. In the case of a three-layer structure, tungsten nitride may be used in place of the first tungsten layer of the first conductive film, or the aluminum and silicon alloy film of the second layer of the first conductive film. Instead of this, an alloy film of aluminum and titanium may be used, or a titanium film may be used instead of the third titanium nitride film of the first conductive film. The first conductive film 104 may be formed with a single layer or a stacked layer.

  Note that a gate electrode refers to a portion of a conductive film which overlaps with a semiconductor film that forms a channel region, an LDD (Lightly Doped Drain) region, or the like with a gate insulating film in a thin film transistor. A gate wiring refers to a wiring for connecting a gate electrode to another thin film transistor or connecting a gate electrode to another wiring. However, there is a portion that functions as a gate electrode and also functions as a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region that overlaps with an extended gate wiring, the region functions as a gate wiring, but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring.

Next, using the first conductive film 104 as a mask, an impurity element of one conductivity type is added to the semiconductor film 102 to form an impurity region. The impurity region functions as a source region or a drain region. Here, as the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. For example, phosphorus (P) may be added as an impurity element to the semiconductor film 132 so as to be contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ , so that an impurity region exhibiting n-type conductivity may be formed. Although not illustrated, a low concentration impurity region (LDD region) to which an impurity is added at a lower concentration than the source region or the drain region may be formed between the channel formation region and the source region or the drain region. After the addition of impurities, annealing is performed to activate the impurities.

  Note that an LDD region is a region formed for the purpose of improving reliability in a thin film transistor whose semiconductor film is polycrystalline silicon. In a TFT in which the semiconductor film is polycrystalline silicon, it is important to suppress the off current, and a sufficiently low off current is required particularly when used as an analog switch such as a pixel circuit. However, due to the reverse bias strong electric field at the drain junction, there is a leakage current through the defect even at the off time. Since the electric field in the vicinity of the drain end is relaxed by the LDD region, the off-current can be reduced. Further, the reverse bias electric field at the drain junction can be distributed to the junction between the channel region and the LDD region, and the junction between the LDD region and the drain region, and the electric field at the drain end is relaxed, so that the leakage current is reduced. .

  Next, the insulating film 106 is formed. The insulating film 106 is formed by CVD, sputtering, or the like, using silicon oxide, silicon oxynitride (SiOxNy (x> y> 0)), silicon nitride oxide (SiNxOy (x> y> 0)), diamond-like carbon ( DLC) or the like can be used. In addition, organic materials such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acryl, and epoxy, siloxane materials such as siloxane resins, oxazole resins, etc. formed by spin coating, droplet discharge, screen printing, etc. It can be formed as a single layer or a stacked layer. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used. The oxazole resin is, for example, photosensitive polybenzoxazole. Photosensitive polybenzoxazole has a low dielectric constant (dielectric constant 2.9 at room temperature of 1 MHz) and high heat resistance (differential thermogravimetric-differential thermal analysis (TG / TDA) temperature rise of 5 ° C./min. And a thermal decomposition temperature of 550 ° C.) and a low water absorption rate (0.3% at room temperature for 24 hours). Oxazole resin has a low relative dielectric constant (about 2.9) compared to the relative dielectric constant (about 3.2 to 3.4) of polyimide, etc., so that the generation of parasitic capacitance is suppressed and high speed operation is performed. Can do. Here, as the insulating film 106, a single layer or a stack of silicon oxide, silicon oxynitride (SiOxNy (x> y> 0)), or silicon nitride oxide (SiNxOy (x> y> 0)) formed by a CVD method is used. Form. Further, an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy, a siloxane material such as a siloxane resin, or an oxazole resin may be stacked.

  Next, a second conductive film 107 to be an electrode or a wiring is formed. The second conductive film is not limited to a specific object. As with the first conductive film 104, the second conductive film 107 can be selectively formed by forming a film using a CVD method, a sputtering method, or the like and performing etching so as to form a pattern. . Alternatively, a droplet discharge method may be used. The first conductive film 104 includes tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), nickel ( One or a plurality of elements selected from Ni) and neodymium (Nd), or an alloy material or a compound material containing the element as a main component may be used. When aluminum (Al) is used for the conductive film, hillocks are suppressed by using an Al—Ta alloy that is alloyed by adding tantalum (Ta). In addition, it is preferable to use an Al—Nd alloy obtained by adding neodymium (Nd) because not only hillocks are suppressed but also low-resistance wiring can be formed. Alternatively, a semiconductor film typified by polycrystalline silicon doped with an impurity element such as phosphorus (P) or an AgPdCu alloy may be used. Further, it may be a single layer or a stacked layer. For example, a two-layer structure including a titanium nitride film and a molybdenum film, or a three-layer structure in which a tungsten film with a thickness of 50 nm, an alloy film of aluminum and silicon with a thickness of 500 nm, and a titanium nitride film with a thickness of 30 nm are stacked. It is good also as a structure. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or an alloy of aluminum and titanium instead of the alloy film of aluminum and silicon of the second conductive film. A film may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. The conductive film may be formed with a single layer or a stacked layer.

  As described above, the thin film transistor of the present invention is formed. Note that the structure of the transistor can take a variety of forms and is not limited to a specific structure. For example, a multi-gate structure in which the number of gates per transistor is two or more may be used. With the multi-gate structure, the off-current is reduced, the breakdown voltage of the transistor is improved, the reliability is improved, and even if the drain-source voltage changes when operating in the saturation region, the drain-source current does not change. It does not change so much and can be made flat.

  In the semiconductor device of the present invention, the insulating film having a low dielectric constant in contact with the side surface of the semiconductor film is formed thicker than the insulating film in contact with the surface of the semiconductor film. Therefore, the gate breakdown voltage in the semiconductor film side end region of the thin film transistor is improved, and the gate leakage defect is reduced. Furthermore, since the electric field strength is reduced in the side end region, the so-called parasitic transistor effect is suppressed.

  The gate insulating film included in the semiconductor device of the present invention is provided by subjecting the semiconductor film to plasma treatment with high-density plasma and oxidizing it. Therefore, interface characteristics between the semiconductor film and the gate insulating film are improved. That is, it is possible to form a gate insulating film not only having a high breakdown voltage in the semiconductor film side end region but also having a high breakdown voltage on the surface in contact with the semiconductor film surface.

  By using the present invention, a thin film transistor with a thin gate insulating film can be manufactured with high yield and high reliability and high reliability.

  Furthermore, since the insulating film in contact with the side surface of the semiconductor film has a lower dielectric constant and is formed thicker than the conventional thin film transistor, it is possible to effectively prevent electrostatic breakdown of the gate insulating film in the end region on the semiconductor film side. it can.

  Furthermore, since halogen is added by plasma treatment using the same resist as that used for etching the semiconductor film, the above-described effect can be produced without complicating the manufacturing process.

  Since the thick insulating film that is in contact with the side end region of the channel formation region of the semiconductor film under the gate electrode is provided, it is possible to reduce the influence on the semiconductor device due to the poor coating of the gate insulating film on the semiconductor film surface.

(Embodiment 2)
In this embodiment, an example of a semiconductor device of the present invention and a manufacturing method thereof, which is different from that in Embodiment 1, will be described with reference to FIGS.

  FIG. 2 shows one mode of a semiconductor device described in this embodiment mode. 2A is a top view of the semiconductor device described in this embodiment, FIG. 2A is a cross-sectional view taken along line D-E in FIG. 2A, and FIG. ) Is a cross-sectional view taken along line FG in FIG.

  The semiconductor device illustrated in FIG. 2 includes the thin film transistor 205 formed over the substrate 200 with the base film 201 interposed therebetween, similarly to the semiconductor device illustrated in FIG. The thin film transistor 205 includes a first conductive film 204 provided over a semiconductor film 202 with an insulating film 203 functioning as a gate insulating film, an insulating film 206 provided over the first conductive film 204, and an insulating film And a second conductive film 207 formed over 206. In the insulating film 203, the thickness of the portion in contact with the side end region 202C is thicker than the region in contact with the channel formation region 202A. As the substrate 200, a glass substrate, an SOI substrate, a silicon substrate, or the like can be used similarly to the substrate 100 in Embodiment 1, and the base film 201 can be formed in the same manner as the base film 201 in Embodiment 1.

The semiconductor film 202 included in the thin film transistor 205 is preferably crystalline. The semiconductor film 202 includes a channel formation region 202A in a region overlapping with the first conductive film 204, and an impurity region 202B functioning as a source region or a drain region adjacent to the channel formation region 202A. The semiconductor film 202 is formed using a material containing silicon as a main component. Examples of the material mainly containing silicon include silicon (Si) and silicon germanium (Si _x Ge _y (0 <y <x)). In this embodiment mode, a polycrystalline silicon film is used as the semiconductor film 202. The semiconductor film 202 may be formed to a thickness of 50 nm or less, preferably 10 nm to 50 nm. More preferably, it is formed to be 10 nm or more and 30 nm or less.

However, the present invention is not limited to this, and an amorphous semiconductor may be used as the semiconductor film, or a semi-amorphous semiconductor (hereinafter referred to as SAS) may be used. Good. Note that a SAS is a semiconductor having an intermediate structure between an amorphous semiconductor and a semiconductor having a crystal structure (including single crystal and polycrystal). This SAS is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline semiconductor having a short-range order and having a lattice distortion, and having a grain size of 0.5 to 20 nm. It can be dispersed in the crystalline semiconductor film. In SAS, the Raman spectrum is shifted to a lower wavenumber than 520 cm ⁻¹ , and diffraction peaks of (111) and (220) that are derived from the Si crystal lattice are observed in X-ray diffraction. In addition, in order to terminate dangling bonds (dangling bonds), at least 1 atomic% or more of hydrogen or halogen is included. In this specification, such a semiconductor is referred to as a SAS for convenience. Furthermore, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, a SAS having improved stability and good characteristics can be obtained. Note that microcrystalline semiconductors (microcrystalline semiconductors) are also included in SAS. SAS can be obtained by glow discharge decomposition of a gas containing silicon. As a typical gas containing silicon, silane (SiH ₄ ) can be used, and Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can also be used. In addition, the gas containing silicon and at least one kind of rare gas element selected from helium, argon, krypton, and neon is used by diluting the gas containing silicon to facilitate the formation of the SAS. It can be. It is preferable to dilute the gas containing silicon so that the dilution rate becomes 2 to 1000 times. Furthermore, by mixing a gas containing silicon, a carbide gas such as CH ₄ and C ₂ H ₆ , a germanium gas such as GeH ₄ and GeF ₄ , F _2, etc., the energy bandwidth is 1.5 to You may adjust to 2.4 eV or 0.9-1.1 eV.

In forming the crystalline semiconductor film 202, first, an amorphous semiconductor film of silicon is formed. When forming the amorphous semiconductor film, it is preferably formed by using a semiconductor material gas such as monosilane (SiH ₄ ) by LPCVD (Low Pressure CVD) method, plasma CVD method, vapor phase growth method or sputtering method. . In addition, disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used.

Before the amorphous semiconductor film is crystallized, a dehydrogenation step may be performed as necessary. When a normal CVD method using silane (SiH ₄ ) is applied in forming the amorphous semiconductor film, hydrogen remains in the film. When the semiconductor film is irradiated with laser light in a state where hydrogen remains in the film in this manner, the film disappears due to laser light having an energy value about half of the energy value optimum for crystallization. Therefore, it is preferable to go through a dehydrogenation step. The dehydrogenation step is performed by heating the substrate on which the amorphous semiconductor film is formed in a nitrogen (N ₂ ) atmosphere. By this step, hydrogen remaining in the film can be removed. In the case where the amorphous semiconductor film is formed by the LPCVD method or the sputtering method, the dehydrogenation step is not necessarily required.

  Moreover, you may perform channel dope as needed. Channel doping means that an impurity having a predetermined concentration is added to a channel formation region of a semiconductor film, the threshold voltage of the thin film transistor is intentionally shifted, and the threshold value of the thin film transistor is controlled to a desired value. For example, when the threshold voltage is shifted to the negative side, a p-type impurity element is added as a dopant. When the threshold voltage is shifted to the positive side, an n-type impurity element is added to the dopant. Examples of the p-type impurity element include phosphorus (P) and arsenic (As), and examples of the n-type impurity element include boron (B) and aluminum (Al). Note that the timing at which channel doping is performed is not limited to a specific one, but is preferably performed before crystallization.

  Here, the amorphous semiconductor film is crystallized. Although heat energy and light energy can be used for crystallization of the amorphous semiconductor film, laser light is used for crystallization of the amorphous semiconductor film in this embodiment mode. By irradiating with laser light, the heat necessary for crystallization is supplied to the amorphous semiconductor film. By using laser light, the amorphous semiconductor film can be locally heated. When glass is used for the substrate, the amorphous semiconductor film is set so that the temperature of the substrate is lower than the strain point of the glass. Can be crystallized.

  The laser is composed of a laser medium, an excitation source, and a resonator. Lasers can be classified into gas lasers, liquid lasers, and solid-state lasers according to the medium. Free lasers, semiconductor lasers, and X-ray lasers can be classified according to the characteristics of oscillation. In the present invention, any laser is used. Also good. Note that a gas laser or a solid laser is preferably used, and a solid laser is more preferably used.

  Gas lasers include helium neon laser, carbon dioxide laser, excimer laser, and argon ion laser. The excimer laser includes a rare gas excimer laser and a rare gas halide excimer laser. A rare gas excimer laser has oscillation by three types of excited molecules, argon, krypton, and xenon. Argon ion lasers include rare gas ion lasers and metal vapor ion lasers.

  Liquid lasers include inorganic liquid lasers, organic chelate lasers, and dye lasers. Inorganic liquid lasers and organic chelate lasers use rare earth ions such as neodymium, which are used in solid-state lasers, as laser media.

A laser medium used by a solid-state laser is obtained by doping a solid matrix with an active species that acts as a laser. The solid matrix is a crystal or glass. The crystal is YAG (yttrium / aluminum / garnet crystal), YLF, YVO ₄ , YAlO ₃ , sapphire, ruby, or alexandride. In addition, the active species having a laser action are, for example, trivalent ions (Cr ³⁺ , Nd ³⁺ , Yb ³⁺ , Tm ³⁺ , Ho ³⁺ , Er ³⁺ , Ti ³⁺ ).

  The laser used in this embodiment mode only needs to emit laser light having a wavelength that is absorbed by the amorphous semiconductor film. In this embodiment mode, since silicon is used for the amorphous semiconductor film, the wavelength of the laser light used may be 800 nm or less, more preferably about 350 to 550 nm, which is absorbed by silicon.

  A thermal crystallization method using an element that promotes crystallization, such as nickel (Ni), may be used for crystallization of the amorphous semiconductor film.

The crystallized semiconductor film is selectively etched and removed. For etching the semiconductor film, a resist pattern is selectively formed on the semiconductor film and dry etching is performed. Here, the etching gas to be used is not limited to a specific one, but at least the etching selectivity with respect to the base film needs to be sufficient. In other words, a material having a low etching rate for the base film and a high etching rate for the semiconductor film may be used. As an example of a gas used for etching a semiconductor film, a chlorine-based gas such as Cl ₂ , BCl ₃ , or SiCl ₄ , or a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , CHF ₃ , or CF ₄ is used. Can do.

Next, plasma treatment is performed on a side end region of the semiconductor film. First, a first resist 131 is formed at a desired position on the semiconductor film 130 formed over the entire surface (see FIG. 5A). Next, dry etching is performed with the first resist 231 formed. As the etching gas used at this time, a gas having a low etching rate for the base film 201 and the first resist 231 and a high etching rate for the semiconductor film 230 is selected. By using such a gas, the semiconductor film 230 can be etched without removing the base film 201 by etching. (See FIG. 5B). An example of a gas that can be used here is a mixed gas of CF ₄ or SF ₆ and He or H ₂ . CF ₄ and SF ₆ have a high etching rate with respect to silicon forming a semiconductor film, and He and H ₂ do not cause the resist to recede. Here, He and H ₂ serve to adjust the etching rate of silicon.

Here, the first resist 231 is moved backward to form the second resist 233. For the treatment, light ashing using oxygen (O ₂ ) may be performed, or etching using a gas containing oxygen (O ₂ ) may be performed. By performing such treatment, the first resist 231 moves backward to become the second resist 233 (see FIG. 5C). Here, the gas to be used is not limited to oxygen (O ₂ ), and any gas may be used as long as the first resist 231 recedes.

Next, plasma treatment is performed in order to add halogen to the side end region of the semiconductor film 232 with the second resist 233 remaining (see FIG. 6A). In this embodiment mode, fluorine (F) is used as a halogen to be added. For the plasma treatment, a mixed gas of CHF ₃ and He is used. As an example, the gas flow ratio is 7.5: 142.5 (sccm), the pressure in the chamber is 5.5 Pa, and 475 W of RF (13.56 MHz) power is applied to the coil-type electrode. Plasma treatment can be performed by applying 300 W of RF (13.56 MHz) power to the substrate side. More preferably, the gas flow ratio is 56: 144 (sccm), the pressure in the chamber is 7.5 Pa, and 25 W of RF (13.56 MHz) power is applied to the coiled electrode to generate plasma. The plasma treatment is preferably performed by supplying 425 W of RF (13.56 MHz) power to the substrate side. By performing the treatment under such conditions, fluorine (F) can be added to the side end region of the semiconductor film 232. After the plasma treatment, light ashing is performed with O ₂ plasma, and the resist is removed by peeling using a predetermined chemical solution (see FIG. 6B).

Note that since CHF ₃ is used in the above plasma treatment, the base film in a region which does not overlap with the semiconductor film 232 can be slightly etched. Therefore, it is preferable to adjust plasma generation conditions so that etching of the base film 201 does not progress.

Next, the insulating film 203 is formed. The insulating film 203 is formed by plasma treatment similarly to the insulating film 203 in Embodiment 1, and is formed using silicon oxide (SiO _x ) (see FIG. 6C).

Since the side end region 232C of the semiconductor film 232 containing fluorine (F) has a high oxidation rate, the oxidation proceeds preferentially in the side end region 232C of the semiconductor film 232. When a silicon oxide (SiO _x ) film or a silicon oxynitride (SiN _x O _y (x>y> 0)) film is formed as the gate insulating film, compared to the oxidation rate of the semiconductor film in contact with the gate insulating film, Since the oxidation rate of the side end region 232C of the semiconductor film 232 is high, a portion of the gate insulating film in contact with the side end region can be formed thick.

  Note that since the plasma treatment is performed from the surface of the semiconductor film 232, not only the side end region 232C of the semiconductor film 232 but also the surface of the semiconductor film 232 in contact with the insulating film 203 is oxidized. Accordingly, an insulating film is also formed on the surface of the semiconductor film 232 in contact with the insulating film 203.

As described above, the insulating film 203 can be formed using a single layer or stacked layers of a silicon oxide (SiO _x ) film and a silicon oxynitride (SiO _x N _y ) (x>y> 0) film.

Note that as the atmosphere containing oxygen (O ₂ ), for example, oxygen and hydrogen (H ₂ ) in a mixed gas atmosphere of oxygen and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe). And a rare gas mixed gas atmosphere, a mixed gas atmosphere of dinitrogen monoxide (N ₂ O) and a rare gas, or a mixed gas atmosphere of dinitrogen monoxide, hydrogen, and a rare gas. . For example, a mixed gas containing oxygen, hydrogen, and argon (Ar) can be used. In that case, a mixed gas containing 0.1 to 100 sccm of oxygen, 0.1 to 100 sccm of hydrogen, and 100 to 5000 sccm of argon can be used. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

Note that the plasma treatment is performed using plasma with an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of 1.5 eV or less in the atmosphere of the gas. More specifically, plasma having an electron density of 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and an electron temperature of 0.5 eV to 1.5 eV is used. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor film 232) formed on the substrate is low, damage to the object to be processed can be prevented. it can. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or nitride film formed by oxidizing an object to be irradiated using plasma treatment can be formed by CVD or sputtering. Compared with a film formed by a method or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, sufficient oxidation can be performed even if the plasma treatment is performed at a temperature 100 degrees or more lower than the strain point of the glass substrate. As a frequency for forming plasma, a high frequency such as a microwave (2.45 GHz) can be used.

Note that nitriding treatment may be performed by plasma after the insulating film 203 is formed. As an atmosphere containing nitrogen, for example, a mixture of nitrogen, hydrogen, and a rare gas in a mixed gas atmosphere of nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) The reaction can be performed in a gas atmosphere or a mixed gas atmosphere of ammonia (NH ₃ ) and a rare gas.

  As described above, in the gate insulating film of this embodiment, the thickness of the portion in contact with the side end region 232C of the semiconductor film 232 is larger than the position overlapping the surface of the semiconductor film 232. Further, since the side end region 232C of the semiconductor film 232 contains fluorine (F), it becomes a low-k film, ie, a SiOF film or a film close to the SiOF film, and the dielectric constant is higher than the dielectric constant at the position overlapping the semiconductor film surface. Becomes smaller. By forming the gate insulating film in this way, a low dielectric constant insulating film is formed thick at the side end, so that a film having a high breakdown voltage and a low leakage current at the side end of the semiconductor film can be formed. . Further, since the insulating film formed by plasma treatment has a uniform thickness and is dense, an insulating film with high withstand voltage and low leakage current can be formed.

  Alternatively, chlorine (Cl) may be used as the halogen added to the side end region 232C. By using chlorine as an element added to the side end region 232C, oxidation of the side end region 232C is promoted, and the thickness of the portion of the semiconductor film 232 in contact with the side end region 232C is larger than the position overlapping the surface of the semiconductor film 232. A gate insulating film can be formed to be large.

  Note that in the semiconductor device of this embodiment mode, by reducing the taper angle of the side end region provided in contact with the semiconductor film included in the thin film transistor, the area where the semiconductor film end is exposed to halogen can be increased. The halogen can be easily added to the side end region 232C. Furthermore, by reducing the taper angle of the side end region, step coverage (step coverage) of the first conductive film formed on the side end region can be improved. However, the present invention is not limited to this, and the taper angle may be 45 ° or more and 90 ° or less.

  Next, a first conductive film 204 functioning as a gate electrode is selectively formed. The first conductive film 204 can be formed in a manner similar to that of the first conductive film 104 in Embodiment 1.

Next, an impurity region is formed by adding an impurity element of one conductivity type to the semiconductor film 232 using the first conductive film 204 as a mask. The impurity region functions as a source region or a drain region. Here, as the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. For example, phosphorus (P) may be added as an impurity element to the semiconductor film 232 so as to be included at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ , so that an impurity region exhibiting n-type conductivity may be formed. Although not illustrated, a low concentration impurity region (LDD region) to which an impurity is added at a lower concentration than the source region or the drain region may be formed between the channel formation region and the source region or the drain region. The impurity is activated by annealing after adding the impurity.

  Note that an LDD region is a region formed for the purpose of improving reliability in a thin film transistor whose semiconductor film is polycrystalline silicon. In a TFT in which the semiconductor film is polycrystalline silicon, it is important to suppress the off current, and a sufficiently low off current is required particularly when used as an analog switch such as a pixel circuit. However, due to the reverse bias strong electric field at the drain junction, there is a leakage current through the defect even at the off time. Since the electric field in the vicinity of the drain end is relaxed by the LDD region, the off-current can be reduced. Further, the reverse bias electric field at the drain junction can be distributed to the junction between the channel region and the LDD region, and the junction between the LDD region and the drain region, and the electric field at the drain end is relaxed, so that the leakage current is reduced. .

  Next, an insulating film 206 and a second conductive film 207 are formed. The insulating film 206 can be formed using a material and a formation method similar to those of the insulating film 106. The second conductive film 207 can be formed using a material and a formation method similar to those of the second conductive film 107.

  Through the process described above, the thin film transistor of the present invention is formed. Note that the structure of the transistor can take a variety of forms and is not limited to a specific structure. For example, a multi-gate structure in which the number of gates per transistor is two or more may be used. With the multi-gate structure, the off-current is reduced, the breakdown voltage of the transistor is improved, the reliability is improved, and even if the drain-source voltage changes when operating in the saturation region, the drain-source current does not change. It does not change so much and can be made flat.

  In the semiconductor device of the present invention, the insulating film having a low dielectric constant is formed on the side surface of the semiconductor film to be thicker than the insulating film in contact with the semiconductor film surface. Therefore, the gate breakdown voltage in the semiconductor film side end region of the thin film transistor is improved, and the gate leakage defect is reduced. Furthermore, since the electric field strength is reduced in the side end region, the so-called parasitic transistor effect is suppressed.

  The gate insulating film included in the semiconductor device of the present invention is provided by subjecting the semiconductor film to plasma treatment with high-density plasma and oxidizing it. Therefore, interface characteristics between the semiconductor film and the gate insulating film are improved. That is, it is possible to form a gate insulating film not only having a high breakdown voltage in the semiconductor film side end region but also having a high breakdown voltage on the surface in contact with the semiconductor film surface.

  By using the present invention, a thin film transistor with a thin gate insulating film can be manufactured with high yield and high reliability and high reliability.

  Furthermore, since the insulating film in contact with the side surface of the semiconductor film has a lower dielectric constant and is formed thicker than the conventional thin film transistor, it is possible to effectively prevent electrostatic breakdown of the gate insulating film in the end region on the semiconductor film side. it can.

  Furthermore, since halogen is added by plasma treatment using the same resist as that used for etching the semiconductor film, the above-described effect can be produced without complicating the manufacturing process.

  Since the thick insulating film that is in contact with the side end region of the channel formation region of the semiconductor film under the gate electrode is provided, it is possible to reduce the influence on the semiconductor device due to the poor coating of the gate insulating film on the semiconductor film surface.

(Embodiment 3)
In this embodiment, unlike the thin film transistors described in Embodiments 1 and 2, a mode is described in which an insulating film called a sidewall is provided on a side end portion of the first conductive film functioning as a gate electrode. .

  A mode in which a sidewall is formed on the side end portion of the first conductive film 104 of the thin film transistor described in FIG. 1B is shown in FIG. 7A, and the first of the thin film transistor described in FIG. FIG. 7B illustrates a mode in which a sidewall is formed on a side end portion of the conductive film 204.

  The semiconductor device illustrated in FIG. 7A includes a thin film transistor 305A formed over a substrate 100 with a base film 101 interposed therebetween. The thin film transistor 305A includes a first conductive film 104 functioning as a gate electrode formed over the semiconductor film 302 with the insulating film 103 interposed therebetween, a sidewall 300 formed on a side end portion of the first conductive film 104, An insulating film 106 formed over the first conductive film 104 and a second conductive film 107 formed over the insulating film 106 are included. The semiconductor film 302 includes a channel formation region 302A, a high-concentration impurity region 302C that functions as a source region or a drain region, and a low-concentration impurity region 302B whose impurity concentration is lower than that of the high-concentration impurity region 302C. A side end region 302D is provided in contact with the side surface of the high concentration impurity region 302C. The insulating film 103 provided in contact with the side end region 302D is formed thick.

  The semiconductor device illustrated in FIG. 7B includes a thin film transistor 305 </ b> B formed over a substrate 100 with a base film 101 interposed therebetween. The thin film transistor 305B includes a first conductive film 204 that functions as a gate electrode formed over the semiconductor film 303 with the insulating film 203 interposed therebetween, a sidewall 301 formed on a side end portion of the first conductive film 204, An insulating film 206 formed over the first conductive film 204 and a second conductive film 207 formed over the insulating film 206 are included. The semiconductor film 303 includes a channel formation region 303A, a high-concentration impurity region 303C that functions as a source region or a drain region, and a low-concentration impurity region 303B whose impurity concentration is lower than that of the high-concentration impurity region 303C. A side end region 303D is provided in contact with the side surface of the high concentration impurity region 303C. The insulating film 103 provided in contact with the side end region 303D is formed thick.

  The sidewalls 300 and 301 are formed using a film including an inorganic material such as silicon, silicon oxide, or silicon nitride, or an organic material such as an organic resin by using a plasma CVD method, a sputtering method, or the like. The containing film is formed as a single layer or a stacked layer. Then, the insulating film can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surface of the first conductive film. Note that the sidewall 300 or the sidewall 301 can be used as a doping mask when forming the low-concentration impurity region 302B or the low-concentration impurity region 303B, and contributes to the formation of the LDD region.

  Note that an LDD region is a region formed for the purpose of improving reliability in a thin film transistor whose semiconductor film is polycrystalline silicon. In a TFT in which the semiconductor film is polycrystalline silicon, it is important to suppress the off current, and a sufficiently low off current is required particularly when used as an analog switch such as a pixel circuit. However, due to the reverse bias strong electric field at the drain junction, there is a leakage current through the defect even at the off time. Since the electric field in the vicinity of the drain end is relaxed by the LDD region, the off-current can be reduced. Further, the reverse bias electric field at the drain junction can be distributed to the junction between the channel region and the LDD region, and the junction between the LDD region and the drain region, and the electric field at the drain end is relaxed, so that the leakage current is reduced. .

  In the semiconductor device of the present invention, the insulating film having a low dielectric constant in contact with the side surface of the semiconductor film is formed thicker than the insulating film in contact with the surface of the semiconductor film. Therefore, the gate breakdown voltage in the semiconductor film side end region of the thin film transistor is improved, and the gate leakage defect is reduced. Furthermore, since the electric field strength is reduced in the side end region, the so-called parasitic transistor effect is suppressed.

  The gate insulating film included in the semiconductor device of the present invention is provided by subjecting the semiconductor film to plasma treatment with high-density plasma and oxidizing it. Therefore, interface characteristics between the semiconductor film and the gate insulating film are improved. That is, it is possible to form a gate insulating film not only having a high breakdown voltage in the semiconductor film side end region but also having a high breakdown voltage on the surface in contact with the semiconductor film surface.

  By using the present invention, a thin film transistor with a thin gate insulating film can be manufactured with high yield and high reliability and high reliability.

  Further, since the insulating film in contact with the semiconductor film side end region has a low dielectric constant and is thicker than the conventional thin film transistor, it effectively prevents electrostatic breakdown of the gate insulating film in the semiconductor film side end region. be able to.

  Furthermore, since halogen is added by plasma treatment using the same resist as that used for etching the semiconductor film, the above-described effect can be produced without complicating the manufacturing process.

  Since the thick insulating film is in contact with the side end region of the channel formation region of the semiconductor film under the gate electrode, it is possible to reduce the influence of the poor coating of the gate insulating film on the semiconductor film surface on the semiconductor device.

  Furthermore, since the thin film transistor of this embodiment includes an LDD region, an electric field in the vicinity of the drain end is reduced, an off current is reduced, and a leakage current is also reduced. Therefore, the operation of the transistor can be performed at high speed, and power consumption can be suppressed low. Therefore, as described in this embodiment mode, the effect of the present invention can be further enhanced by forming the LDD region in the thin film transistor of the present invention.

  Further, since the thin film transistor of this embodiment includes a sidewall formed of an insulating film on the gate electrode, the insulating film formed over the gate electrode covers the insulating film well.

(Embodiment 4)
As the semiconductor device described in any of Embodiments 1 to 4, a semiconductor device capable of wireless communication can be given. In this embodiment, a semiconductor device capable of wireless communication manufactured by applying any of Embodiments 1 to 4 will be described.

  One structural example of the semiconductor device 400 of this embodiment is shown in FIG. The semiconductor device 400 includes an antenna circuit 402, a demodulation circuit 403, a clock generation circuit 404, a power supply circuit 405, a control circuit 406, a memory circuit 407, and a modulation circuit 408.

  The antenna circuit 402 converts the carrier wave supplied from the reader / writer 401 into an AC electrical signal. The antenna circuit preferably has a rectifier circuit.

  The shape of the antenna that can be used in the present invention is not particularly limited. Therefore, as a signal transmission method applied to the antenna circuit 402 in the semiconductor device 400, an electromagnetic coupling method, an electromagnetic induction method, a radio wave method, an optical method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an antenna having an optimal length and shape may be provided according to the transmission method. In the present invention, a radio wave system can be used as a signal transmission system, and a microwave system can also be used.

  When an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a transmission method, a conductive film that functions as an antenna is formed into a ring shape (for example, a loop antenna) in order to use electromagnetic induction due to a change in electric field density. ) Or a spiral shape (for example, a spiral antenna).

  When a microwave method (for example, UHF band (860 to 960 MHz band) or 2.45 GHz band) is applied as a transmission method, an antenna is considered in consideration of the wavelength of the radio wave used for signal transmission. The length and shape of the conductive film functioning as the above may be set as appropriate. The conductive film functioning as an antenna can be formed into, for example, a linear shape (for example, a dipole antenna), a flat shape (for example, a patch antenna), or the like. The shape of the conductive film functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

  Here, an example of the shape of the antenna provided in the antenna circuit 402 is shown in FIG. For example, as shown in FIG. 9A, a structure in which one antenna 421 is arranged around a chip 420 provided with a signal processing circuit may be employed. Further, as shown in FIG. 9B, a structure may be adopted in which a thin antenna 423 is arranged around the chip 422 around the chip 422 provided with the signal processing circuit. 9C, an antenna having a shape like the antenna 425 for receiving high-frequency electromagnetic waves may be provided for a chip 424 provided with a signal processing circuit. Further, as shown in FIG. 9D, an antenna having a shape such as an antenna 427 of 180 degrees omnidirectional (reception is possible from any direction) is provided for a chip 426 provided with a signal processing circuit. Also good. As shown in FIG. 12E, an antenna having a shape like an antenna 429 elongated in a rod shape may be provided for a chip 428 provided with a signal processing circuit. The antenna circuit 402 can use a combination of antennas of these shapes.

  Further, in FIG. 9, there is no particular limitation on a method for connecting the chip 420 or the like provided with the signal processing circuit and the antenna 421 or the like. Taking FIG. 9A as an example, the antenna 421 and a chip 420 provided with a signal processing circuit are connected by wire bonding connection or bump connection, or a part of the chip is attached to the antenna 421 as an electrode. You may take In this method, the chip 420 can be attached to the antenna 421 using an anisotropic conductive film (hereinafter referred to as ACF). The length required for the antenna varies depending on the frequency used for reception. For example, when the frequency is 2.45 GHz, the length of the antenna is about 60 mm (1/2 wavelength) if a half-wave dipole antenna is provided, and the length of the antenna is about 30 mm (1/4 wavelength) if a monopole antenna is provided. do it. Particularly preferably, when the frequency is 900 MHz, transmission / reception is performed by a radio wave method using an antenna of 100 mm to 150 mm.

  The demodulation circuit 403 demodulates the AC electrical signal converted by the antenna circuit 402 and transmits the demodulated signal to the control circuit 406. Note that the demodulation circuit 403 is not necessarily provided if it is not particularly necessary.

  The clock generation circuit 404 supplies a clock signal necessary for the operation of the control circuit 406 and the memory circuit 407. As an example of the circuit configuration, an oscillation circuit or a frequency divider circuit may be used.

  The power supply circuit 405 generates a power supply voltage using the AC electrical signal converted by the antenna circuit 402, and supplies the power supply voltage necessary for the operation to each circuit.

  Based on the signal demodulated by the demodulation circuit 403, the control circuit 406 performs instruction analysis, control of the storage circuit 407, and output to the modulation circuit 408 for data to be transmitted to the outside. The control circuit 406 may include an encoding circuit or the like. The encoding circuit converts all or a part of the data extracted from the data in the storage circuit 407 and transmitted to the reader / writer 401 that performs wireless communication with the semiconductor device into an encoded signal.

  The memory circuit 407 may be any circuit that can store information that the semiconductor device 400 should have. The memory circuit 407 includes a circuit including a memory element and a control circuit that performs data writing and data reading in accordance with the control circuit 406. The storage circuit 407 stores at least individual identification information (ID) of the semiconductor device 400 itself. The individual identification information (ID) is used to distinguish from other semiconductor devices (other semiconductor devices owned by a user and semiconductor devices owned by a person other than the user). The memory circuit 407 includes an organic memory, a DRAM (Dynamic Random Access Memory), a SRAM (Static Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), and a mask ROM (Read Only Memory). One or more types selected from an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), and a flash memory. If the stored content is information unique to the semiconductor device 400 (individual identification information (ID) or the like), a nonvolatile memory that can hold the memory even when power is not supplied is used. If the memory is retained, a volatile memory may be used. In particular, when the semiconductor device 400 is a passive type that does not have a battery, it is preferable to use a nonvolatile memory.

  An organic memory has a structure in which a layer containing an organic compound is sandwiched between a pair of conductive layers, and has a simple structure, and thus has at least two advantages. One is that the manufacturing process can be simplified and the cost can be reduced. The other is that the area of the laminated body can be easily reduced, and a large capacity can be easily realized. Therefore, an organic memory is preferably used for the memory circuit 407.

  The modulation circuit 408 applies load modulation to the antenna circuit 402 based on the data from the control circuit 406.

  The semiconductor device of the present invention has a high gate breakdown voltage and reduced gate leakage defects. Therefore, a semiconductor device with low power consumption can be manufactured.

  Further, even when elements in the semiconductor device are miniaturized and the thickness of the gate insulating film is accordingly reduced, a semiconductor device with favorable electrical characteristics and high reliability can be manufactured with high yield.

  Furthermore, in the semiconductor device of the present invention, since the insulating film in contact with the side surface of the semiconductor film has a low dielectric constant and is thicker than the conventional thin film transistor, electrostatic breakdown of the gate insulating film in the semiconductor film side end region is prevented. It can prevent effectively and can improve reliability.

(Embodiment 5)
The present invention can also be applied to a memory element. As an example, a nonvolatile memory manufactured by applying the present invention will be described with reference to FIGS.

  FIG. 10 is a cross-sectional view of a memory element included in a NOR flash memory as an example of a nonvolatile memory. The NOR type flash memory is mounted on, for example, a mother board (also referred to as a main board), and is used for recording a BIOS (Basic Input Output System). The mother boat is one of the components of the computer and is used to mount various modules such as a CPU (Central Processing Unit).

  In manufacturing the memory element, the manufacturing method is the same as that described in Embodiment Modes 1 to 3. Hereinafter, the configuration of the memory element will be described.

  FIG. 10 illustrates a structure including two memory elements 510 over a substrate 500. The memory element 510 includes a semiconductor film 502 over a base film 501 provided over the substrate 500. The semiconductor film 502 includes a channel formation region 502A and an impurity region 502B that functions as a source region or a drain region. The semiconductor film 502 is provided with a side end region 502C, and the insulating film 503 in contact with the side end region 502C is formed thick. A first conductive film 504 functioning as a floating gate is provided over a channel formation region 502A of the semiconductor film 502 with a gate insulating film 503 interposed therebetween. A second conductive film 506 functioning as a control gate is provided over the first conductive film 504 with an insulating film 505 interposed therebetween. An insulating film 507 is provided over the second conductive film 506. The insulating film 507 has an opening through which the impurity region 502B of the semiconductor film 502 is exposed. The third conductive film 508 provided over the insulating film 507 has an opening which is connected to the impurity region 502B of the semiconductor film 502 through the opening. It is connected.

  As the substrate 500, a substrate similar to the substrate 100 in Embodiment 1 can be used. The base film 501 can be formed using a material and a method similar to those of the base film 101 in Embodiment 1. The semiconductor film 502 can be formed using a material and a method similar to those of the semiconductor film 102 in Embodiment 1. The insulating film 503 can be formed using a material and a method similar to those of the insulating film 103 in Embodiment 1. The first conductive film 504, the second conductive film 506, and the third conductive film 508 are formed using the same materials and methods as the first conductive film 104 and the second conductive film 107 in Embodiment 1. Can be formed. The insulating film 505 and the insulating film 507 can be formed using a material and a method similar to those of the insulating film 103 or the insulating film 106 in Embodiment 1.

  Although not shown in FIG. 10, the semiconductor film 502 may have a structure having a low concentration impurity region (LDD region). Further, the control gate and the floating gate may have sidewalls.

  Note that an LDD region is a region formed for the purpose of improving reliability in a thin film transistor whose semiconductor film is polycrystalline silicon. In a TFT in which the semiconductor film is polycrystalline silicon, it is important to suppress the off current, and a sufficiently low off current is required particularly when used as an analog switch such as a pixel circuit. However, due to the reverse bias strong electric field at the drain junction, there is a leakage current through the defect even at the off time. Since the electric field in the vicinity of the drain end is relaxed by the LDD region, the off-current can be reduced. Further, the reverse bias electric field at the drain junction can be distributed to the junction between the channel region and the LDD region, and the junction between the LDD region and the drain region, and the electric field at the drain end is relaxed, so that the leakage current is reduced. .

  Note that elements provided over the substrate 500 may be adjusted as appropriate depending on the application of the semiconductor device. For example, an erase voltage control circuit may be mounted. A resistor element, a capacitor element, or the like may be provided as necessary.

  An example of a circuit diagram of the flash memory described above is shown in FIG. Writing and reading operations are performed using the word lines W1 to W7 and the bit lines B1 to B4. The word line and the bit line are connected to a circuit for controlling each operation. Or you may connect to the wiring extended | stretched to the circuit which controls each operation | movement by a next process. The word line is connected to the gate electrode in the memory element, and the bit line is connected to the source electrode or the drain electrode in the memory element. A region 520 surrounded by a dotted line corresponds to one memory element 510.

  Although not shown, it is possible to mount a device having a more complicated circuit configuration in a small size by adopting a multilayer wiring structure.

  Although only the NOR flash memory has been described here, the present invention can also be applied to a NAND flash memory.

  A memory element to which the present invention is applied has a high gate breakdown voltage and reduced gate leakage defects. Therefore, a semiconductor device with low power consumption can be manufactured.

  Further, even when the element in the memory element is miniaturized and the thickness of the gate insulating film is reduced accordingly, a semiconductor device with favorable electrical characteristics and high reliability can be manufactured with high yield.

  Furthermore, in the memory element of the present invention, since the insulating film in contact with the side surface of the semiconductor film has a low dielectric constant and is formed thick, it effectively prevents electrostatic breakdown of the gate insulating film in the end region on the semiconductor film side. And reliability can be improved.

Note that this embodiment can be freely combined with any of the other embodiments in this specification.
(Embodiment 6)
In this embodiment, a structure of a CPU will be described with reference to a block diagram.

12 includes an arithmetic circuit 701 (also referred to as an ALU), an arithmetic circuit control unit 702 (ALU Controller), an instruction analysis unit 703 (Instruction Decoder), and an interrupt control unit. 704 (Interrupt Controller), timing controller 705 (Timing Controller), register 706 (Register), register controller 707 (Register Controller), bus interface 708 (Bus I / F), rewritable ROM 709, and ROM interface 720 ( ROM I / F). The ROM 709 and the ROM interface 720 may be provided on separate chips.

  The above circuit can be formed using a thin film transistor over a glass substrate formed by the method described in Embodiment Modes 1 to 3.

  Note that the CPU illustrated in FIG. 12 is merely an example in which the configuration is simplified, and an actual CPU has various configurations depending on the application.

  An instruction input to the CPU via the bus interface 708 is input to the instruction analysis unit 703 and decoded, and then is input to the control unit 702 for the arithmetic circuit, the interrupt control unit 704, the register control unit 707, and the timing control unit 705. Entered.

  An arithmetic circuit control unit 702, an interrupt control unit 704, a register control unit 707, and a timing control unit 705 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control unit 702 generates a signal for controlling the operation of the arithmetic circuit 701. The interrupt control unit 704 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register control unit 707 generates an address of the register 706, and reads and writes the register 706 according to the state of the CPU.

  The timing control unit 705 generates a signal for controlling the operation timing of the arithmetic circuit 701, the arithmetic circuit control unit 702, the instruction analysis unit 703, the interrupt control unit 704, and the register control unit 707. For example, the timing control unit 705 includes an internal clock generation unit that generates an internal clock signal CLK2 (722) based on the reference clock signal CLK1 (721), and supplies the clock signal CLK2 to the various circuits.

  The thin film transistor of the present invention has a high gate breakdown voltage and reduced gate leakage defects. Therefore, a CPU with low power consumption can be manufactured. This is a particularly great advantage for a CPU that consumes more power than other semiconductor devices.

  Further, even when elements in the semiconductor device are miniaturized and the thickness of the gate insulating film is accordingly reduced, a semiconductor device with favorable electrical characteristics and high reliability can be manufactured with high yield.

  Furthermore, in the semiconductor device of the present invention, since the insulating film in contact with the side surface of the semiconductor film has a low dielectric constant and is thicker than the conventional thin film transistor, electrostatic breakdown of the gate insulating film in the semiconductor film side end region is prevented. It can prevent effectively and can improve reliability.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 7)
A semiconductor device 800 capable of wireless communication to which the present invention is applied can be used for various articles and systems by utilizing a function of transmitting and receiving electromagnetic waves. For example, the article is a key (see FIG. 13A), banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 13B). Books, containers (petrials, etc., see FIG. 13C), packaging containers (wrapping paper, bottles, etc., see FIGS. 13E and 13F), recording media (discs and videos) Tapes, etc.), vehicles (bicycles, etc.), jewelry (eg, bags, glasses, etc., see FIG. 13D), foods, clothing, household goods, electronic devices (liquid crystal display devices, EL display devices, televisions) Device, portable terminal, etc.). The semiconductor device of the present invention is fixed or mounted by being attached or embedded on the surface of an article having various shapes as described above. The system is an article management system, an authentication function system, a distribution system, or the like, and the reliability of the system can be improved by using the semiconductor device of the present invention.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. FIG. 10 illustrates a conventional semiconductor device. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate an antenna mounted on a semiconductor device capable of wireless communication according to the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 4 shows an example of mounting the semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Substrate 101 Base film 102 Semiconductor film 103 Insulating film 104 First conductive film 105 Thin film transistor 106 Insulating film 107 Second conductive film 130 Semiconductor film 131 First resist 132 Semiconductor film 133 Second resist 140 Semiconductor film 141 Semiconductor film 200 Substrate 201 Base film 202 Semiconductor film 203 Insulating film 204 First conductive film 205 Thin film transistor 206 Insulating film 207 Second conductive film 230 Semiconductor film 231 First resist 232 Semiconductor film 233 Second resist 300 Side wall 301 Side wall 302 Semiconductor film 303 Semiconductor film 400 Semiconductor device 401 Reader / writer 402 Antenna circuit 403 Demodulation circuit 404 Clock generation circuit 405 Power supply circuit 406 Control circuit 407 Memory circuit 408 Modulation circuit 420 Chip 421 422 Chip 423 Antenna 424 Chip 425 Antenna 426 Chip 427 Antenna 428 Chip 429 Antenna 500 Substrate 501 Base film 502 Semiconductor film 503 Insulating film 504 First conductive film 505 Insulating film 506 Second conductive film 507 Insulating film 508 Third conductive Film 510 Storage element 520 Region 700 Substrate 701 Arithmetic circuit 702 Control unit 703 Instruction analysis unit 704 Control unit 705 Timing control unit 706 Register 707 Register control unit 708 Bus interface 709 ROM
720 ROM interface 800 Semiconductor device 102A Channel formation region 102B Impurity region 102C Side end region 1100 Substrate 1101 Base film 1102 Semiconductor film 1103 Insulating film 1104 First conductive film 1105 Thin film transistor 1106 Insulating film 1107 Second conductive film 1108 Region 132C Side end Region 140C side end region 141C side end region 232C side end region 202A channel formation region 202B impurity region 202C side end region 302A channel formation region 302B low concentration impurity region 302C high concentration impurity region 302D side end region 303A channel formation region 303B low concentration impurity Region 303C High-concentration impurity region 303D Side end region 305A Thin film transistor 305B Thin film transistor 502A Channel formation region 502B Impurity region 502C Side end region 1102A Channel formation region 1102B Impurity region

Claims (12)

An island-shaped semiconductor film having a tapered side end region;
A gate insulating film having an opening provided in contact with the surface and side end regions of the semiconductor film;
A gate electrode layer provided on the semiconductor film via the gate insulating film;
An insulating film having an opening provided on the gate electrode layer;
A source electrode and a drain electrode layer provided in contact with the insulating film having the opening and connected to the semiconductor film through the opening;
A thin film transistor, wherein a portion of the gate insulating film in contact with a side end region of the semiconductor film contains halogen and is thicker than a portion in contact with the surface of the semiconductor film. An island-shaped semiconductor film having a tapered side end region provided on the substrate;
A gate insulating film having an opening provided in contact with the surface and side end regions of the semiconductor film;
A gate electrode layer provided on the semiconductor film via the gate insulating film;
An insulating film having an opening provided on the gate electrode layer;
A source electrode and a drain electrode layer provided in contact with the insulating film having the opening and connected to the semiconductor film through the opening;
A thin film transistor, wherein a portion of the gate insulating film in contact with a side end region of the semiconductor film contains halogen and is thicker than a portion in contact with the surface of the semiconductor film. In claim 2,
The thin film transistor, wherein the substrate is a glass substrate or a semiconductor substrate. In any one of Claim 1 thru | or 3,
The thin film transistor, wherein the halogen is fluorine. In any one of Claims 1 thru | or 4,
The thin film transistor, wherein the semiconductor film is a crystalline silicon film. In any one of Claims 1 thru | or 5,
The thin film transistor, wherein the gate insulating film is a silicon oxide film.   A semiconductor device comprising the thin film transistor according to claim 1. Forming a first resist on the semiconductor film;
Forming a second resist from the first resist while forming an island-shaped semiconductor film by etching the semiconductor film using the first resist;
Halogen is added to the side edge region of the island-shaped semiconductor film using the second resist,
Removing the second resist;
A gate insulating film is formed by oxidizing the surface and side edge regions of the island-shaped semiconductor film,
Forming a gate electrode layer on the gate insulating film;
Forming an insulating film covering the gate electrode layer;
Forming an opening in the gate insulating film and the insulating film;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode layer are formed over the opening and the insulating film. Forming a first resist on the semiconductor film;
An island-shaped semiconductor film is formed by etching the semiconductor film using the first resist,
Forming a second resist;
Halogen is added to the side edge region of the island-shaped semiconductor film using the second resist,
Removing the second resist;
A gate insulating film is formed by oxidizing the surface and side edge regions of the island-shaped semiconductor film,
Forming a gate electrode layer on the gate insulating film;
Forming an insulating film covering the gate electrode layer;
Forming an opening in the gate insulating film and the insulating film;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode layer are formed over the opening and the insulating film. In claim 9,
The method for manufacturing a thin film transistor, wherein the second resist is formed by processing the first resist using oxygen gas. In any one of Claims 8 thru | or 10,
A method for manufacturing a thin film transistor, wherein CHF ₃ plasma treatment is used for the addition of the halogen. In any one of Claims 8 thru | or 11,
A method for manufacturing a thin film transistor, wherein the insulating film is formed by high-density plasma.

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