JP2008165279A - Vector arithmetic unit and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vector arithmetic unit for calculating the maximum value or minimum value for every element only by one vector instruction, and for making it unnecessary to hold elements in a vector data register for a long time. <P>SOLUTION: A vector data holding circuit 30 is provided for holding elements A and B of a plurality of vector data only in a time necessary for comparing those elements, and the maximum element or minimum element is selected from the vector data holding circuit 30, and derived as an arithmetic result C based on the comparison result of a comparator circuit 20 by the subtraction processing of the elements A and B. Thus, it is possible to calculate the maximum value or minimum value for every element by one instruction, and it is unnecessary to hold any element in vector data registers 41 to 43 once this arithmetic operation is performed, and it is possible to write the next elements. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a vector operation apparatus and method, and more particularly to a vector operation apparatus and method for continuously calculating a plurality of vector data as input.

  In a conventional vector operation device, in order to obtain the maximum value or the minimum value for each element, a comparison operation process of element values, a mask generation process from the positive / negative of this comparison result value, and an element selection process according to this mask value Is realized by a plurality of instructions (see Patent Documents 1 to 3, etc.).

  Here, referring to Patent Document 4, a technique for obtaining the maximum value and the minimum value of data is disclosed, and a data comparison process and a data selection process based on the comparison result are executed with one instruction. The configuration is shown as follows.

JP 60-251470 A Japanese Patent Laid-Open No. 61-160176 Japanese Patent Laid-Open No. 95-324699 JP 2004-062401 A

  In the vector arithmetic unit, in order to calculate the maximum value and the minimum value of a plurality of vector data, as described above, it is necessary to execute a plurality of instructions for each element. There is a disadvantage that the functions of the vector data register are complicated, and that the elements in the vector data register need to be held for a long time between the plurality of processes.

  The technique described in Patent Document 4 is merely for obtaining the maximum value or the minimum value of data, and does not relate to a vector operation device that continuously calculates these vector data by using a plurality of vector data as inputs. .

  An object of the present invention is to provide a vector operation apparatus and method capable of calculating the maximum value and the minimum value for each element with only one vector instruction and not requiring the retention of elements in the vector data register for a long time. It is to be.

  A vector arithmetic device according to the present invention is a vector arithmetic device for continuously calculating vector data to obtain a maximum value (or minimum value), a holding means for holding each of the vector data, Comparing means for performing a comparison operation, and selecting means for selecting one of the vector data held in the holding means according to the comparison result of the comparing means and deriving it as a maximum value (or minimum value). It is characterized by.

  A vector calculation method according to the present invention is a vector calculation method for continuously calculating vector data to obtain a maximum value (or minimum value), a holding step for holding each of the vector data, A comparison step for performing a comparison operation, and a selection step for selecting one of the vector data held in the holding step according to the comparison result and deriving it as a maximum value (or a minimum value). .

  According to the present invention, it becomes possible to calculate the maximum value and the minimum value for each element with only one vector instruction, and as a result, there is an effect that it is not necessary to hold elements in the vector data register for a long time. is there.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram for explaining an embodiment of the present invention. Referring to FIG. 1, in the embodiment of the present invention, a comparison circuit 20 that compares vector data A and B element by element, a vector data holding circuit 30 that holds vector data A and B, and a comparison circuit 20 are compared. A selection circuit 40 that selects one of the vector data A and B of the vector data holding circuit 30 from information indicating the result is included.

  The comparison circuit 20 performs subtraction of (A−B). In the case of maximum value calculation, when the subtraction result is 0 or more, information (“0”) indicating A ≧ B is generated, and the subtraction result is negative. When it is a value, information (“1”) indicating A <B is generated. The selection circuit 40 selects the vector data A from the vector data holding circuit 30 when the comparison information is information indicating A ≧ B, and selects the vector data B from the vector data holding circuit 30 when the comparison information is information indicating A <B. select.

  In the case of the minimum value calculation, the selection circuit 40 selects vector data B from the vector data holding circuit 30 when the comparison information is information indicating “A ≧ B” (“0”), and information indicating A <B ( When “1”), the vector data A is selected from the vector data holding circuit 30. The output of the selection circuit 40 is the calculation result C.

  Thus, according to the present invention, in the vector operation circuit that continuously calculates the vector data, the vector data holding circuit 30 that holds each of the plurality of input vector data for the time required for the comparison, and the comparison operation circuit 20 Since the selection circuit 40 is provided for selecting the largest element (small element) of the vector data held in the vector data holding circuit 30 in accordance with the comparison result, the maximum value (minimum value) is set for each element. It can be calculated with one vector instruction.

  FIG. 2 is a circuit diagram of an embodiment showing a specific configuration of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. Referring to FIG. 2, the vector arithmetic unit of this embodiment includes vector data registers 41, 42, and 43 that hold a plurality of vector data, and vector data A and B that are successively read from the vector data registers 41 and 42, respectively. Each of the registers 10 and 11 and a vector comparison circuit 20 having the vector data A and B held in the registers 10 and 11 as two inputs. The registers 10 and 11 hold the vector data A and B as inputs and supply them to the comparison circuit 20 continuously by the number of elements.

  The vector comparison circuit 20 receives the 2-input operands of the register 10 that holds the vector data A and the register 11 that holds the vector data B, performs subtraction of (A−B), and performs comparison information (“0” or “0”). "1") is generated and output to the selection circuit 40. The register 31 holds vector data A, and the register 32 holds vector data B, which are output to the selection circuit 40, respectively.

  When the maximum value is calculated from the subtraction result of (A−B) by the vector comparison circuit 20, that is, the comparison information, the selection circuit 40 is a vector when the comparison information is 0 or more (when “0” indicating A ≧ B). Data A is selected, and B is selected when the value is negative (when “1” indicating A <B). In the case of the minimum value calculation, the selection circuit 40 displays the vector data B when the comparison information by the vector comparison circuit 20 is 0 or more (when “0” indicating A ≧ B), and when the comparison information is negative (A < (When B is “1”) A is selected and output as a calculation result C. The calculation result C is stored in one of the vector data registers 43, 41, and 42.

  In FIG. 2, the operation of the instruction for performing the maximum value calculation will be described. The vector data A and B are supplied to the comparison circuit 20 with the number of elements continuously held in the registers 10 and 11, respectively. At the same time, the vector data A is stored in the register 31 and the vector data B is stored in the register 32 of the vector data holding circuit 30 and then supplied to the selection circuit 40.

  In the vector comparison circuit 20, the supplied vector data A and vector data B are subtracted and compared. When the vector data A is greater than or equal to B, “0” is output, and the vector data When A is smaller than B, “1” is generated and supplied to the selection circuit 40 as comparison information.

  In the selection circuit 40, the vector data A and B held in the vector data holding circuit 30 corresponding to the comparison target are selected by the selection circuit 40 as follows. That is, in the case of the maximum value calculation, the vector data A of the register 31 is selected when the comparison information is “0”, and the vector data B of the register 32 is selected when the comparison information is “1”.

  In the case of the minimum value calculation, the vector data B of the register 32 is selected when the comparison information is “0”, and the vector data A of the register 31 is selected when the comparison information is “1”. Thereby, the calculation result as the maximum value or the minimum value is obtained. The above operation is performed continuously for the number of elements, and the maximum value (minimum value) can be calculated for each element.

  As described above, by generating and supplying a vector instruction that calculates the maximum (minimum) operation for each element, the maximum (minimum) operation can be performed for each element with one vector instruction. is there. Further, as soon as this operation is performed, it is not necessary to hold the element in the vector data register, so that the next element can be written to the vector data register, and the processing speed can be greatly improved.

  In the above embodiment, the vector comparison circuit 20 generates “0” when the comparison information as a subtraction result of (A−B) is 0 or more, and generates “1” when the comparison information is a negative value. On the contrary, it is clear that “1” may be generated when the comparison information is 0 or more, and “0” may be generated when the comparison information is negative.

  The present invention can be applied to a vector calculation device in a supercomputer vector computer, but it is needless to say that the present invention can be widely applied to general vector calculations.

It is a block diagram of an embodiment of the invention. It is a concrete block diagram which shows the Example of this invention.

Explanation of symbols

10, 11, 31, 32 registers
20 Comparison circuit
30 Vector data holding circuit
40 selection circuit
41-43 vector data register

Claims (4)

A vector arithmetic device for continuously calculating vector data to obtain a maximum value (or minimum value),
Holding means for holding each of the vector data;
A comparison means for performing a comparison operation of the vector data;
And a selection means for selecting one of the vector data held in the holding means in accordance with the comparison result of the comparison means and deriving it as a maximum value (or minimum value).   The said holding | maintenance means, the said comparison means, and the said selection means perform a process for every element of the said vector data by one command, and derive | lead-out a maximum value (or minimum value), Vector arithmetic unit. A vector calculation method for continuously calculating vector data to obtain a maximum value (or minimum value),
Holding step for holding each of the vector data;
A comparison step for performing a comparison operation of the vector data;
A selection step of selecting one of the vector data held in the holding step according to the comparison result and deriving it as a maximum value (or minimum value).   4. The vector operation method according to claim 3, wherein the holding step, the comparing step, and the selecting step are executed for each element of the vector data with one instruction.

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