JP2008160905A - Switching regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching regulator capable of stably and highly accurately generating a desired output voltage from an input voltage. <P>SOLUTION: This switching regulator has: a comparator 12 for generating a comparing signal Sa between a feedback voltage Vfb and a reference voltage Vref; an oscillator 14 for generating a clock signal Sb; a latch circuit 15 for generating a PWM signal Sc (gate signal Sd) on the basis of the comparing signal Sa and the clock signal Sb; an output transistor 11 to be controlled in switching on the basis of the PWM signal Sc (gate signal Sd) and allowing a switch voltage Vsw to be extracted from its one end. The switching regulator smoothes the switch voltage Vsw to generate a desired output voltage Vo from an input voltage Vi. The switching regulator has a slope adding circuit 17 for adding a negative slope to the reference voltage Vref at a timing of turning on the output transistor 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a switching regulator that generates a desired output voltage from an input voltage.

  FIG. 4 is a circuit diagram showing a conventional example of a switching regulator.

  The conventional switching regulator shown in this figure compares a predetermined reference voltage Vref and a feedback voltage Vfb corresponding to the output voltage Vo, and based on the comparison signal Sa and a predetermined clock signal Sb, a pulse width of a desired duty is obtained. The modulation signal Sc (hereinafter referred to as a PWM [Pulse Width Modulation] signal Sc), that is, the gate signal Sd of the output transistor 101 is generated.

  In the conventional switching regulator shown in this figure, the output transistor 101 is turned on at the rising edge of the clock signal Sb and turned off at the falling edge of the comparison signal Sa.

  Therefore, a rectangular wave switch voltage Vsw corresponding to the on / off state is drawn from the source of the output transistor 101 to which the input voltage Vi is applied to the drain. By smoothing this, the desired output is obtained. A voltage Vo is generated.

  Note that Patent Documents 1 and 2 can be cited as examples of the related art related to the above.

  Patent Document 1 discloses and proposes a current mode control type switching regulator that performs an appropriate amount of slope compensation using a calculation result of an input voltage and an output voltage in order to prevent subharmonic oscillation.

Patent Document 2 discloses and proposes a current mode control type switching regulator that performs an appropriate amount of slope compensation using a voltage difference between an input voltage and an output voltage in order to prevent subharmonic oscillation. .
JP 2006-33958 A JP 2006-246626 A

  Certainly, with the conventional switching regulator shown in FIG. 4, it is possible to generate the desired output voltage Vo from the input voltage Vi with a very simple configuration.

  However, in the conventional switching regulator, the output operation becomes unstable or a desired oscillation frequency cannot be obtained due to inevitable delays occurring in the operations of the comparator 102, the latch circuit 105, and the pre-driver 106. There was a fear. In particular, when an attempt is made to increase the switching frequency, the above-described problems are likely to occur because the influence of the delay becomes obvious.

  In addition, as a means for solving the above-mentioned problems, the speed-up capacitor C2 and the like have been conventionally externally attached. However, with such measures, an unnecessary increase in the number of external elements and the associated cost increase are provided. Was invited.

  Further, in the switching regulator having the above-described conventional configuration, when the voltage difference between the input voltage Vi and the output voltage Vo is small (for example, output voltage Vo / input voltage Vi ≧ 1/2) as in the current mode control type switching regulator. When the on-duty of the output transistor 101 exceeds 50%, there is a problem that subharmonic oscillation is likely to occur, the ripple becomes large, and the output accuracy decreases.

  In view of the above problems, an object of the present invention is to provide a switching regulator capable of generating a desired output voltage from an input voltage stably and with high accuracy.

  In order to achieve the above object, a switching regulator according to the present invention includes a comparator that generates a comparison signal between a feedback voltage corresponding to an output voltage and a predetermined reference voltage, an oscillator that generates a clock signal of a predetermined frequency, A latch circuit that generates a pulse width modulation signal having a desired duty based on the comparison signal and the clock signal, an output transistor that is switching-controlled based on the pulse width modulation signal, and that draws a rectangular wave switch voltage from one end thereof, A switching regulator that generates a desired output voltage from an input voltage by smoothing the switch voltage, and adds a negative slope to the reference voltage when the output transistor is turned on It is set as the structure (1st structure) which has a slope addition circuit to perform .

  In the switching regulator having the first configuration, the slope adding circuit includes a switch inserted between the reference voltage application terminal and the reference voltage input terminal of the comparator, and a reference voltage input terminal of the comparator. And a discharge means for discharging the charge accumulated in the capacitor, and the switch is complementary to the output transistor based on the pulse width modulation signal. It is preferable to adopt a configuration (second configuration) in which switching control is performed.

  In the switching regulator having the first or second configuration, the comparator sets the comparison signal to a high level when the feedback voltage is lower than the reference voltage, and sets the comparison signal to a low level when the feedback voltage is high. The latch circuit is configured to set the pulse width modulation signal to a high level at the rising edge of the clock signal and to set the pulse width modulation signal to a low level at the falling edge of the comparison signal (third configuration). ).

  Further, in the switching regulator having any one of the first to third configurations, the output transistor has one end connected to the input voltage application end and the switch voltage is drawn from the other end (first 4 configuration).

  The switching regulator having any one of the first to fourth configurations includes a pre-driver that increases the driving capability of the pulse width modulation signal and generates the control signal of the output transistor (fifth) Configuration).

  The switching regulator having the fifth configuration includes a semiconductor device in which the comparator, the oscillator, the latch circuit, the pre-driver, the output transistor, and the phase compensation circuit are integrated; and A smoothing circuit which is externally attached and smoothes the switch voltage to generate a desired output voltage; and a voltage dividing circuit which is externally attached to the semiconductor device and divides the output voltage to generate the feedback voltage. (6th configuration).

  The switching regulator according to the present invention can generate a desired output voltage from an input voltage stably and with high accuracy.

  FIG. 1 is a circuit diagram showing an embodiment of a switching regulator according to the present invention.

  As shown in the figure, the switching regulator of the present embodiment includes a switching regulator IC 10, a diode (Schottky diode) D 1, an inductor L 1, a capacitor C 1, and resistors R 1 and R 2 externally attached thereto. Become.

  The switching regulator IC 10 includes an N-channel field effect transistor (output transistor) 11, a comparator 12, a DC voltage source 13, an oscillator 14, a latch circuit (RS flip-flop) 15, a pre-driver 16, and a slope adding circuit. 17 is an integrated semiconductor device.

  The drain of the output transistor 11 is connected to the application terminal for the input voltage Vi. The source of the output transistor 11 is connected to the cathode of the diode D1 and one end of the inductor L1. The anode of the diode D1 is connected to the ground terminal. The other end of the inductor L1 is connected to a load (not shown) as an extraction terminal for the output voltage Vo, and is also connected to the ground terminal through a path via the capacitor C1 and a path via the resistors R1 and R2. Yes.

  The non-inverting input terminal (+) of the comparator 12 is connected to the positive terminal of the DC voltage source 13 via the slope load circuit 17. The negative terminal of the DC voltage source 13 is grounded. The inverting input terminal (−) of the comparator 12 is connected to an application terminal (a connection node between the resistor R1 and the resistor R2) of the feedback voltage Vfb corresponding to the output voltage Vo.

  The reset terminal (R) of the latch circuit 15 is connected to the output terminal of the comparator 12. The set end (S) of the latch circuit 15 is connected to the output end of the oscillator 14. The output terminal (Q) of the latch circuit 15 is connected to the gate of the output transistor 11 via the pre-driver 16.

  The slope adding circuit 17 includes an N-channel field effect transistor (switch) 17a, a capacitor 17b, a constant current source (discharge means) 17c, and an inverter 17d. The drain of the transistor 17 a is connected to the positive terminal of the DC voltage source 13. The source of the transistor 17a is connected to the non-inverting input terminal (+) of the comparator 12, and is also connected to the ground terminal through a path through the capacitor 17b and a path through the constant current source 17c. The gate of the transistor 17a is connected to the output terminal of the latch circuit 15 via the inverter 17d. The back gate of the transistor 17a is connected to the ground terminal.

  A basic operation (generation operation of the output voltage Vo) of the switching regulator configured as described above will be described.

  When the desired output voltage Vo is generated from the input voltage Vi, the comparator 12 generates a comparison signal Sa between the feedback voltage Vfb corresponding to the output voltage Vo and a predetermined reference voltage Vref. More specifically, in the comparator 12, the comparison signal Sa is set to the high level when the feedback voltage Vfb is lower than the reference voltage Vref, and is set to the low level when it is high.

  On the other hand, the oscillator 14 generates a clock signal Sb having a predetermined frequency in order to determine the switching frequency of the output transistor 11.

  In the latch circuit 15, a PWM signal Sc having a desired duty is generated based on the comparison signal Sa and the clock signal Sb. More specifically, in the latch circuit 15, the PWM signal Sc is set to the high level at the rising edge of the clock signal Sb, and the PWM signal Sc is set to the low level at the falling edge of the comparison signal Sa. In other words, in the latch circuit 15, when the PWM signal Sc transitions to the high level according to the clock signal Sb, the PWM signal Sc is maintained at the high level until the feedback voltage Vfb reaches the reference voltage Vref. When Vfb reaches the reference voltage Vref, the PWM signal Sc transitions to a low level. Therefore, as the output voltage Vo is lower than the target value, the on-duty of the output transistor 11 increases, and as the target value is approached, the on-duty of the output transistor 11 decreases.

  In the pre-driver 16, the drive capability of the PWM signal Sc is increased, and the gate signal Sd of the output transistor 11 is generated.

  The output transistor 11 is switching-controlled based on the gate signal Sd, and a rectangular wave switch voltage Vsw is drawn from the source thereof. The switch voltage Vsw is smoothed by a smoothing circuit including a diode D1, an inductor L1, and a capacitor C1, and a desired output voltage Vo is generated. The output voltage Vo is divided by a voltage dividing circuit composed of resistors R1 and R2, and the feedback voltage Vfb described above is generated.

  With such feedback control, the switching regulator of this embodiment generates a desired output voltage Vo from the input voltage Vi with a very simple configuration.

  Next, the slope adding operation of the reference voltage Vref in the switching regulator having the above configuration will be described with reference to FIGS.

  FIG. 2 is a waveform diagram for explaining the operation of the slope adding circuit 17, and FIG. 3 is a waveform diagram for explaining the function and effect of the slope adding circuit 17.

  In FIG. 2, the PWM signal Sc, the output voltage Vo, and the feedback voltage Vfb are shown by solid lines in order from the top. Further, the reference voltage Vref (one-dot chain line) of the present embodiment is shown in contrast with the feedback voltage Vfb.

  On the other hand, in FIG. 3, the comparison signal Sa, the gate signal Sd, the output voltage Vo, the feedback voltage Vfb, and the clock signal Sb of the present embodiment are indicated by solid lines in order from the top, and are compared with these. The voltage behavior when the slope adding circuit 17 is not provided (the output operation becomes unstable due to inevitable delays occurring in the operations of the comparator 12, the latch circuit 15, and the pre-driver 16, and the ripple of the output voltage Vo) Is shown by a broken line). Further, a reference voltage Vref (one-dot chain line) is shown in contrast with the feedback voltage Vfb. Note that, if the voltage behaviors of the feedback voltage Vfb according to the presence or absence of the slope adding circuit 17 are superimposed on each other, it will be very difficult to see. (No slope added, bottom with slope added).

  As shown in FIG. 2, in the switching regulator of this embodiment, a negative slope is added to the reference voltage Vref by the slope adding circuit 17 at the timing when the output transistor 11 is turned on.

  More specifically, the transistor 17a of the slope load circuit 17 is subjected to switching control in a complementary manner to the output transistor 11 based on the PWM signal Sc that is inverted and input via the inverter 17d.

  That is, when the output transistor 11 is turned off, the transistor 17a is turned on. As a result, since the capacitor 17b is charged by the DC voltage source 13, the reference voltage Vref is raised to a predetermined voltage value (electromotive voltage of the DC voltage source 13) and maintained there.

  On the other hand, when the output transistor 11 is turned on, the transistor 17a is turned off. As a result, the accumulated charge in the capacitor 17b is discharged through the constant current source 17c, so that a negative slope is added to the reference voltage Vref. The slope of the slope can be arbitrarily adjusted according to the current amount of the constant current source 17c.

  As described above, if the negative voltage is added to the reference voltage Vref, the output logic of the comparator 12 is switched earlier than the original timing. Therefore, the influence of unavoidable delays occurring in the operations of the comparator 12, the latch circuit 15, and the pre-driver 16 can be reduced or eliminated, so that the output operation is stabilized as shown in FIG. A desired oscillation frequency can be obtained.

  In addition, adding a negative slope to the reference voltage Vref shortens the time until the feedback voltage Vfb reaches the reference voltage Vref, and eventually reduces the on-duty of the output transistor 11 intentionally. . Therefore, the switching regulator of this embodiment can make subharmonic oscillation less likely to occur, so that the generation of ripples can be suppressed and the output accuracy can be increased.

  In the above embodiment, the case where the present invention is applied to the step-down switching regulator has been described as an example. However, the application target of the present invention is not limited to this, and the step-up switching is not limited thereto. The regulator can also be widely applied.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  For example, in the embodiment described above, the configuration using the constant current source 17c has been described as an example of the discharging unit that configures the slope load circuit 17, but the configuration of the present invention is not limited to this. The constant current source 17c may be replaced with a resistor.

  The present invention is a useful technique for improving the stability and accuracy of output voltage in all applications using a switching regulator such as an ink jet printer.

These are circuit diagrams which show one structural example of the switching regulator which concerns on this invention. These are waveform diagrams for explaining the operation of the slope adding circuit 17. These are waveform diagrams for explaining the operation and effect of the slope adding circuit 17. These are circuit diagrams which show one prior art example of a switching regulator.

Explanation of symbols

10 Switching regulator IC
11 N-channel field effect transistor (output transistor)
12 Comparator 13 DC Voltage Source 14 Oscillator 15 Latch Circuit (RS Flip-Flop)
16 Pre-driver 17 Slope addition circuit 17a N-channel field effect transistor (switch)
17b Capacity 17c Constant current source (discharge means)
17d Inverter D1 Diode (Schottky diode)
L1 Inductor C1 Capacitance R1, R2 Resistance

Claims (6)

A comparator that generates a comparison signal between a feedback voltage corresponding to the output voltage and a predetermined reference voltage, an oscillator that generates a clock signal of a predetermined frequency, and a pulse width modulation signal having a desired duty based on the comparison signal and the clock signal And a latch circuit that is switching-controlled based on the pulse width modulation signal, and an output transistor from which a rectangular wave-shaped switch voltage is drawn from one end thereof, and smoothing the switch voltage, A switching regulator that generates a desired output voltage from an input voltage,
A switching regulator comprising a slope adding circuit for adding a negative slope to the reference voltage at a timing when the output transistor is turned on. The slope adding circuit includes a switch inserted between an application terminal of the reference voltage and a reference voltage input terminal of the comparator, a capacitor inserted between a reference voltage input terminal of the comparator and a ground terminal, A discharge means for discharging the accumulated charge of the capacitor,
The switching regulator according to claim 1, wherein the switch is controlled to be complementarily switched with the output transistor based on the pulse width modulation signal.   The comparator sets the comparison signal to a high level when the feedback voltage is lower than the reference voltage, and sets the comparison signal to a low level when the feedback voltage is high, and the latch circuit has the pulse width at a rising edge of the clock signal. 3. The switching regulator according to claim 1, wherein the modulation signal is set to a high level and the pulse width modulation signal is set to a low level at a falling edge of the comparison signal.   4. The switching regulator according to claim 1, wherein one end of the output transistor is connected to an input end of the input voltage, and the switch voltage is extracted from the other end. 5.   5. The switching regulator according to claim 1, further comprising a pre-driver that increases a driving capability of the pulse width modulation signal to generate a control signal of the output transistor. 6.   A semiconductor device in which the comparator, the oscillator, the latch circuit, the pre-driver, the output transistor, and the phase compensation circuit are integrated; and externally attached to the semiconductor device to smooth the switch voltage to obtain a desired value 6. A smoothing circuit that generates an output voltage; and a voltage dividing circuit that is externally attached to the semiconductor device and divides the output voltage to generate the feedback voltage. Switching regulator.

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