JP2008158699A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor allowing prevention of deterioration of performance of the whole processor by reducing overhead of the processor controlling a vector arithmetic processor. <P>SOLUTION: This processor 1 incudes: a first processor 2 outputting a vector arithmetic parameter for a vector operation; and a second processor 3 executing the vector operation based on the vector arithmetic parameter. The second processor 3 has: a first register 26 storing the vector arithmetic parameter; a scalar processor 31 writing the vector arithmetic parameter into the first register 26 according to an instruction designated from the first processor 2; and one or more vector processors 32, 33 executing the instruction designated by the first processor 2 based on the vector arithmetic parameter stored in the first register 26. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a processor, and more particularly to a processor capable of performing vector operations.

  Conventionally, a multiprocessor including a plurality of processors has been developed and put into practical use. For example, a multiprocessor has been proposed in which a control processor performs overall processing and exceptional processing, and a vector coprocessor performs iterative processing (see, for example, Patent Document 1).

  In the system according to the proposal, the control processor performs a scalar operation and the vector coprocessor performs a vector operation, and the control processor initializes, starts, and stops the vector coprocessor. As a result, the processing of the two processors is synchronized.

However, when such a multiprocessor is applied to data processing with a short vector length (that is, a small number of data) in vector operation, the overhead of the control processor for initialization, start and stop increases, and the entire processor There was a problem that the performance of was difficult to improve. This is because communication between the control processor and the vector coprocessor is rate-determined and the performance of the entire processor is limited.
Japanese Patent Laid-Open No. 10-149341

  Therefore, an object of the present invention is to provide a processor that can reduce the overhead of the processor that controls the processor for vector operation and can prevent the performance of the entire processor from being lowered.

  According to an aspect of the present invention, the method includes: a first processor that outputs a vector operation parameter for vector operation; and a second processor that executes the vector operation based on the vector operation parameter; The second processor includes a first register that stores the vector operation parameter, a scalar processor that writes the vector operation parameter to the first register in accordance with an instruction specified by the first processor, One or more vector processors that execute an instruction designated by the first processor based on the vector operation parameter stored in the first register;

  ADVANTAGE OF THE INVENTION According to this invention, the processor which can reduce the overhead of the processor which controls the processor for vector operations, and can prevent the fall of the performance of the whole processor is realizable.

Embodiments of the present invention will be described below with reference to the drawings.
(Configuration of the entire processor 1)
First, the configuration of the processor according to the present embodiment will be described. FIG. 1 is a block diagram showing a configuration of a processor according to the present embodiment.
Hereinafter, the present embodiment will be described using an example of a processor as a decoding device for image data and audio data in a digital television apparatus.

  The processor 1 shown in FIG. 1 is a multiprocessor including two sub-processors 2 and 3. The first processor 2 is a processor for control and audio data processing, and the second processor 3 is a processor for video data processing. The control processor 2 performs control of the processor 3 and audio data decoding processing, and the vector calculation processor 3 performs block-by-block processing on the image data divided in block units (for example, macroblock units). The image data decoding process is repeated so that the same process is repeated.

  The processor 1 further includes a direct memory access (hereinafter referred to as DMA) controller (hereinafter abbreviated as DMAC) 4 and a bus interface (hereinafter abbreviated as bus I / F) 5. The bus I / F 5 is an interface for connecting the processors 2 and 3 to the global bus 7. A main memory 6 as a storage unit is connected to the global bus 7. Therefore, the processors 2 and 3 are connected to the main memory 6 via the global bus 7. The global bus 7 is a bus for not only transmitting / receiving data between the processor 1 and the main memory 6 but also for communicating with circuits, processors, chips, etc. for realizing other functions of the digital television apparatus. .

The processor 2 and the processor 3 are connected to each other via the control bus 8, and the DMAC 4 is connected to the control bus 8.
Furthermore, the processor 3 is connected to the bus I / F 5 via the local bus 9.

The processor 2 includes an instruction cache 11, a data cache 12, and a central processing unit (hereinafter abbreviated as CPU) 13. The processor 2 controls the processor 3 and processes audio data as described above.
The processor 3 includes an instruction memory 21, a data memory 22, a vector register 23, a DMAC 24, a control bus register 25, a control register 26, a scalar processor 31, a plurality of (here, two) vector processors 32, 33, and decodes image data.
In FIG. 1, the processor 3 is provided with two vector processors 32 and 33, but may be three or more.

(Configuration of processor 2, processor 3 and DMA 4)
Next, the configurations of the processor 2 and the processor 3 that are sub-processors will be described.
First, the processor 2 will be described.
The instruction cache 11 is a cache for temporarily storing one instruction or a plurality of instructions to be executed by the CPU 13 (a program consisting of a plurality of instructions is also simply referred to as an instruction hereinafter). This is a cache for temporarily storing data to be processed and processed data.
The CPU 13 reads and executes the instruction stored in the instruction cache 11 for the data stored in the data cache 12.
The instruction stored in the instruction cache 11 of the processor 2 is an instruction read from the main memory 6. Data written to the data cache 12 is also data read from the main memory 6. Each data processed in the processor 2 and temporarily stored in the data cache 12 is transferred to the main memory 6 and stored therein.

Therefore, the processor 2 executes the instruction stored in the main memory 6, transfers the instruction to be executed in the processor 3 stored in the main memory 6 and the target data to be decoded to the processor 3 by the DMAC 4, and sends it to the processor 3. Predetermined image processing, here decoding processing, is executed by vector operation.
Further, the processor 2 outputs a vector operation parameter to the processor 3 as described later.

Next, the processor 3 will be described.
The instruction memory 21 is an instruction holding unit having a storage area for storing instructions that the scalar processor 31, the vector processors 32 and 33, and the DMAC 24 should execute or can execute.
The data memory 22 is a data holding unit having a storage area for storing target data to be decoded and decoded result data. That is, the data memory 22 has two storage areas, a target data storage area and a result data storage area.

  The instruction written to the instruction memory 21 is also an instruction read from the main memory 6, and the data written to the data memory 22 is also data read from the main memory 6. Note that the result data obtained by processing in the processor 3 is also output to the data memory 22, and then transferred and stored in the main memory 6.

  The vector register 23 is provided between the vector processors 32 and 33 and the data memory 22, and continuously stores unit data to be processed by the vector processors 32 and 33, for example, 16 × 16 pixel macroblock data. is there. Target data to be processed in the vector processors 22 and 23 and result data obtained by processing in the vector processors 22 and 23 are stored. That is, the vector register 23 has two storage areas, a target data storage area and a result data storage area.

The DMAC 24 constitutes a transfer unit for transferring target data and result data between the vector register 23 and the data memory 22. The operation of the DMAC 24 is controlled by an instruction included in a scalar LIW (Long Instruction Word) instruction read from the instruction memory 21. Accordingly, while a certain vector operation is being executed, target data to be processed thereafter can be transferred from the data memory 22 to the vector register 25 and set in advance. Instructions for controlling the DMAC 24 will be described later.
The control bus register 25 controls, by the processor 2, the address of the instruction to be executed in the instruction memory 21, the address of the target data to be processed in the data memory 22, the address for storing the result data obtained by processing, and the like. It is a register for designating by being written via the bus 8.

  For example, the instruction memory 21 may store a plurality of instructions each as a subroutine program, and the data memory 22 may store a large size of data. In such a case, in the control bus register 25, an initial value of a program counter indicating which instruction (subroutine) in the instruction memory 21 is to be activated, and an address of the data in the data memory 22 storing a large size data Is retained.

Specifically, when large-sized result data obtained by processing is supplied to the processor 2 via the local bus 9, the control bus register 25 includes a scalar processor 31 and a vector processor. 32 and 33 write the address data in the data memory 22 into which the result data is written.
In some cases, data of a small size is transmitted and received between the processor 2 and the processor 3. In such a case, the control bus register 25 also stores data having a small data structure transferred between the processor 2 and the processor 3.

  The control register 26 is a register for storing vector operation parameters received from the processor 2 and necessary for the vector processors 32 and 33 to perform various vector operations. Each of the plurality of registers of the control register 26 stores scalar data such as the number of repetitions of vector operation, the width of automatic increment at the time of vector operation, constant value data used in the vector operation unit, and feature value data of each block. The These data are not set directly from the processor 2 via the control bus 8. These data are directly set in the control register 26 by the scalar processor 31.

  The scalar processor 31 of the processor 3 includes a general-purpose register therein and includes a circuit that executes an arithmetic logic operation instruction, a branch instruction, and the like. As will be described later, the scalar processor 31 is a processor for writing and setting parameters relating to instructions executed in the vector processors 32 and 33 in accordance with instructions specified by the processor 2. Data transfer between the scalar processor 31 and the control bus register 25 and the control register 26 is performed so that the scalar processor 31 can read and write data to and from the control bus register 25 and the control register 26 as necessary. The buses 41 and 42 are connected.

  For example, when the scalar processor 31 performs processing based on the feature amount of each block based on the feature amount data indicating the complexity of the image obtained by the vector processors 32 and 33, the data related to the feature amount data is The data is written into the control bus register 25 or the control register 26.

The scalar processor 31 is preferably a processor that does not execute processing such as an operating system (hereinafter referred to as OS). The scalar processor 31 may be configured to be able to perform OS processing. However, when configured to be able to perform OS processing, there is a demerit that the area of the scalar processor 31 in a chip that is a semiconductor device increases. . As will be described later, if only a parameter setting process or a predetermined scalar operation (for example, calculation of an image feature amount) is performed in addition to the parameter setting process, the scalar processor 31 performs an OS process. A processor that cannot be executed is preferable.
Furthermore, the scalar processor 31 may be a dedicated processor for setting parameters relating to instructions executed in the vector processors 32 and 33.

The vector processors 32 and 33 each execute an instruction designated by the processor 2 based on the vector operation parameters stored in the control register 26. That is, the vector processors 32 and 33 respectively read data from the control bus register 25, the control register 26, and the vector register 23 as necessary, repeatedly execute an operation based on a designated instruction, and obtain result data of an operation result. Is written into the control bus register 25 or the vector register 23. For this reason, the vector processors 32 and 33 are connected to the control bus register 25 and the control register 26 by data transfer buses 41 and 42. The vector processors 32 and 33 may execute different calculations, or may perform the same calculation.
In particular, a data transfer bus 42 provided to connect between the scalar processor 31 and the control register 26 so that a plurality of parameter data respectively corresponding to a plurality of instructions can be simultaneously set in the control register 26 includes a plurality of parameter data. It consists of signal lines or multiple buses. Here, three bus signal lines are provided in parallel so that parameter data corresponding to the three instructions can be written and set in parallel in the control register 26. Therefore, the data transfer bus 42 has a higher parallel data transfer capability than the control bus 8, so the processor 3 simultaneously executes a plurality of vector processors (here, two vector processors 32 and 33) for parallel processing. be able to.

  As will be described later, the instruction for the scalar processor 31 includes an instruction for instructing what data the scalar processor 31 sets in the control register 26. Thereby, since it is not necessary for the processor 2 to set parameter data for the control register 26, the overhead for the processor to control the processor 3 is reduced, that is, the entire processor 1 is communicated between the processors 2 and 3. The processing speed is not limited.

  In this embodiment, a plurality of (here, two) vector processors 32 and 33 are provided for one scalar processor 31. As a result, it is possible to limit the processing speed of the processor 1 by preventing communication from the processor 2 to a plurality of vector processors as in the prior art.

  The DMAC 4 constitutes a transfer unit that performs data transfer by DMA between the main memory 6 and the instruction memory 21 and between the main memory 6 and the data memory 22. The DMAC 4 performs data transfer processing between the main memory 6 and the instruction memory 21 and between the main memory 6 and the data memory 22 under the control of the CPU 13 of the processor 2. Specifically, the CPU 13 of the processor 2 controls the DMAC 4, reads out the instruction to be executed and the target data from the main memory 6, transfers the data to the instruction memory 21 and the data memory 22, and stores the result data in the data memory. 22 to the main memory 6 for writing. In the case of a vector operation, an instruction to be executed often executes the same process repeatedly. Therefore, the instruction memory 21 can store a plurality of instructions.

  Then, the CPU 13 writes the address data of the instruction stored in the instruction memory 21 to a predetermined area of the control bus register 25 of the processor 3 via the control bus 8. Specifically, as will be described later, when performing the decoding process, the processor 2 notifies the processor 3 of the instruction to be executed by specifying the instruction start address in the instruction memory 21 and specifies the instruction. be able to.

  Note that the instruction memory 21 and the data memory 22 in the processor 3 may be caches depending on the processing contents or the processing target data. Furthermore, even when the capacity of the instruction memory 21 and the data memory 22 of the processor 3 can be increased, the occurrence of a cache miss is reduced, so that the instruction memory 21 and the data memory 22 may be caches.

As described above, the processor 1 is a so-called media processor that processes audio data and image data, but the processor 2 controls the processor 3 to perform decoding processing of image data.
In the present embodiment, as described above, the processor 3 performs an image decoding process such that the image data is divided into blocks and the same process is repeated for each block. Therefore, in the processor 3, an instruction memory 21 and a data memory 22 having a relatively small storage capacity are used instead of a cache so as to be optimal for such processing. This is because, in such a process, the CPU 13 can predict the instruction to be executed for the decoding process and the data to be decoded, and if the cache is used, the process is stopped due to the occurrence of a cache miss. It will occur.

(order)
Next, instructions executed in the processor 3 will be described.
The instructions executed in the processor 3 are roughly classified into two types: a scalar LIW instruction and a vector LIW instruction. In particular, the scalar LIW instruction includes a field for setting various parameters related to DMA executed by the DMAC 24 in the processor 3 and a field for setting a parameter for vector operation in the control register 26.

  The instruction memory 26 stores an instruction group in which a scalar LIW instruction as an instruction for the scalar processor 31 and a vector LIW instruction as an instruction for the vector processors 32 and 33 are mixed. Therefore, each of the scalar LIW instruction and the vector LIW instruction has a designation (or identification) field for identifying whether the instruction is a scalar processor instruction or a vector operation instruction. The vector LIW instruction includes data indicating, that is, identifying which of the vector processors 32 and 33 the instruction is for the processor.

  FIG. 2 is a diagram for explaining the configuration of the instruction memory 21 in which a plurality of instructions are stored. As shown in FIG. 2, the instruction memory 21 stores a plurality of LIW instructions and includes a mixture of instructions for the scalar processor 31 and instructions for the vector processors 32 and 33. When the CPU 13 designates an instruction to be executed from among a plurality of LIW instructions, the instruction to be executed by the vector processors 32 and 33 is designated by designating the start address of the instruction to be executed in the instruction memory 21. Notice.

FIG. 3 is a diagram illustrating a configuration example of each LIW instruction. Here, one LIW instruction 50 has a length of 128 bits. In both of the scalar LIW instruction and the vector LIW instruction, one LIW instruction 50 includes a field 51 indicating whether the instruction is for the scalar processor 21 or the processor of the vector processors 31 and 32. . That is, it has an identification field for identifying the processor to be executed. Furthermore, in this embodiment, one LIW instruction 50 has four fields 52, 53, 54, and 55.
First, the case where the LIW instruction 50 is a scalar LIW instruction will be described. The scalar LIW instruction includes a DMA instruction for the DMAC 24 and a vector operation parameter setting instruction for setting a vector operation parameter in the control register 26.

When the scalar LIW instruction is a DMA instruction for the DMAC 24, the field 52 includes an activation instruction for the DMAC 24 and a parameter for DMA (for example, address data of the target data in the data memory 22). 54 and 55 are described so as to include a NOP indicating that nothing is executed. In other words, the DMAC 24 is configured to perform DMA between the vector register 23 and the data memory 22 based on the parameters included in the field 52 in the scalar LIW instruction.
The start instruction for DMAC 24 and the parameters for DMA are included in the scalar LIW instruction because the scalar LIW instruction is compared with the vector LIW instruction for the scalar operation to be supplied to the scalar processor 31. This is because the instruction can be shorter than the instruction executed by the vector processors 32 and 33.

When the scalar LIW instruction is an instruction for setting various parameters for vector operation in the control register 26, the fields 53, 54, and 55 include parameters for setting various parameters in the control register 26. Specifically, the fields 53, 54, and 55 include the register number and parameter value in the control register 26, respectively. Each register in the control register 26 corresponds to each parameter in the vector operation, and various parameters for the vector operation are set by designating the register number and writing the parameter value in the register of that number. Can be done. The various parameters are, for example, the number of repetitions of vector operation, the width of automatic increment at the time of vector operation, and constant value data used by the vector operation unit. Therefore, the scalar LIW instruction includes an instruction for setting various parameters for vector operation executed in each of the vector processors 32 and 33 in the control register 26.
As described above, the scalar LIW instruction may be an instruction for instructing DMAC 24 for DMA processing or an instruction for instructing parameter setting for vector operation. The vector LIW instruction is an instruction executed by the vector processor specified in the identification field. That is, the instructions stored in the instruction memory 21 include an instruction for instructing DMA processing to the DMAC 24, an instruction for instructing parameter setting for vector operation, and an instruction executed by the vector processor. An instruction for instructing DMA processing and an instruction for instructing parameter setting for vector operation are included in one LIW instruction.

  The vector operation is executed using the parameters stored in the corresponding register in the vector processor specified by the identification field. For example, when a vector operation is repeatedly executed in the vector processor 32, one or more in the instruction memory 21 is stored in the control register 26 based on data in a predetermined register that stores the number of repetitions of the vector processor 3. Multiple vector LIW instructions are executed repeatedly for that number of times. Note that parameters such as the number of repetitions are stored in the control register 26 by the scalar processor 31 as described above.

  Therefore, since a plurality of instructions can be included in the vector LIW instruction, one of the plurality (here, two) of vector processors is automatically executed while a certain operation is repeatedly executed. Another vector processor can be activated by the vector LIW instruction to automatically perform another operation repeatedly. In addition, the scalar processor 31 can execute the scalar LIW instruction in parallel while a plurality of vector processors automatically execute certain operations repeatedly. Furthermore, the DMAC 24 can execute DMA in parallel with the processing by the scalar processor 31 and the vector processors 32 and 33.

(Process flow)
Next, an operation for synchronizing processing between the processor 2 and the processor 3 when image data decoding processing is performed will be described. FIG. 4 is a diagram for explaining an example of the flow of processing between the processors 2 and 3. FIG. 4 shows an example in which the same instruction is executed for the data of a plurality of macroblocks by the activation of one instruction from the processor 2 when decoding the data of the plurality of macroblocks.
As described above, first, the processor 2 uses the DMA 4 to load, transfer, or store an instruction to be executed or a plurality of instruction groups (that is, a program) in the instruction memory 21 in advance (step S1). In the case where the same instruction is repeatedly performed on a plurality of blocks as in the image data decoding process, once the instruction is stored in the instruction memory 21, the stored instruction is thereafter stored. This is because it is only necessary to repeat the above.
Note that the processor 2 may transfer the instruction memory 21 by the DMAC 4 immediately before the decoding process.

Then, the processor 2 transfers and supplies the target data to be decoded to the data memory 22 of the processor 3 (step S2). Here, for example, data of a plurality of macro blocks is collectively transferred to the target data storage area of the data memory 22 as the target data. At that time, the structure or size of the supplied data may be small or large.
When transferring target data of a small size to the processor 3, the processor 2 transfers the target data by directly writing it to the control bus register 25 in the processor 3 via the control bus 8.

  On the other hand, when transferring the target data having a large data structure to the processor 3, the processor 2 first uses the DMAC 4 as a first step and stores the data in the data memory 22 in the processor 3 via the local bus 9. Data is transferred to the target data storage area by DMA. Note that the processor 2 may transfer a plurality of data at once by starting the DMAC 4 instead of transferring the target data in units of macroblocks.

  Then, as the second stage, the processor 2 writes the address data of the transferred target data, that is, the address data in the data memory 22 to the control bus register 25 of the processor 3 via the control bus 8. As a result, the processor 3 can obtain the address data of the target data to be decoded.

As a third stage, the DMAC 24 in the processor 3 is activated by an instruction for the DMAC 24 stored in the instruction memory 21. The DMAC 24 uses the address data stored in the control bus register 25 to transfer the data of one macroblock in the data memory 22 to the vector register 23 by DMA. Note that the processor 2 may transfer data of a plurality of macroblocks collectively by starting the DMAC 24 once.
As described above, the target data to be decoded is stored in the vector register 23 of the processor 3.

  Further, in order to transfer the result data to the main memory 6 by DMA, the processor 2 notifies the processor 3 of the address in the data memory 22 where the result data is stored (step S3). This notification is performed by the processor 2 writing the address in the control bus register 25 as described above.

  Next, the processor 2 notifies the processor 3 of the instruction to be executed in the instruction memory 21. Specifically, this notification is made by the processor 2 via the control bus 8 in the predetermined area of the control bus register 25 of the processor 3, the start address data in the instruction memory 26 of the instruction (or subroutine) to be executed. Is done by writing Thereby, the processor 2 can designate the instruction to be executed in the instruction memory 21 to the processor 3.

Then, the processor 2 sends, via the control bus 8, data indicating an activation instruction, for example, flag data, in a predetermined area of the control bus register 25 (an area other than the area where the data of the start address of the instruction is stored). Write. As a result, the processor 2 can instruct the vector processors 32 and 33 of the processor 3 to start the instruction (step S4).
As a result, the processor 3 starts an instruction from the designated address, and the designated vector processor executes the instruction (step S11).
At this time, the instruction is activated only once, and the instruction is repeated for the data of a plurality of macroblocks. For example, when the same instruction is executed for each macroblock, a predetermined parameter (for example, a parameter for the number of repetitions) is set to 1 so that the instruction is repeatedly executed for a plurality of macroblocks. It is possible to cause the designated vector processor to execute the same instruction for a plurality of macroblocks by activating the instruction only once.

After step S4, the processor 2 determines whether or not the execution of the instruction for one macroblock from the processor 3 is completed (step S5).
On the other hand, the processor 3 executes an instruction for one macroblock, and outputs an interrupt instruction to the processor 2 when the execution of the instruction is completed. As a result, the interrupt instruction is received by the processor 2, and the processor 2 knows that the execution of the instruction for one macroblock is completed. Therefore, in step S5, it is determined that the instruction has been executed, and the result data is output to the main memory 6 (step S6).

The decoded data, that is, the result data is temporarily stored in the vector register 23, but thereafter transferred to the designated address in the result data storage area in the data memory 22 by the DMAC 24 and stored. Therefore, the result data is output from the data memory 22 to the main memory 6 or the processor 2.
Specifically, the size or structure of the result data obtained by decoding may be small or large. In the case of data having a small data structure, the processor 3 writes the result data to the control bus register 25 in the processor 3 via the control bus 8. The processor 2 can obtain the result data by directly reading the result data from the control bus register 25.

  Further, when transferring the result data having a large data structure from the data memory 22 to the main memory 6, the address of where the result data is to be stored in the data memory 22 is specified in step S3. The DMAC 24 is activated by an instruction for executing DMA transfer of the DMAC 24 in the instruction memory 21, and the result data can be transferred from the vector register 23 to the designated address in the result data storage area of the data memory 22. Note that the processor 3 may collectively transfer a plurality of data from the vector register 23 to the data memory 22 when the DMAC 24 is activated once.

Then, the processor 2 uses the DMAC 4 to transfer the result data from the data memory 22 to the main memory 6 via the local bus 9 and output the result data.
Here again, the processor 2 may collectively transfer a plurality of result data from the data memory 22 to the main memory 6 when the DMAC 4 is activated once.

  When the target data is output to the main memory 6, it is determined whether or not there is target data to be decoded next, that is, whether or not execution of instructions has been completed for all macroblocks that are target data to be decoded. Judgment is made (step S7).

  If the processing has not been completed for all macroblocks, the processing returns to step S5, and the processor 2 waits to receive an interrupt instruction from the processor 3 in step S5. When the interrupt instruction is received, it is determined in step S5 that the execution of the instruction for the data of the next macroblock has been completed, and the processor 2 performs steps S5 to S7 until the execution of the instruction is completed for all the macroblocks. repeat.

  Accordingly, the processor 3 sequentially executes instructions for data of a plurality of macroblocks, and outputs an interrupt instruction each time execution of instructions for each macroblock is completed. When the execution of the instruction for the data of all designated macroblocks is completed, the processing of the processor 3 stops.

  At this time, specifically, in the processor 3, the DMAC 24 is activated by an instruction for the DMAC 24 stored in the instruction memory 21, and the target data in the data memory 22 is transferred to the vector register 23. Then, the processor 3 executes an instruction for the data of each macro block which is the next target data, but the instruction is not activated from the processor 2, and as described above, the instruction is repeated This is automatically executed by the processor 3 as many times as set by parameters such as. Each time execution of an instruction is completed for each macroblock, result data is output and target data to be processed next is input, and the instruction is executed.

Therefore, for example, even when an instruction is executed n times to perform the same decoding process on n macroblocks, the processor 2 activates the instruction to the processor 3 only for the first time. After that, the same instruction can be automatically executed for n macroblocks in the processor 3. Therefore, the processor 2 can execute other processes during that time.
FIG. 5 is a diagram for explaining another example of the flow of processing between the processors 2 and 3. The same processes as those in FIG. 4 are denoted by the same reference numerals and description thereof is omitted. FIG. 5 shows an example in which an instruction is executed for one macroblock data each time an instruction from the processor 2 is activated when data of a plurality of macroblocks is decoded.
Also in the case of FIG. 5, first, the processor 2 loads an instruction to be executed or a plurality of instruction groups to the instruction memory 21 by the DMA 4 (step S1).
Then, the processor 2 transfers the macroblock data, which is the target data to be decoded, to the data memory 22 of the processor 3 by the DMA 4 and supplies the data (step S2). Here, for example, data of one macro block is transferred to the target data storage area of the data memory 22 as the target data.

Further, although the structure, that is, the size of the supplied target data may be small or large, the target data is transferred from the processor 2 to the processor 3 in the same procedure as described in FIG.
As a result, the target data to be decoded is stored in the vector register 23 of the processor 3.
Further, the processor 2 notifies the processor 3 of the address in the data memory 22 where the result data is stored (step S3).

Then, the processor 2 instructs the processor 3 to start an instruction (step S4).
As a result, in the processor 3, the instruction is started from the designated address and the instruction is executed. However, when the HALT instruction (stop instruction) written in the instruction is executed, the vector processor temporarily stops (step S21).

  When the HALT instruction is executed, the processor 3 notifies the processor 2 that the HALT instruction has been executed, and the processor 2 can detect the end of execution of the instruction.

  After step S4, the processor 2 monitors whether or not the execution of the instruction has ended (step S5), and outputs the result data when detecting the end (step S6). The output of the result data is the same as in the case of FIG.

  When the target data is output to the main memory 6, it is determined whether or not there is target data to be decoded next, that is, whether or not instruction execution has been completed for all the macroblocks to be decoded (step). S22).

If the instruction execution has not been completed for all the macroblocks, the processing of the processor 2 returns to step S2, and the target data of the next macroblock is transferred from the main memory 6 to the data memory 22 and supplied ( Step S2).
Thereafter, the above-described processing from steps S2 to S22 is repeated until all the designated blocks are executed.

The processor 3 executes the HALT instruction at the end of the execution of the instruction for the data of one macroblock which is the target data, and thereafter, the execution of the instruction is stopped. In step S4, when an instruction is activated from the processor 2, the instruction is executed again.
In this way, the same instruction is continuously executed on the data of a plurality of macroblocks.

  Also in the process as shown in FIG. 5, the processor 2 only needs to specify and start an instruction as a process for the vector operation, so that the overhead for controlling the processor 3 can be reduced.

  As described above, according to the processor 1 according to the above-described embodiment, it is possible to reduce the overhead of the control processor 2 that controls the vector calculation processor 3 and to prevent the performance of the entire processor from being deteriorated. .

  Further, according to the processor 1, since the vector operation instruction is directly supplied from the instruction memory 21 to the vector processors 32 and 33, the performance of the processor 1 is hardly lowered even for an application having a high frequency of vector operation.

  Furthermore, the number of vector processors in the processor 3 can be flexibly adjusted according to the ratio between the scalar operation and the vector operation of the application to be applied, thereby achieving high performance at low cost according to a wide variety of applications. A possible configuration can be provided.

(Modification)
Next, a modified example will be described.
FIG. 6 is a block diagram illustrating a configuration example of a processor according to a first modified example in which a plurality of processors that perform vector operations are provided for one control processor. The same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. As shown in FIG. 6, the processor 1A, which is a media processor, includes a single processor and a plurality of processors each performing vector operations. In the processor 1A, the control processor 2A has the same configuration as the processor 2 of FIG. The m processors 3A1 to 3Am (hereinafter collectively referred to as the processor 3A when referring to the respective processors) that perform vector operations have the same configuration as the processor 3 of FIG. 1, and each of the processors 3A1 to 3Am. The control bus register 25 is connected to the control bus 8, and the instruction memory 21 and the data memory 22 are connected to the local bus 9. Note that m is an integer. The DMAC 4A, like the DMAC 4 described above, transfers instructions and data between the instruction memory 21 and the main memory 6 of each processor 3A and between the data memory 22 and the main memory 6 of each processor 3A. Run under 2A control.

  According to such a configuration, when high performance is required for vector operation, even if a plurality of processors 3A are provided to increase the degree of parallelism, the processor 2 does not specify instructions as processing for vector operation. Since it only needs to be started, overhead can be reduced.

Compared to the configuration disclosed in Japanese Patent Laid-Open No. 10-149341 described above, the processor 1A having the configuration of FIG. 6 requires less overhead.
That is, in the configuration disclosed in Japanese Patent Laid-Open No. 10-149341 described above, when high performance is required for vector calculation, it is possible to cope with higher performance by providing a plurality of vector coprocessors to increase the degree of parallelism. However, the control processor has a high control overhead for starting, stopping, etc. for a plurality of vector coprocessors, and it is difficult to improve the performance. In order to increase the performance, it may be possible to arrange a plurality of processing cores composed of a control processor and a vector coprocessor. However, depending on the device to which such a multiprocessor is applied, the cost performance is lowered. .

  On the other hand, according to the processor according to the first modification, a plurality of sub-processors can be connected to one general-purpose control processor 2A. For high applications, high performance can be achieved more efficiently than before. Further, since it is possible to increase the number of sub-processors in units of the processor 3A, the processor 1A can achieve high performance efficiently for various applications by adjusting the number of processors 3A according to the application. A configuration can be provided. Further, each processor 3A includes a scalar processor, and the scalar processor performs a process for quickly starting the vector processor. Therefore, even if the number of processors 3A increases, the starting process of the vector operation is hardly rate-determined.

  FIG. 7 is a block diagram showing a configuration example of a processor according to a second modified example in which a SIMD (Single Instruction / Multiple Data) coprocessor is provided in a control processor, and a SIMD coprocessor is also provided in a processor that performs vector operations. FIG. The same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  The processor 2B has a CPU 13 that is a general-purpose processor that can be expanded, and a SIMD coprocessor 14 is connected to the CPU 13 as a processor that executes an expansion function. The processor 3B as a sub processor has a SIMD coprocessor 34 in addition to the same configuration as that shown in FIG. The SIMD coprocessor 34 has a general purpose register for the coprocessor. In this case, the scalar LIW instruction includes a field for specifying an operation in the SIMD coprocessor 34 in addition to a field for specifying a scalar operation for setting a parameter for vector operation and a field for setting a parameter to the DMAC 24. including.

  According to such a configuration, in the processor 3B that performs the vector operation, the SIMD coprocessor 14 or 34 that is a scalar processor can perform processing such as detection processing in the preprocessing of the deblocking processing on the image data. The processing capability of the processor 1B can be improved. That is, for example, in the processing of an image or the like, a vector operation and a scalar operation are mixed so that a scalar amount is calculated with respect to a result of image processing by vector operation, and further processing is performed based on the scalar amount. For complex applications, scalar operations can be made to the SIMD coprocessor 14 or 34.

  That is, in the configuration disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 10-149341, in the case of a complicated application in which such vector calculation and scalar calculation are mixed, the amount of vector calculation is increased with respect to an increase in the amount of scalar calculation. Does not increase relatively, so the overall performance of the processor is unlikely to increase.

  On the other hand, according to the processor 1B according to the second modification, the SIMD coprocessor 14 or 34 can process a process with a short vector length, so a process with a long vector length and a process with a short vector length can be performed. When they are mixed, high performance can be achieved efficiently in the processor 3B.

The apparatus according to the embodiment described above is a digital television apparatus. However, the above-described processors 1, 1A, and 1B may be other digital home appliances such as a DVD recorder, The present invention can also be applied to various image processing apparatuses such as an in-vehicle image recognition processing apparatus and a robot image recognition processing apparatus, and devices such as a personal computer and a mobile phone.
The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the structure of the processor concerning embodiment of this invention. It is a figure for demonstrating the structure of the instruction | indication memory in which the some instruction | command memorize | stored concerning embodiment of this invention. It is a figure which shows the structural example of each LIW instruction concerning embodiment of this invention. It is a figure for demonstrating the example of the flow of a process between two processors concerning embodiment of this invention. It is a figure for demonstrating the other example of the flow of a process between two processors concerning embodiment of this invention. It is a block diagram which shows the structural example of the processor of the 1st modification of embodiment of this invention. It is a block diagram which shows the structural example of the processor of the 2nd modification of embodiment of this invention.

Explanation of symbols

1, 1A, 1B processor, 2, 2A, 2B, 3, 3A, 3B sub-processor, 7 global bus, 8 control bus, 9 local bus, 21 instruction memory, 41, 42 data transfer bus, 50 LIW instruction, 51 ~ 55 fields

Claims (5)

A first processor for outputting vector operation parameters for vector operation;
A second processor that executes the vector operation based on the vector operation parameters;
Including
The second processor is
A first register for storing the vector operation parameters;
A scalar processor for writing the vector operation parameter to the first register in accordance with an instruction designated by the first processor;
One or more vector processors that execute instructions designated by the first processor based on the vector operation parameters stored in the first register;
A processor characterized by comprising:   A plurality of signal lines are provided to connect the scalar processor and the first register, and write a plurality of vector operation parameters in parallel. The processor of claim 1. An instruction holding unit for holding a plurality of instructions executable in the one or more vector processors;
A first transfer unit configured to transfer the plurality of instructions from the storage unit to the instruction holding unit in order to write the plurality of instructions from the storage unit to the instruction holding unit;
Have
3. The one or more vector processors each execute an instruction designated by the first processor from the plurality of instructions based on an address of the designated instruction. The processor described. A first processor for outputting vector operation parameters for vector operation;
A plurality of second processors each executing the vector operation based on the vector operation parameters;
Including
Each of the plurality of second processors is
A first register for storing the vector operation parameters;
A scalar processor for writing the vector operation parameter to the first register in accordance with an instruction designated by the first processor;
One or more vector processors that execute instructions designated by the first processor based on the vector operation parameters stored in the first register;
A processor characterized by comprising: A first processor for outputting vector operation parameters for vector operation;
A second processor that executes the vector operation based on the vector operation parameters;
Including
The second processor is
A first register for storing the vector operation parameters;
A first scalar processor for writing the vector operation parameter to the first register in accordance with an instruction designated by the first processor;
A second scalar processor that performs a predetermined scalar operation in accordance with an instruction designated by the first processor;
One or more vector processors that execute instructions designated by the first processor based on the vector operation parameters stored in the first register;
A processor characterized by comprising:

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