JP2008145921A - Driving circuit for active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device wherein the number of shift registers of a gate driver is decreased. <P>SOLUTION: The active matrix display device according to the present invention includes a pixel matrix having a plurality of pixels arrayed in a matrix form of N stages of P rows by Y columns, a source driver driving data lines connected to source terminals of pixel TFTs provided to the respective pixels, and the gate driver driving data lines connected to gate terminals of the pixel TFTs, where the gate driver includes at least one shift register in each stage and includes N×P gates and output lines of the shift registers of the respective stages are connected to P gate input terminals of the respective stages to output a plurality of gate pulses. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a drive circuit for an active matrix display device, and more particularly to an active matrix display device capable of reducing the size of a drive circuit for driving each pixel and increasing an effective display area.

  In a liquid crystal display device, two transparent substrates are arranged in parallel, a pixel electrode is provided on the opposing surface, and a liquid crystal layer is arranged in the gap between the two transparent substrates. Among liquid crystal display devices, an active matrix type liquid crystal display device displays pixels by arranging pixel electrodes in a matrix, and on and off in the vicinity of each pixel electrode on a transparent substrate. The switching element for this is arranged.

  FIG. 3 is a block diagram of a conventional active matrix type liquid crystal display device. The configuration and operation of the conventional liquid crystal display device will be described with reference to FIG. 3. The liquid crystal panel 1 is an active matrix type liquid crystal panel, 30, a scanning signal line 31, a data signal line 32, a switching element 33, and a counter electrode 34.

  The pixel electrode 30 is an electrode arranged in a matrix with respect to the row direction and the column direction. The scanning signal lines 31 are scanning signal lines for selecting pixels in the same direction, and it is assumed that p scanning signal lines 31 are provided along the column direction of the liquid crystal panel. The data signal lines 32 are data signal lines that transmit an applied voltage corresponding to display data to pixels in the same column direction, and q switching elements 33 are assumed to be provided along the row direction of the liquid crystal panel. This is a switching element that transmits data signal line data to the pixels of the liquid crystal cell. The counter electrode 14 is an electrode for supplying a common voltage for each liquid crystal cell. A liquid crystal cell is inserted between the pixel electrode 30 and the counter electrode 34. A liquid crystal cell is inserted between the pair of pixel electrodes 30 and the counter electrode 34. A liquid crystal cell inserted between a pair of the pixel electrode 30 and the counter electrode 34 is called a pixel.

  The liquid crystal cell serves as a shutter that adjusts light according to the voltage applied between the pixel electrode 30 and the counter electrode 34. If pixels are regularly assigned to RGB and an RGB color filter is provided on the counter electrode 34 side, RGB light is synthesized by the human eye and a color image is recognized. Based on the RGB arrangement of pixels, RGB data is assigned to the data line 32.

  The gate driver 2 is a circuit for sequentially applying p scanning signals X1, X2,... Xp to the scanning signal lines 11 in the liquid crystal panel 1. The source driver 3 is a circuit that generates an applied voltage corresponding to display data on the data signal line 12 in the liquid crystal panel 1 and outputs this voltage as pixel signals Y1, Y2,. The signal processing circuit 4 is a circuit that inputs a video signal from the outside, outputs display data to the source driver 3, and outputs control signals to the gate driver 2 and the source driver 3.

  Next, an operation for displaying an image on the liquid crystal panel 1 will be described. The signal processing circuit 4 controls the gate driver 2 by the control signal, and applies the scanning signal to the scanning signal line 31 of an arbitrary row of the liquid crystal panel 1. Then, the switching element 33 in that row is turned on, and the data line 32 and the pixel electrode 30 in each column are electrically connected. The signal processing circuit 4 supplies in advance to the source driver 3 data to be given to the pixels in each column of the row to which the scanning signal is supplied. The source driver 3 converts the display data into a voltage applied to each pixel electrode 30 and outputs it while the switching element 33 is in the ON state. The signal processing circuit 4 supplies display data to all the pixel electrodes 30 by sequentially scanning, for example, from the uppermost row (i = 1) to the lowermost row (i = p) of the liquid crystal panel 1.

  Next, the structure of the gate driver 2 will be described with reference to FIG. The output lines of the one-stage shift registers 22a, 22b, 22c and 22d are connected to the input terminals of AND gates 25a, 25b, 26c and 27d, respectively. Individual enable lines 24a, 24b, 24c and 24d are connected to the other input terminal of each AND gate. The output terminals of the AND gates 24a, 24b, 25c and 26d are connected to the buffer circuits 26a, 26b, 26c and 26d, respectively. As described above, the shift registers 22a, 22b, 22c, and 22d are arranged corresponding to the AND gates 25a, 25b, 26c, and 27d, respectively, and the area of the shift register is relatively large. The area becomes large, which is a factor that relatively decreases the ratio of the image area.

  The present invention reduces the ratio of the area occupied by the gate driver device by reducing the area occupied by the shift register in the gate driver in the active matrix display device, thereby reducing the size of the device and increasing the image display area. And it aims at realizing reduction of cost.

  In the gate driver in the active matrix display device, the total number of shift registers is reduced to 1 / th by arranging the shift registers arranged for each gate collectively for each stage (a total of N stages) composed of a plurality of gates. P.

The specific configuration of the present invention is as follows.
(1) a pixel matrix in which a plurality of pixels are arranged in a matrix of N stages × P rows and Y columns; a source driver that drives a data line connected to a source terminal of a pixel TFT provided in each pixel; In the active matrix display device including a gate driver for driving a data line connected to the gate terminal of the pixel TFT, the gate driver includes at least one shift register in each stage and includes N × P gates. An active matrix display device characterized in that an output line of the shift register in each stage is connected to the P gate input terminals in each stage and outputs a plurality of gate pulses.
(2) The active matrix display device according to (1), wherein the gate driver drives a row of pixels in descending or reverse order.
(3) The active matrix display device according to (1) or (2), wherein the gate drivers are driven in an arbitrary order.
(4) The active matrix display device according to any one of (1) to (3), wherein the gate is an AND gate.

  According to the gate driver of the present invention, it is possible to reduce the number of shift registers of the gate driver that have been redundant so far, the layout can be reduced, the active matrix display device can be downsized, and the display frame can be narrowed. Can be realized.

  In addition to the normal descending and ascending order driving, it is possible to realize the dancing scan only by changing the selection order of the enable lines.

  The present invention will be described in detail based on the following examples. However, this is an exemplification, and the present invention is not limited to such examples.

  As shown in FIG. 1, the output line 13 of the shift register 11 in each stage is connected to the input terminals of four AND gates 15a, 15b, 15c and 15d. Individual enable lines 14a, 14b, 14c and 14d are connected to the other input terminal of each AND gate. The output terminals of the AND gates 15a, 15b, 15c and 15d are connected to the buffer circuits 16a, 16b, 16c and 16d, respectively. The buffer output lines are connected to gate lines 17a, 17b, 17c and 17d, respectively. The shift register 11 receives the carry signal 12 from the previous section. Here, if the shift register 11 is in an active state, one terminal of each AND gate in this section is at the HI level. Therefore, when the enable line is at the HI level, the gate line 17 is activated through the buffer. . When rice pulses are input in the order of 14a, 14b, 14c and 14d, the gate lines are selected in the order of 17a, 17b, 17c and 17d. Thereafter, a clock is input to the shift register, and driving of this section is completed.

  In the above embodiment, the case where the gate is an AND gate is shown. However, it is obvious that the present invention can be applied to another gate, for example, a NOR gate.

  In the above embodiment, the driving order of the enable lines is either descending order or ascending order. However, the driving order of a plurality of gate lines can be changed within a section, and the driving order is changed within adjacent sections. Thus, a dancing scan can also be realized.

  In the above embodiment, the gate is an AND gate, but it is obvious that another gate, for example, a NOR gate may be used.

An example of the gate driver of the active matrix display device of the present invention is shown. An example of a gate driver of a conventional active matrix display device is shown. The block diagram of the conventional active matrix type liquid crystal display device is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Gate driver 3 Source driver 4 Signal processing circuit 11 Shift register 12 Carry input line 13 Shift register output line 14a Enable line 14b Enable line 14c Enable line 14d Enable line 15a AND gate 15b AND gate 15c AND gate 15d AND gate 16a Gate buffer 16b Gate buffer 16c Gate buffer 16d Gate buffer 17a Gate output line 17b Gate output line 17c Gate output line 17d Gate output line 22a Shift register 22b Shift register 22c Shift register 22d Shift register 25a AND gate 25b AND gate 26c AND gate 26d AND Gate 30 Pixel electrode 31 Scanning signal line 32 Data signal line 33 Switching element 34 Counter electrode

Claims (4)

A pixel matrix in which a plurality of pixels are arranged in a matrix of N stages × P rows and Y columns; a source driver that drives a data line connected to a source terminal of the pixel TFT provided in each pixel; and the pixel TFT In the active matrix display device including a gate driver for driving a data line connected to a gate terminal of each of the plurality of gate terminals, the gate driver includes at least one shift register in each stage, includes N × P gates, An active matrix display device characterized in that an output line of a shift register in a stage is connected to the P gate input terminals in each stage and outputs a plurality of gate pulses. 2. The active matrix display device according to claim 1, wherein the gate driver drives a row of pixels in descending order or reverse order. The active matrix display device according to claim 1, wherein the gate drivers are driven in an arbitrary order. 4. The active matrix display device according to claim 1, wherein the gate is an AND gate.

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