JP2008135117A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which operation can be performed by only one test result output terminal even when a plurality of memories having different specifications one another, in a one chip type semiconductor device which mounts a memory and can perform a self test of the memory. <P>SOLUTION: A plurality of test circuits 51 to 54 are provided corresponding to each of a plurality of memories 41 to 44 having different specifications one another. A logical circuit selecting one test result out of test result signals 21 to 24 of the plurality of test circuits 41 to 54 is provided. Thereby, test results of respective memories can be output to the outside by only one external output terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a one-chip semiconductor device, and more particularly to a self-test technique for a plurality of memories mounted on one chip constituting the one-chip semiconductor device.

  2. Description of the Related Art BIST (built-in self-test) technology is known as one of testability technologies for semiconductor devices, particularly LSIs (large-scale integrated circuits). BIST includes, for example, a logic BIST for testing a logic circuit, a memory BIST for testing a memory block, and the like. Generally, a BIST circuit incorporated in a semiconductor device holds a test result expected value for each test pattern in advance. The BIST circuit has a function of sequentially giving the generated test pattern to the test target circuit block and comparing the output returned from the test target circuit block with the corresponding test result expected value each time.

As an example of the prior art of BIST, there is the following (see Patent Document 1). This BIST circuit is incorporated in a semiconductor device having a plurality of memory blocks. The BIST circuit includes a test control circuit, a memory input selector, a memory output selector, and a pattern comparator. The memory input selector switches between a memory input during normal operation and a memory input during testing. This memory input selector switching operation enables test signal input to each memory block. Further, the expected value comparison for each memory block can be sequentially executed by a single pattern comparator by the selection operation of the memory output selector.
Japanese Patent Laid-Open No. 2001-184900 (particularly FIGS. 3 and 4)

  However, the BIST circuit described in Patent Document 1 is applied when a plurality of memory blocks mounted on one chip all have the same specifications. Therefore, when a plurality of memory blocks mounted on one chip are two or more different types of memory blocks, the BIST circuit described in Patent Document 1 cannot be used.

  In recent years, a semiconductor device is often configured by mounting a large number of memories having different specifications on one chip. In a semiconductor device in which a plurality of memory blocks having different specifications are mounted on one chip, a plurality of BIST circuits having different specifications are incorporated corresponding to the memory blocks having different specifications. For this reason, the control signal and test result signal of the memory BIST circuit also increase by the number of memories having different specifications.

  As variations of specifications, for example, in addition to variations in storage capacity, there are functional variations such as 1-port SRAM, 2-port SRAM, EDO type DRAM, and SRAM interface DRAM. In order to cope with memories having different specifications, the types of memory BISTs also increase. When the number of types of memory BIST increases, there is a problem that the number of external output terminals of the test result increases accordingly.

  When there are a plurality of test output external output terminals, it is necessary to individually connect the input terminals of the monitor device to the plurality of test result external output terminals. For this reason, as the memory mounted on one chip is diversified, there is a problem that labor and time required for monitoring the test result increase.

  The present invention has been made in view of such circumstances, and even in the case where a plurality of memories having different specifications are mounted in a one-chip semiconductor device in which a memory is mounted and a self-test of the memory can be performed. An object of the present invention is to provide a semiconductor device capable of having only one external output terminal.

A semiconductor device according to the present invention includes:
A one-chip semiconductor device having a memory and capable of performing a self-test of the memory,
Multiple memories,
A plurality of self-test circuits for respectively testing the plurality of memories;
A selection circuit connected to the plurality of self-test circuits, selecting a test result for one memory from a plurality of test results obtained by the plurality of self-test circuits, and outputting the test result; Prepare.

  According to the present invention, the selection circuit selects a test result for one memory from a plurality of test results obtained by the plurality of self-test circuits, and outputs the test result. Therefore, even if multiple memories with different specifications are installed in a single-chip semiconductor device that has a memory and can perform the self-test of the above memory, only one test result external output terminal is required. be able to.

In the present invention,
The plurality of memories are preferably memories having different specifications of at least two kinds.

In the present invention,
Each of the plurality of self-test circuits performs a test of the memory when receiving a test instruction of the corresponding memory,
It is preferable that the selection circuit sequentially outputs the test results of the memory that has received the test instruction.

  According to this configuration, the selection circuit sequentially outputs the test results of the memory that has received the test instruction. Therefore, it is possible to automatically and sequentially obtain test results for the memory that has received the test instruction.

In the present invention,
The self-test circuit
Including a test end signal output unit for outputting a test end signal when the corresponding memory test is completed,
The selection circuit is
When the test end signal is detected for all the memories, it is preferable to sequentially output the test results for all the memories.

  According to this configuration, when the selection circuit detects a test end signal for all the memories, the test results for all the memories are sequentially output. Therefore, test results for all memories can be automatically and sequentially acquired.

The semiconductor device according to the present invention is
A one-chip semiconductor device having a memory and capable of performing a self-test of the memory,
Multiple memories,
A plurality of self-test circuits for respectively testing the plurality of memories;
A logical product circuit connected to the plurality of self-test circuits, calculating a logical product of a plurality of test results obtained by the plurality of self-test circuits, and outputting the logical product;

  According to the present invention, the logical product circuit calculates a logical product of a plurality of test results obtained by the plurality of self-test circuits, and outputs the logical product. Therefore, even when a plurality of memories having different specifications are mounted in a one-chip type semiconductor device in which a memory is mounted and the memory self-test can be executed, only one test result output terminal can be used. Also, macro test results for a plurality of memories can be acquired.

In the present invention,
The plurality of memories are preferably memories having different specifications of at least two kinds.

In the present invention,
Each of the plurality of self-test circuits is
When the corresponding memory test instruction is received, the memory is tested,
Preferably, the logical product circuit calculates a logical product of a plurality of test results obtained for a plurality of memories that have received the test instruction.

  According to this configuration, the logical product circuit calculates the logical product of the plurality of test results obtained for the plurality of memories that have received the test instruction. Therefore, the logical product of the test results for a plurality of memories that have received the test instruction can be acquired as a macro test result.

The semiconductor device according to the present invention is
A one-chip semiconductor device having a memory and capable of performing a self-test of the memory,
Multiple memories,
A plurality of self-test circuits for respectively testing the plurality of memories;
A selection circuit connected to the plurality of self test circuits, selecting a test result for one memory from a plurality of test results obtained by the plurality of self test circuits, and outputting the test result;
A logical product circuit connected to the plurality of self-test circuits, calculating a logical product of a plurality of test results obtained by the plurality of self-test circuits, and outputting the logical product;

  According to the present invention, the selection circuit selects a test result for one memory from a plurality of test results obtained by the plurality of self-test circuits, and outputs the test result. The logical product circuit calculates a logical product of a plurality of test results obtained by the plurality of self-test circuits and outputs the logical product. Therefore, even when a plurality of memories having different specifications are mounted in a one-chip semiconductor device that has a memory and can perform a self-test of the memory, only one test result external output terminal can be used. . It is also possible to acquire both individual test results for each memory and macro test results for a plurality of memories.

  According to the present invention, in a one-chip type semiconductor device equipped with a memory and capable of executing the self-test of the memory, even if the device is equipped with a plurality of memories having different specifications, the test result One external output terminal can be used.

  Therefore, the one-chip type semiconductor device can be reduced in size. Further, when testing a plurality of memories having different specifications, the test result of each memory can be monitored through one output terminal. Therefore, the test result can be easily monitored, and the time and labor required for monitoring can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a one-chip type semiconductor device 100 (hereinafter referred to as a semiconductor device 100) according to the first embodiment.

  First, a schematic configuration of the semiconductor device 100 will be described.

  The semiconductor device 100 is a one-chip type semiconductor device in which elements such as a CPU and a memory are mounted on one chip.

  As shown in FIG. 1, the semiconductor device 100 is a semiconductor device in which a plurality of memories 41, 42, 43, 44 are mounted and a self test of these memories 41, 42, 43, 44 can be executed.

  The semiconductor device 100 includes a plurality of memories 41, 42, 43, 44, a plurality of self-test circuits 51, 52, 53, 54, a selection circuit 61-1, and an AND circuit 61-2. ing. The selection circuit 61-1 and the logical product circuit 61-2 are components of the logic circuit 61. In the first embodiment, illustration and description of a CPU and the like that are mounted on the semiconductor device 100 and are not directly related to the present embodiment are omitted.

  The types of the plurality of memories 41, 42, 43, 44 are not particularly limited. The plurality of memories 41, 42, 43, and 44 may have different specifications or the same specifications. In the following description, it is assumed that the plurality of memories 41, 42, 43, and 44 have different specifications.

  In the first embodiment, the first memory 41 is a 1-port SRAM (Static Random Access Memory). The second memory 42 is a 2-port SRAM. The third memory 43 is a DRAM (Dynamic Random Access Memory) in which one memory operation is completed in one clock, that is, a one-clock specification DRAM. The fourth memory 44 is a DRAM that completes one memory operation in three clocks, that is, a three-clock specification DRAM.

  The plurality of self-test circuits 51, 52, 53, 54 test the plurality of memories 41, 42, 43, 44, respectively. In FIG. 1, the self-test circuits 51 and 52 are denoted as SRAM-BIST 51 and SRAM-BIST 52, respectively. In FIG. 1, the self-test circuits 53 and 54 are represented as 1CLK DRAM-BIST 53 and 3CLK DRAM-BIST 54, respectively.

  Each of the plurality of self-test circuits 51, 52, 53, 54 includes a test end signal output unit (not shown) that outputs a test end signal when the test of the corresponding memory 41, 42, 43, 44 is completed. Yes. The self-test circuits 51, 52, 53, and 54 can test the memories when receiving test instructions for the corresponding memories 41, 42, 43, and 44, respectively. The test instruction can be made based on, for example, enable signals input from a plurality of enable signal input terminals 11, 12, 13, and 14.

  The selection circuit 61-1 is connected to a plurality of self-test circuits 51, 52, 53, and 54. The selection circuit 61-1 selects a test result for one memory from the plurality of test results obtained by the plurality of self-test circuits 51, 52, 53, and outputs the test result. The test result is output from the test result output terminal 25 to the outside of the semiconductor device 100.

  Note that “selecting a test result for one memory” here means that the test results of each memory are individually output in time series. That is, the test result for one memory may be output at each moment when the test result is output externally. The test result for which memory is selected can be changed over time by a test result selection signal arbitrarily given from the outside when monitoring the test result.

  In order to instruct which memory and which memory test result is to be output, a plurality of memories are selected in advance by inputting a test result selection signal, and the test results for the selected plurality of memories are displayed. It can also be configured to output sequentially.

  When a logical product of test results to be described later is output to the outside, it is possible to select test results for two or more memories in order to instruct which memory and which memory the test result logical product is to be output. It is also possible to configure.

  The AND circuit 61-2 is connected to a plurality of self-test circuits 51, 52, 53, and 54. The logical product circuit 61-2 calculates the logical product of the plurality of test results obtained by the plurality of self-test circuits 51, 52, 53, and 54, and outputs the logical product. The test result is output to the outside of the semiconductor device 100 via the test result output terminal 25. The output of the selection circuit 61-1 and the output of the logical product circuit 61-2 are output to the outside through one common output terminal 25.

  The semiconductor device 100 includes a plurality of program input terminals 1, 2, 3, and 4. The program input terminals 1, 2, 3, 4 are terminals for inputting program codes to be supplied to the corresponding self test circuit among the plurality of self test circuits 51, 52, 53, 54 from the outside in parallel.

  The semiconductor device 100 includes a plurality of enable signal input terminals 11, 12, 13, and 14. The enable signal input terminals 11, 12, 13, 14 receive an enable signal for operating the corresponding self test circuit among the plurality of self test circuits 51, 52, 53, 54 from the outside.

  Test result signals 21, 22, 23, and 24 of the plurality of memories 41, 42, 43, and 44 are input to the logic circuit 61 from the plurality of self-test circuits 51, 52, 53, and 54, respectively.

  Test end signals 31, 32, 33, and 34 of the plurality of memories 41, 42, 43, and 44 are input to the logic circuit 61 from the plurality of self-test circuits 51, 52, 53, and 54, respectively.

  The semiconductor device 100 includes the test result output terminal 25 as described above. The test result output terminal 25 includes an enable signal input from a plurality of enable signal input terminals 11, 12, 13, and 14 and a test result signal 21 input from a plurality of self-test circuits 51, 52, 53, and 54. 22, 23, 24, and test end signals 31, 32, 33, 34 are terminals for outputting monitor test result signals.

  The logic circuit 61 includes a plurality of enable signals from a plurality of enable signal input terminals 11, 12, 13, and 14, and a plurality of test result signals 21, 22, 23, and 24 from a plurality of self-test circuits 51, 52, 53, and 54. And a plurality of test end signals 31, 32, 33 and 34, an individual selection / AND result switching signal from the individual selection / AND result switching terminal 62, and a test result selection signal from the test result selection terminals 63 and 64, respectively. The logic circuit 61 outputs a monitor test result signal from the test result output terminal 25 and a monitor test end signal from the test end signal output terminal 35, respectively.

  FIG. 2 is a block diagram showing a detailed configuration of the logic circuit 61 shown in FIG. In FIG. 2, the reference numeral of the logic circuit is 610 for convenience.

  The logic circuit 610 includes a plurality of selectors 63-1,... 63-1, 63-2,... 63-2, a plurality of AND gates 64-1, 64-2, and a plurality of OR gates 65-1. .. 65-1, 65-2... 65-2, a plurality of inverters (NOT gates) 66... 66, and a logic operation circuit 67 are included. The plurality of selectors 63-2 to 63-2 correspond to the selection circuit 61-1 in FIG. The AND gate 64-2 corresponds to the AND circuit 61-2 in FIG.

  The logical operation circuit 67 selects the selector 63-1 based on the enable signals input from the plurality of enable signal input terminals 11, 12, 13, and 14 and the test result selection signals input from the test result selection terminals 63 and 64. ... 63-1, 63-2... 63-2 are controlled.

  The logic circuit 610 is provided with a plurality of input terminals and output terminals. Among these input terminals and output terminals, the individual selection / AND result switching terminal 62, the test result selection terminals 63 and 64, the test result output terminal 25, and the test end signal output terminal 35 are semiconductors as shown in FIG. An external input terminal or an external output terminal of the device 100.

  The individual selection / AND result switching terminal 62 selects one test result from the test results obtained from the plurality of self-test circuits 51, 52, 53, 54, and outputs the selected test result, This is a terminal for calculating a logical product of the test results obtained from the self-test circuits 51, 52, 53, and 54 and inputting a switching signal for switching whether to output the logical product from the outside.

  The test result selection terminals 63 and 64 are terminals for inputting a test result selection signal for selecting which test result is selected from among the test results obtained from the plurality of self-test circuits 51, 52, 53 and 54 and outputting the test result. It is.

  Hereinafter, the operation of the logic circuit 610 will be described.

  As a first operation example, a case where a test is performed only on the memory 41 will be described as an example.

  First, the enable signal from the enable signal input terminal 11 corresponding to the memory 41 and the enable signal from the enable signal input terminal 13 corresponding to the memory 43 are set to logic-H level. As a result, the self-test circuits 51 and 53 are activated. The specifications of the memory 41 and the memory 43 are different. Therefore, the self test circuit 51 and the self test circuit 53 have different test times. For this reason, the test result is monitored according to the memory having a long test time.

  When monitoring only the test result of the memory 41, the individual selection / AND result switching signal from the individual selection / AND result switching terminal 62 is set to logic-L level. In addition, a selection signal for selecting a test result in the memory 41 is input to the test result selection terminals 63 and 64. By inputting a digital signal to each of the test result selection terminals 63 and 64, four types of selection can be made. Therefore, a selection signal for selecting a test result in the memory 41 can be input to the test result selection terminals 63 and 64.

  When a selection signal for selecting a test result in the memory 41 is input to the test result selection terminals 63 and 64, a plurality of AND gates 64-1, 64-2, a plurality of OR gates 65-1,. 2 ... 65-2, a plurality of inverters 66 ... 66, a logical operation circuit 67, and a plurality of selectors 63-1 ... 63-1, 63-2 ... 63-2 in combination. Thus, a monitor test result signal and a monitor test end signal are generated. The test result signal for monitoring is output from the test result output terminal 25 to the outside. When the selection signal for selecting the test result of the memory 41 is input to the test result selection terminals 63 and 64, the monitor test result signal is the test result signal of the memory 41.

  The monitor test end signal is output from the test end signal output terminal 35 to the outside. When a selection signal for selecting a test result in the memory 41 is input to the test result selection terminals 63 and 64, the monitor test end signal is a test end signal for the memory 41.

  The monitor test result signal and the monitor test end signal are input to a monitoring device (not shown) and used to determine whether the memory 41 is good or bad.

  Next, as a second operation example, a case where only the memory 41 and the memory 43 are tested will be described as an example. Here, a case where the logical product of the test result of the memory 41 and the test result of the memory 43 is monitored will be described as an example.

  In this case, first, the individual selection / AND result switching signal from the individual selection / AND result switching terminal 62 is set to the logic-H level.

  As a result, the logical product of the test result signals (digital values) 21, 22, 23, and 24 of the plurality of memories 41, 42, 43, and 44 is output from the test result output terminal 25 to the outside as the monitor test result signal. . Here, the enable signal input from the enable signal input terminals 12 and 14 is at the logic-L level. In this case, the inverters (NOT gates) 66... 66 and the OR gates 65-2... 66 and the OR gates 65-2 and so that the test result signals 72 and 74 (see FIG. 2) for the memories 42 and 44 are forcibly set to "H" level.・ ・ The logic is organized by 65-2. For this reason, the logical product signal of the test result signal 21 of the memory 41 and the test result signal 23 of the memory 43 is output from the test result output terminal 25 as a monitor test result signal. The test result signals 72 and 74 are signals corresponding to the memories 42 and 44 among the signals 71, 72, 73, and 74 output from the OR gates 65-2 to 65-2.

  As described above, based on the individual selection / AND result switching signal from the individual selection / AND result switching terminal 62 and the test result selection signal from the test result selection terminals 63 and 64, the following switching operation is possible. That is, one test result is selected from the test results of the plurality of memories 41, 42, 43, and 44, and the selected test result is individually output from one output terminal 25, or a plurality of memories to be monitored are selected. Whether to output a logical product (AND logic) signal of the test results can be switched.

  In the above example, the test results are monitored only for a part of the memories, but the present embodiment is not limited to this example. For example, the test results for all memories may be monitored sequentially. Further, a logical product of test results for all memories may be calculated and the logical product may be output. Alternatively, the logical product of the test results for all the memories may be output, and then the test results for each memory may be output individually.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to the drawings. The second embodiment differs from the first embodiment in the specific configuration of the logic circuit 61 shown in FIG.

  FIG. 3 is a diagram showing another configuration example of the logic circuit 61 in FIG. For convenience, the reference numeral of the logic circuit shown in FIG. In addition, about the structure same as 1st Embodiment, the same referential mark is attached | subjected and the description is abbreviate | omitted suitably.

  This logic circuit 611 includes a plurality of D-flip flops 67-1 ... 67-1, 67-2 ... 67-2, a plurality of inverters 69 ... 69, and a plurality of selectors 63 ... 63 and a plurality of AND gates 81-1 and 81-2. The AND gate 81-2 corresponds to the AND circuit 61-2 in FIG.

  The AND gate 81-1 receives the test result end signals 31, 32, 33, and 34 from the memories 41, 42, 43, and 44, and outputs a logical product signal 68 of the test result end signals 31, 32, 33, and 34 as D−. Output to flip-flops 67-2 to 67-2.

  The selector 63 inputs the test result signals 21, 22, 23, and 24 of the memories 41, 42, 43, and 44 and the signals from the D-flip flops 67-2 to 67-2. The selector 63 sequentially outputs the test result signals of the memories 41, 42, 43, and 44 as monitor test result signals in accordance with the signals from the D flip-flops 67-2... 67-2. The logical product signal of each memory 41, 42, 43, 44 is output.

  The operation of the logic circuit 611 configured as described above will be described.

  Here, a case where the test results of all the memories 41, 42, 43, and 44 are monitored will be described as an example.

  Since the memories 41, 42, 43, and 44 have different specifications, the time required for the test also differs. For this reason, the test result is monitored according to the memory having a long test time.

  In the logic circuit 611, the test is completed for all the memories 41, 42, 43, and 44, so that the logical product signal 68 becomes logic-H level. When the logical product signal 68 becomes logic-H level, the reset of the D-flip flops 67-1 to 67-1, 67-2 to 67-2 is released.

  FIG. 4 is a timing chart showing the operation of the logic circuit 611 shown in FIG.

  The clock periods after the logical product signal 68 changes to the logic-H level are T1, T2, T3, T4, and T5 for each clock.

  The BIST_DONE signal in FIG. 4 means the logical product signal 68. FIG. 4 shows that the level has changed to the logic-H level immediately before the period T1.

  Reference numerals A, B, C, and D in FIG. 4 correspond to the signals A, B, C, and D in FIG. That is, since the signals A, B, C, and D are all “0”, that is, “L” level in the period T 1 in FIG. 4, the test result signal 21 of the memory 41 is output from the test result output terminal 25. In the period T2, since the signals A and D are both “0” and the signals B and C are both “1”, the test result signal 22 of the memory 42 is output from the test result output terminal 25. In the period T3, since the signals B, C, and D are all “0” and the signal A is “1”, the test result signal 23 of the memory 43 is output from the test result output terminal 25. Since the signal D is “0” and the signals A, B, and C are all “1” in the period T4, the test result signal 24 of the memory 44 is output from the test result output terminal 25. Since the signal D is “1” after the period T5, the logical product of the test result signals of all the memories 41, 42, 43, 44 is output from the test result output terminal 25.

  Therefore, it is possible to monitor the test result signal 21 in the memory 41 during the period T1. In the period T2, the test result signal 22 in the memory 42 can be monitored. In the period T3, the test result signal 23 in the memory 43 can be monitored. In the period T4, the test result signal 24 in the memory 44 can be monitored. After the period T5, it is possible to monitor the logical product of the test result signals of all the memories 41, 42, 43, and 44. By monitoring the logical product of the test result signals of all the memories 41, 42, 43, 44, it is possible to detect that at least one of the memories 41, 42, 43, 44 is defective. . That is, the macro test result can be monitored.

  Thereby, after the test of all the memories 41, 42, 43, 44 is completed, the individual test results of the respective memories 41, 42, 43, 44 and the macro test results of all the memories are monitored sequentially in synchronization with the clock signal. Is possible. Therefore, not only the PASS / FAIL of the semiconductor device 100 but also which memory is defective can be determined through one external output terminal 25. Accordingly, the ease of analysis of the memory test result is also improved.

  The semiconductor device according to the present invention is useful for reducing the number of output terminals of a one-chip type semiconductor device equipped with a memory BIST circuit, facilitating monitoring of a memory test result, improving ease of analysis, and the like.

1 is a block diagram showing a configuration example of a one-chip semiconductor device according to the present invention. 1 is a circuit diagram showing a first configuration example of a logic circuit in FIG. 1 (first embodiment). Circuit diagram showing a second configuration example of the logic circuit in FIG. 1 (second embodiment) FIG. 3 is a timing chart showing an example of monitoring of a test result signal output from the logic circuit shown in FIG.

Explanation of symbols

1-4 Program input terminals 11-14 Enable signal input terminals 21-24 Test result signal 25 Test result output terminals 31-34 Test end signal 35 Test end signal output terminal 41 Memory (1-port SRAM)
42 memory (2 port SRAM)
43 memory (1 clock specification DRAM)
44 memory (3 clock specification DRAM)
51-54 test circuit (BIST)
61 logic circuit 61-1 selection circuit 61-2 AND circuit

Claims (8)

A one-chip semiconductor device equipped with a memory and capable of executing a self-test of the memory,
Multiple memories,
A plurality of self-test circuits for respectively testing the plurality of memories;
A selection circuit connected to the plurality of self-test circuits, selecting a test result for one memory from a plurality of test results obtained by the plurality of self-test circuits, and outputting the test result; A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the plurality of memories are at least two kinds of memories having different specifications. Each of the plurality of self-test circuits performs a test of the memory when receiving a test instruction of the corresponding memory,
The semiconductor device according to claim 1, wherein the selection circuit sequentially outputs a test result of the memory that has received the test instruction. Each of the plurality of self-test circuits is
Including a test end signal output unit for outputting a test end signal when the corresponding memory test is completed,
The selection circuit includes:
2. The semiconductor device according to claim 1, wherein when the test end signal is detected for all the memories, the test results of all the memories are sequentially output. A one-chip semiconductor device equipped with a memory and capable of executing a self-test of the memory,
Multiple memories,
A plurality of self-test circuits for respectively testing the plurality of memories;
A semiconductor device comprising: an AND circuit connected to the plurality of self-test circuits, calculating a logical product of a plurality of test results obtained by the plurality of self-test circuits, and outputting the logical product.   6. The semiconductor device according to claim 5, wherein the plurality of memories are at least two kinds of memories having different specifications. Each of the plurality of self-test circuits is
When the corresponding memory test instruction is received, the memory is tested,
6. The semiconductor device according to claim 5, wherein the logical product circuit calculates a logical product of a plurality of test results obtained for a plurality of memories that have received the test instruction. A one-chip semiconductor device equipped with a memory and capable of executing a self-test of the memory,
Multiple memories,
A plurality of self-test circuits for respectively testing the plurality of memories;
A selection circuit connected to the plurality of self-test circuits, selecting a test result for one memory from a plurality of test results obtained by the plurality of self-test circuits, and outputting the test result;
A semiconductor device comprising: an AND circuit connected to the plurality of self-test circuits, calculating a logical product of a plurality of test results obtained by the plurality of self-test circuits, and outputting the logical product.

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