JP2008130123A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device providing a desired control voltage through more proper voltage trimming. <P>SOLUTION: A parameter control circuit of the nonvolatile semiconductor memory device 100 controls a parameter register to sequentially output a plurality of parameters to a voltage generation control circuit, counts for a fixed time, oscillations of trimming flag signals which are sequentially output from the voltage generation control circuit in accordance with each parameter, stores the count value in association with each parameter, and selects a parameter having a maximum count value as a parameter corresponding to a control voltage closest to an external reference voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device that performs voltage trimming by BIST (Built-In Self-Test).

  Control voltages such as a reference voltage, a read voltage, and a write voltage of the nonvolatile semiconductor memory device have a large difference between chips. Therefore, it is necessary to adjust these voltages to target voltages before shipment.

  Conventionally, a test circuit is incorporated in the chip in order to shorten the time for such adjustment. When the tester inputs a command to the test circuit, the nonvolatile semiconductor memory device itself can automatically perform this kind of test.

  Conventionally, there is a method for adjusting a reference voltage by inputting a target voltage from the outside to the test circuit and comparing the target voltage with a voltage corresponding to an internal parameter (for example, Patent Document 1). reference).

  In the above prior art, when the adjustment is successful, the test circuit raises a completed flag (outputs a trimming flag signal) and ends the adjustment.

  On the other hand, if the adjustment is unsuccessful, the test circuit adjusts the reference voltage or the like to a value close to the external target voltage by increasing (or decreasing) the voltage corresponding to the parameter.

In the above-described prior art, if noise is added to the trimming flag signal at the timing of checking the adjustment, there is a problem that a desired control voltage cannot be obtained by deviating from the target voltage.
JP 2001-255948 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can obtain a desired control voltage by performing voltage trimming more appropriately.

A nonvolatile semiconductor memory device according to an embodiment of one aspect of the present invention includes:
A nonvolatile semiconductor memory device that sets a control voltage to be supplied to an internal circuit to an external reference voltage input from the outside,
A plurality of memory cells connected to a word line in the selected row direction and a bit line in the selected column direction and capable of storing bit information, and a memory cell array in which the memory cells are arranged in a matrix;
A row decoder connected to the word line for supplying a voltage to the word line and operating the memory cell;
A sense amplifier device connected to the bit line, for reading data stored in the memory cell, and holding the read data and data written in the memory cell;
A parameter register for storing a plurality of parameters respectively corresponding to the plurality of control voltages;
Voltage generation that generates the control voltage corresponding to the parameter input from the parameter register, compares the control voltage with the external reference voltage, and outputs a trimming flag signal according to the comparison result A control circuit;
A parameter control circuit that controls the parameter register in accordance with the trimming flag signal and causes the voltage generation control circuit to output the selected parameter; and
The parameter control circuit includes:
A plurality of the parameters are sequentially output from the parameter register to the voltage generation control circuit,
Counting the number of oscillations of the trimming flag signal sequentially output by the voltage generation control circuit corresponding to each parameter for a certain period,
Store this count value corresponding to each parameter,
The parameter that maximizes the count value is selected as a parameter corresponding to a control voltage closest to the external reference voltage.

  According to the nonvolatile semiconductor memory device of the present invention, a desired control voltage can be obtained by performing voltage trimming more appropriately.

  Embodiments according to the present invention will be described below with reference to the drawings. In the following embodiments, a case where the present invention is applied to a NAND flash memory will be described. However, the present invention can be similarly applied to a nonvolatile semiconductor memory device such as a NOR flash memory.

  FIG. 1 is a block diagram showing a main configuration of a nonvolatile semiconductor memory device 100 according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, a nonvolatile semiconductor memory device 100 includes a memory cell array 1, a row decoder 2, a sense amplifier device 3, a column decoder 4, a data input / output buffer 5, and a first input / output control circuit. 6, a control signal generation circuit 7, an address decoder 8, a voltage generation control circuit 9, a parameter control circuit 10, a parameter register 11, and a synchronous clock generation circuit 12.

  The row decoder 2 is connected to the word line. The row decoder 2 includes a word line driving circuit (not shown), and performs word line selection and driving of the memory cell array 1.

  The sense amplifier device 3 is connected to the bit line of the memory cell array 1, reads data stored in the memory cell, and holds the read data and data written in the memory cell.

  The column decoder 4 performs bit line selection of the memory cell array 1.

  At the time of data reading, the data read by the sense amplifier device 3 is output to the first input / output control circuit 6 via the data input / output buffer 5.

  The input / output control circuit 6 supplies a command to the control signal generation circuit 7 via the data input / output buffer 5. The control signal generation circuit 7 decodes this command.

  The control signal generation circuit 7 is supplied with external control signals such as a chip enable signal CE, a write enable signal WE, a read enable signal RE, an address latch enable signal ALE, and a command latch enable signal CLE.

  The control signal generation circuit 7 performs data write / erase sequence control and data read control based on an external control signal and command supplied in accordance with the operation mode.

  The control signal generation circuit 7 outputs a signal for controlling various operations such as reading, writing, and erasing. As a result, the voltage generation control circuit 9 generates control voltages for various operations.

  The address of the memory cell is supplied from the input / output control circuit 6 via the data input / output buffer 5. This address is transferred to the word line control circuit 2 and the column decoder 4 via the address decoder 8.

  The parameter register 10 stores a plurality of parameters respectively corresponding to a plurality of control voltages. These parameters are used to compensate for variations in the control voltage for each chip, as will be described later.

  Here, the voltage generation control circuit 9 generates the control voltage corresponding to the parameter input from the parameter register 11. The voltage generation control circuit 9 compares the control voltage with the external reference voltage and outputs a trimming flag signal according to the comparison result.

  The parameter control circuit 11 performs a trimming test for determining parameters before shipment of the nonvolatile semiconductor memory device 100. In this trimming test, a control voltage corresponding to a parameter stored in the parameter register 11 is set in the voltage generation control circuit 9 to test whether the control voltage generated by the voltage generation control circuit 9 is close to the external reference voltage. To do. The parameter control circuit 11 controls the parameter register 10 in accordance with the trimming flag signal and causes the voltage generation control circuit 9 to output the selected parameter.

  Here, FIG. 2 is a diagram illustrating timing waveforms of the trimming flag signal output from the voltage generation control circuit of the nonvolatile semiconductor memory device according to the first embodiment and the counter value counted by the parameter control circuit.

  As shown in FIG. 2, the parameter control circuit 11 determines the number of oscillations of the trimming flag signal sequentially output by the voltage generation control circuit 9 corresponding to each parameter (here, a change from “High” to “Low”). Each counts for a certain period. The parameter control circuit 11 stores the count value corresponding to each parameter.

  FIG. 3 is a circuit diagram including a main configuration of the memory cell array 1 of FIG.

  As shown in FIG. 3, the memory cell array 1 is connected to word lines WL1 to WL31 in the selected row direction and bit lines BL0 to BL2n + 1 (n is an integer of 0 or more) in the selected column direction, and arranged in a matrix. And a plurality of memory cells (NAND cells) 1a.

In this memory cell 1a, information of different x bits (x is an integer of 2 or more) is stored corresponding to 2 ^x threshold voltages. Then, by applying a read voltage to the word lines WL1 to WL31, information of each x bit can be read from the memory cell 1a. That is, the memory cell 1a is multi-valued.

  In addition, the memory cell array 1 includes a selection gate transistor 1b that connects the source line SRC and the memory cell 1a. The selection gate transistor 1b is controlled by connecting a source side selection gate line SGS to the gate and applying a voltage from the row decoder 2 to the source side selection gate line SGS.

  The memory cell array 1 further includes a selection gate transistor 1c that connects the bit lines BL0 to BL2n + 1 and the memory cell 1a. The selection gate transistor 1c is controlled by connecting a drain side selection gate line SGD to the gate and applying a voltage from the row decoder 2 to the drain side selection gate line SGD.

  The memory cell 1a is connected in series between the source side select gate line SGS and the drain side select gate line SGD.

  By applying voltages from the word lines WL0 to WL31 connected to the row decoder 2 to the memory cells 1a and the gates of the select gate transistors 1b and 1c in each memory cell array 1, the write operation and the read operation are controlled. As described above, the row decoder 2 supplies voltages to the word lines WL0 to WL31 to operate the memory cells.

  The sense amplifier device 3 has n sense amplifier circuits 3a. Each sense amplifier circuit 3a is connected to the data input / output buffer 5 via each column selection gate 1d. These column selection gates 1d are controlled by column selection signals CSL0 to CSLn. A pair of bit lines (for example, bit lines BL0 and BL1) are connected to each sense amplifier circuit 3a.

  The sense amplifier circuit 3 a performs control in the column direction of the memory cell array 1. Specifically, the sense amplifier circuit 3a performs write control and read operation by charging the bit lines BL0 to BL2n + 1.

  The block 1e includes the plurality of memory cells 1a described above arranged between the source side select gate line SGS and the drain side select gate line SGD. Data is erased in units of blocks.

  The sector 1f is connected to the same word line (for example, the word line WL31), and is composed of memory cells 1a that are simultaneously written and read. In this sector 1f, data for x pages (for example, 3 pages in the case of 3 bits) is stored.

  Next, the bit allocation for each threshold voltage of the memory cell of the nonvolatile semiconductor memory device 100 that performs the above-described configuration and basic operation will be described.

  As described above, the nonvolatile semiconductor memory device 100 can store a plurality of bit information in the memory cell 1a due to a difference in threshold voltage. Here, in the read operation, a read voltage is applied to a single word line in the same procedure with respect to one sector 1f. Then, signals are input from the bit lines in the same procedure by all n sense amplifier circuits 3a. This signal is processed by the sense amplifier circuit 3a, and a set of data corresponding to one page is collectively read in the column direction.

  Next, the trimming test operation of the nonvolatile semiconductor memory device 100 having the above configuration will be described.

  FIG. 4 is a flowchart illustrating the trimming test operation of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 5 is a diagram showing the relationship among parameters, control voltages, and counter values obtained by the trimming test operation of FIG.

  Here, when the analog voltage comparison between the control voltage and the external reference voltage is performed as in the above-described prior art, if the control voltage and the external reference voltage are balanced, the flag indicating the comparison result due to noise The possibility that the signal oscillates increases, and an appropriate value may not be trimmed due to erroneous latching of the comparison result.

  Therefore, in this embodiment, the control voltage corresponding to the case where the oscillation of the comparison result is the largest is considered to be closest to the external reference voltage. Thus, the number of times of oscillation due to noise is counted, and the parameter corresponding to the control voltage with the largest number of oscillations (maximum value of the number of oscillations count) is set in the voltage generation control circuit as the trimming parameter trim_param that has been trimmed. Thus, more appropriate voltage trimming is performed than in the prior art.

  In the present embodiment, a case will be described in which the voltage generation control circuit 9 outputs a trimming flag signal whose signal state is “High” when the control voltage is larger than the external reference voltage. Note that when the control voltage is higher than the external reference voltage, the state of the trimming flag signal may be “Low”.

  Further, as shown in FIG. 5, the parameter register 10 stores parameters P1 to P7 corresponding to the control voltages V1 to V7. In addition, it is assumed that the control voltages V1, V2,...

  The trimming test is started by inputting a reference external reference voltage from the external reference voltage input 13 to the voltage generation control circuit 9.

  First, as shown in FIG. 4, the parameter control circuit 11 causes the parameter register 10 to output the parameter P1 (the parameter to be trimmed first) corresponding to the lowest control voltage V1 from the parameter register 10. Further, the parameter control circuit 11 sets the maximum counter value max_cnt to 1 and the current counter value cnt to 0 as an initial state (step S1).

  Next, the voltage generation control circuit 9 compares the external reference voltage and the control voltage V1, and outputs a trimming flag signal (step S2). That is, the voltage generation control circuit 9 outputs a trimming flag signal whose signal state is “High” when the control voltage is larger than the external reference voltage, and when the control voltage is smaller than the external reference voltage, A trimming flag signal whose signal state is “Low” is output.

  Next, the parameter control circuit 11 counts the number of oscillations of the trimming flag signal output from the voltage generation control circuit 9 corresponding to the parameter P1, and obtains and stores the counter value cnt. Then, the parameter control circuit 11 compares the counter value cnt with the current maximum counter value max_cnt = 1 (step S3).

  If the counter value cnt is larger than the current maximum counter value max_cnt, the current parameter (here P1) is set to the trimming parameter trim_param (step S4).

  After step S4, the parameter control circuit 11 determines whether or not the trimming test has been tried for all the parameters stored in the parameter register 10 (step S5).

  On the other hand, when the counter value cnt is equal to or smaller than the current maximum counter value max_cnt in step S3, the process proceeds to step S5.

  Since there are untried parameters (P2 to P7) in the parameter register 10 other than the parameter P1, the process proceeds to step S6, where the parameter control circuit 11 sets the parameter P2 corresponding to the next lower control voltage V2 to the parameter The voltage is output from the register 10 to the voltage generation control circuit 9. Further, the parameter control circuit 11 sets the current counter value cnt to 0. Then, returning to step S2, the voltage generation control circuit 9 compares the external reference voltage and the control voltage V2, and outputs a trimming flag signal. The subsequent steps are similarly performed for the parameters P2 to P7.

  On the other hand, when the parameter control circuit 11 determines in step S5 that the trimming test has been attempted for all the parameters P1 to P7 stored in the parameter register 10, the flow ends. At this time, a parameter corresponding to the maximum counter value max_cnt finally obtained is obtained as the trimming parameter trim_param.

  In this way, the parameter control circuit 11 sequentially outputs a plurality of parameters from the parameter register 10 to the voltage generation control circuit 9 (steps S2, S3, S4, S5, S6), and the voltage generation control circuit corresponding to each parameter. The number of oscillations of the trimming flag signal sequentially output by 9 is counted for a certain period of time (steps SS2, S3). The count value is stored in association with each parameter, and the parameter with the maximum count value is selected as the trimming parameter trim_param corresponding to the control voltage closest to the external reference voltage (steps S3, S4, and S5).

  Here, as shown in FIG. 5, the counter value when there is no oscillation due to noise or the like is the maximum counter value 1 when the parameters are P4 to P7. For the parameter P4, it is considered that the control voltage V4 exceeds the external reference voltage for the first time. Therefore, the control voltage V4 corresponding to the parameter P4 is obtained as the closest to the external reference voltage.

  Further, the counter values A to C when there is oscillation due to noise or the like are 10 at the parameter P4, that is, the maximum counter value. Therefore, as in the case where there is no oscillation due to noise or the like, the control voltage V4 corresponding to the parameter P4 is obtained as the closest to the external reference voltage.

  As described above, the trimming test operation performed by the nonvolatile semiconductor memory device 100 according to the present embodiment makes it possible to perform voltage trimming more appropriately to obtain a desired control voltage even when there is oscillation due to noise or the like. It turns out that it is obtained.

  As described above, the nonvolatile semiconductor memory device 100 uses the voltage generation control circuit 9, the parameter register 10, and the parameter control circuit 11 as internal circuits such as the row decoder 2, the sense amplifier device 3, and the column decoder 4. A control voltage for supply is set to an external reference voltage input from the outside.

  In this embodiment, the parameter control circuit 11 outputs a plurality of parameters from the parameter register 10 to the voltage generation control circuit 9 in the order of the parameter corresponding to the low control voltage to the parameter corresponding to the high control voltage. did. However, the parameter control circuit 11 may output a plurality of parameters from the parameter register 10 to the voltage generation control circuit 9 in the order of the parameter corresponding to the high control voltage to the parameter corresponding to the low control voltage. Alternatively, a parameter may be arbitrarily selected and a trimming test may be tried for all parameters.

  As described above, according to the nonvolatile semiconductor memory device of this example, a desired control voltage can be obtained by performing voltage trimming more appropriately.

  In the first embodiment, the configuration in which the parameter control circuit directly counts the trimming flag signal has been described.

  In this embodiment, a configuration in which the trimming flag signal is counted in synchronization with a predetermined synchronous clock signal will be described.

  FIG. 6 is a block diagram showing a main configuration of the nonvolatile semiconductor memory device 200 according to the second embodiment which is an aspect of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  As shown in FIG. 6, the nonvolatile semiconductor memory device 200 further includes a synchronous clock generation circuit 12 that outputs a synchronous clock signal to the parameter control circuit 11 as compared with the configuration of the first embodiment.

  The parameter control circuit 11 counts the oscillation of the trimming flag signal output from the voltage generation control circuit 9 for a predetermined time in synchronization with the synchronous clock signal, and obtains a count value.

  The operation of the trimming test by the nonvolatile semiconductor memory device 200 is the same as that in the first embodiment.

  FIG. 7 illustrates timing waveforms of a trimming flag signal output from the voltage generation control circuit of the nonvolatile semiconductor memory device according to the second embodiment, a synchronization clock signal output from the synchronization clock generation circuit, and a counter value counted by the parameter control circuit. FIG.

  As shown in FIG. 7, while the trimming flag signal is output, the synchronous clock generation circuit 12 generates a synchronous clock signal having an arbitrary period. The parameter control circuit 11 generates a counter clock signal that acquires the value of the trimming flag signal (“High” or “Low”) at the timing of the falling edge of the synchronous clock signal. For example, when the counter clock signal changes from “High” to “Low” or “Low” to “High”, the parameter control circuit 11 counts this change for a certain period to obtain a counter value.

  The counter value is thinned out from the counter value of the first embodiment. However, the result of the same tendency as in FIG. 5 of the first embodiment can be obtained also by the trimming test operation of the nonvolatile semiconductor memory device 200 according to the second embodiment using the counter value.

  Further, the synchronous clock signal can be executed at an arbitrary position during the trimming test period. This is to prevent a malfunction of the start-up time in the initial trimming test.

  As described above, according to the nonvolatile semiconductor memory device of this example, a desired control voltage can be obtained by performing voltage trimming more appropriately.

1 is a block diagram showing a main configuration of a nonvolatile semiconductor memory device 100 according to a first embodiment which is an aspect of the present invention. FIG. FIG. 6 is a diagram illustrating timing waveforms of a trimming flag signal output from a voltage generation control circuit and a counter value counted by a parameter control circuit of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 2 is a circuit diagram including a main configuration of the memory cell array 1 of FIG. 1. 3 is a flowchart showing a trimming test operation of the nonvolatile semiconductor memory device according to the first embodiment. It is a figure which shows the relationship between a parameter, a control voltage, and the counter value obtained by the trimming test. It is a block diagram which shows the principal part structure of the non-volatile semiconductor memory device 200 which concerns on Example 2 which is 1 aspect of this invention. FIG. 6 is a diagram illustrating timing waveforms of a trimming flag signal output from a voltage generation control circuit of a nonvolatile semiconductor memory device according to a second embodiment, a synchronization clock signal output from a synchronization clock generation circuit, and a counter value counted by a parameter control circuit. .

Explanation of symbols

1 memory cell array 2 row decoder 3 sense amplifier device 4 column decoder 5 data input / output buffer 6 input / output control circuit 7 control signal generation circuit 8 address decoder 9 voltage generation control circuit 10 parameter register 11 parameter control circuit 12 synchronous clock generation circuit 13 external Signal input 100, 200 Nonvolatile semiconductor memory device

Claims (4)

A nonvolatile semiconductor memory device that sets a control voltage to be supplied to an internal circuit to an external reference voltage input from the outside,
A plurality of memory cells connected to a word line in the selected row direction and a bit line in the selected column direction and capable of storing bit information, and a memory cell array in which the memory cells are arranged in a matrix;
A row decoder connected to the word line for supplying a voltage to the word line and operating the memory cell;
A sense amplifier device connected to the bit line, for reading data stored in the memory cell, and holding the read data and data written in the memory cell;
A parameter register for storing a plurality of parameters respectively corresponding to the plurality of control voltages;
Voltage generation that generates the control voltage corresponding to the parameter input from the parameter register, compares the control voltage with the external reference voltage, and outputs a trimming flag signal according to the comparison result A control circuit;
A parameter control circuit that controls the parameter register in accordance with the trimming flag signal and causes the voltage generation control circuit to output the selected parameter; and
The parameter control circuit includes:
A plurality of the parameters are sequentially output from the parameter register to the voltage generation control circuit,
Counting the number of oscillations of the trimming flag signal sequentially output by the voltage generation control circuit corresponding to each parameter for a certain period,
Store this count value corresponding to each parameter,
The nonvolatile semiconductor memory device, wherein the parameter that maximizes the count value is selected as a parameter corresponding to a control voltage closest to the external reference voltage. A synchronization clock generation circuit that outputs the synchronization clock signal to the parameter control circuit;
The non-volatile semiconductor memory device, wherein the parameter control circuit obtains the count value by counting oscillation of the trimming flag signal for a predetermined time in synchronization with the synchronous clock signal. The parameter control circuit outputs a plurality of the parameters from the parameter register to the voltage generation control circuit in the order of the parameter corresponding to the high control voltage from the parameter corresponding to the low control voltage. The nonvolatile semiconductor memory device according to claim 1. The parameter control circuit outputs a plurality of the parameters from the parameter register to the voltage generation control circuit in the order of the parameters corresponding to the low control voltage from the parameters corresponding to the high control voltage. The nonvolatile semiconductor memory device according to claim 1.

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