JP2008123389A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently set a transfer address while shortening overhead when a DMA transfer address is set by a DMA controller. <P>SOLUTION: A comparison part 13 compares a virtual address registered in a transfer-address conversion table 12 with a designated virtual address so as to output a hit signal when they are identical to each other. A selector 14 receives the hit signal so as to output a physical address corresponding to the virtual address. When the virtual address and the designated virtual address are not identical to each other, a search request signal is outputted from the comparison part 13. A comparison part 8 compares the designated virtual address with a virtual address of a shared address conversion table 7 so as to output a hit signal when they are identical to each other. A selector 9 outputs the virtual address after converting it to a physical address. The comparison part 13 registers the physical address and the designated virtual address into the transfer-address conversion table 12. A selector 14 outputs the retrieved physical address so as to start DMA transfer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer technique in a semiconductor integrated circuit device, and more particularly to a technique effective for DMA transfer by a DMA (Direct Memory Access) controller.

  In a semiconductor integrated circuit device, a DMA for performing DMA transfer for direct data access / control of data writing / reading without going through a central processing unit (CPU) to an externally connected semiconductor memory, internal memory, or the like. Controllers are widely used.

  A central processing unit of a semiconductor integrated circuit device operates with a virtual address. However, a bus master such as a DMA controller is connected to a physical address bus and requires conversion from a virtual address to a physical address.

  Generally, when setting a transfer destination / transfer source address of a DMA controller, conversion to a physical address is performed by software. In addition to address conversion by software, as a technique for setting the transfer destination / transfer source address of the DMA controller, a technique in which the DMA controller has an address conversion function is known.

As a transfer address setting technique by this type of DMA controller, for example, conversion information data for converting a virtual address value and a physical address value is set by a CPU at the time of system startup, and the DMA controller by the CPU at the time of DMA transfer. The virtual DMA transfer address value generated by the DMA controller from the virtual DMA transfer start address value set in the above is converted into the physical DMA transfer address value of the memory by the conversion information data by the virtual / physical address conversion unit (see Patent Document 1). The DMA controller has a memory management mechanism in the controller that is compatible with the memory management mechanism in the microprocessor, and direct memory access to the translation lookaside buffer entry in the memory management mechanism in the controller Such as those for holding the kinematic the microprocessor numbers and direct memory access end interrupt level (see Patent Document 2) are known.
Japanese Patent Laid-Open No. 05-120205 Japanese Patent Laid-Open No. 08-263426

  However, the present inventors have found that the transfer address setting technique using the DMA controller as described above has the following problems.

  In the transfer address conversion technology by software, every time a DMA transfer occurs, a calculation process for converting a virtual address into a physical address is required, and a process for setting the calculated physical address is required. There is a problem that the processing speed decreases.

  Also, when the DMA controller has an address conversion function, the conversion information must be set by software at the time of startup of the semiconductor integrated circuit device, etc. There is a problem that the startup time becomes long.

  In addition, the same address conversion information must be registered in the central processing unit and the DMA controller, respectively, which increases the burden of software, and in this case, the processing speed of the semiconductor integrated circuit device may be reduced. It will end up.

  An object of the present invention is to provide a technique capable of reducing the overhead when setting a DMA transfer address by the DMA controller and setting the transfer address efficiently.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a DMA controller that directly accesses an externally connected semiconductor memory and peripheral function module and performs data write / read control, and a plurality of peripheral modules to be accessed by the DMA controller; A central processing unit, and the DMA controller includes a transfer address conversion table in which arbitrary partial address conversion information for converting a virtual address to a physical address is registered, and a designated virtual address is the transfer address conversion table. The virtual address is converted into a physical address on the basis of the transfer address conversion table and output, and the specified virtual address is stored in the transfer address conversion table. If not registered, search to the central processing unit The central processing unit includes a shared address conversion table for converting all virtual addresses into physical addresses, and a search request signal for the address conversion control unit. Based on this, a shared address search / conversion unit comprising an address search / conversion unit that searches the shared address conversion table for a physical address that matches the specified virtual address and outputs the same to the DMA controller is provided.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device of the present invention, the address translation control unit compares the designated virtual address with the virtual address registered in the transfer address translation table, determines whether or not the addresses match, A comparison control unit that outputs a first hit signal when they match, and a search request signal when they do not match, and the virtual address based on a transfer address conversion table when the first hit signal is input. It comprises a first selection unit that converts to a corresponding physical address and outputs it.

  In the semiconductor integrated circuit device according to the present invention, when the search request signal is input, the address search conversion unit compares the specified virtual address with the virtual address of the shared address conversion table, and matches. A controller that outputs a second hit signal and a physical address corresponding to the virtual address of the searched shared address translation table based on the second hit signal output from the controller. It consists of a second selection unit.

  Furthermore, in the semiconductor integrated circuit device of the present invention, the peripheral module includes at least the semiconductor memory.

  In the semiconductor integrated circuit device of the present invention, the comparison control unit is designated as the physical address selected by the second selection unit when the designated virtual address is not registered in the transfer address conversion table. It has a function of registering the virtual address in the forwarding address conversion table.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since management of information for converting a virtual address to a physical address can be managed only by the central processing unit, the burden on software can be greatly reduced.

  (2) With the above (1), the processing speed of the semiconductor integrated circuit device can be improved.

  (3) According to the above (1), the time required for the initial setting of the semiconductor integrated circuit device can be shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a flowchart showing a processing example when a DMA transfer request from a CPU is generated in the semiconductor integrated circuit device of FIG.

  In the present embodiment, as shown in FIG. 1, the semiconductor integrated circuit device 1 includes a CPU 2, a built-in memory (semiconductor memory) 3, a plurality of peripheral IPs (Intellectual Property) 4, and a DMA controller 5.

  The CPU 2 functions as a central processing unit and manages all the controls in the semiconductor integrated circuit device 1. The built-in memory 3 that is one of the peripheral modules is composed of a volatile semiconductor memory such as a DRAM (Dynamic Random Access Memory), for example, and temporarily stores programs, data, and the like. The built-in memory 3 may be other than a volatile semiconductor memory, and may be a semiconductor memory such as a nonvolatile semiconductor memory exemplified by a flash memory.

  The peripheral IP 4 includes various peripheral modules such as a serial interface module and a timer module. The built-in memory 3 and the peripheral IP 4 are modules to be accessed such as the CPU 2 and the DMA controller 5.

  The DMA controller 5 performs control by directly accessing data transfer between any peripheral IP 4 and the built-in memory 3 without going through the CPU 2. The CPU 2, the built-in memory 3, the peripheral IP 4, and the DMA controller 5 are connected to each other via an address bus AB and a data bus DB.

  The CPU 2 is provided with a shared address search conversion unit 6. Based on the search request signal output from the DMA controller 5, the shared address search conversion unit 6 searches for a physical address that matches the virtual address specified by the CPU 2 or the like, and outputs it to the DMA controller 5.

  The shared address search conversion unit 6 includes a shared address conversion table 7, a comparison unit 8, and a selector 9. The shared address conversion table 7 is a table for converting a virtual address requested by the DMA controller 5 into a physical address.

  Based on the search request signal output from the DMA controller 5, the comparison unit 8 searches for a virtual address in the shared address translation table 7 that matches the virtual address specified by the CPU 2 or the like as the transfer address, and hits when it matches. A signal (second hit signal) is output.

  Based on the hit signal output from the comparison unit 8, the selector 9 serving as the second selection unit selects a physical address corresponding to the searched virtual address of the shared address translation table 7 and outputs it to the DMA controller 5. .

  Further, the DMA controller 5 includes a request control unit 10 and an address conversion unit 11. The request control unit 10 controls data transfer start / end based on a transfer request from the CPU 2 or the like. The request control unit 10 includes an address setting register 10a. The address setting register 10a stores a virtual address serving as a transfer source / transfer destination address designated by the CPU 2 or the like.

  The address conversion unit 11 converts a transfer address composed of a virtual address designated by the CPU 2 or the like into a physical address. The address conversion unit 11 includes a transfer address conversion table 12, a comparison unit 13, and a selector 14.

  The transfer address conversion table 12 stores a part (arbitrary information) of the shared address conversion table 7. The comparison unit 13 functioning as an address translation control unit and a comparison control unit compares the transfer address composed of the virtual address stored in the address setting register 10a of the request control unit 10 with the virtual address of the transfer address translation table 12, and matches them. When this occurs, a hit signal (first hit signal) is output to the selector 14, and when there is a mismatch, a search request signal is output to the shared address search conversion unit 6.

  The selector 14 functioning as an address translation control unit selects a physical address corresponding to the searched virtual address of the shared address translation table 7 based on the hit signal output from the comparison unit 13 and outputs the selected physical address to the address bus AB. To do.

  Next, operations in the DMA controller 5 and the shared address search conversion unit 6 of the CPU 2 according to the present embodiment will be described.

  FIG. 2 is a flowchart showing an example of processing when a DMA transfer request from the CPU 2 is generated, for example.

  First, when the CPU 2 accesses the built-in memory 3, the CPU 2 designates a virtual address as a transfer source / transfer destination address via the data bus DB. These virtual addresses are stored in the address setting register 10a.

  When the DMA transfer is started, the virtual address stored in the address setting register 10 a is output from the request control unit 10 to the address conversion unit 11. In response to this, the comparison unit 13 of the address conversion unit 11 compares the virtual addresses of all entries registered in the transfer address conversion table 12 with the virtual addresses from the request control unit 10 (step S101).

  If there is a virtual address that matches the transfer address conversion table 12 as a result of the comparison, a hit signal is output from the comparison unit 13. The selector 14 receives the hit signal, selects a physical address corresponding to the matching virtual address (step S102), outputs the physical address via the address bus AB, and starts DMA transfer (step S103).

  Further, in the process of step S101, when the matching virtual address does not exist in the forwarding address conversion table 12 as a result of the comparison, a search request signal is output from the comparison unit 13 to the shared address search conversion unit 6.

  When the search request signal is input, the shared address search translation unit 6 compares the virtual address from the request control unit 10 with the virtual addresses of all entries registered in the shared address translation table 7 (step S104). Search for matching virtual addresses.

  When the search is completed, the comparison unit 8 outputs a hit signal to the selector 9. The selector 9 receives the hit signal, selects the physical address registered in the entry corresponding to the searched virtual address, and outputs it to the comparison unit 13.

  The comparison unit 13 registers the physical address output from the shared address search conversion unit 6 and the virtual address from the request control unit 10 in the transfer address conversion table 12 (step S105).

  The selector 14 outputs the physical address output from the shared address search / conversion unit 6 to the address bus AB (step S102), and DMA transfer is started (step S103).

  Thus, according to the present embodiment, when a search error occurs in the address conversion unit 11, mishandling can be performed by hardware, so that processing by software can be reduced, and the semiconductor integrated circuit device 1 The processing speed can be improved.

  Further, since the information management of the transfer address conversion table 12 registered in the DMA controller 5 is not required, the table management becomes easy and the startup time of the semiconductor integrated circuit device 1 can be shortened.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a technique for efficiently setting a transfer address by a DMA controller.

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. 3 is a flowchart showing a processing example when a DMA transfer request from a CPU is generated in the semiconductor integrated circuit device of FIG.

Explanation of symbols

1 Semiconductor Integrated Circuit Device 2 CPU 2
3 Built-in memory 4 Peripheral IP
5 DMA controller 6 Shared address search conversion unit 7 Shared address conversion table 8 Comparison unit 9 Selector 10 Request control unit 10a Address setting register 11 Address conversion unit 12 Transfer address conversion table 13 Comparison unit 14 Selector AB Address bus DB Data bus

Claims (5)

A DMA controller that directly accesses an externally connected semiconductor memory or peripheral function module and performs data write / read control;
A plurality of peripheral modules to be accessed by the DMA controller;
A central processing unit,
The DMA controller
A transfer address conversion table in which any part of address conversion information for converting a virtual address to a physical address is registered;
It searches whether or not the specified virtual address is registered in the transfer address conversion table. When registered, the virtual address is converted into a physical address based on the transfer address conversion table, and output. An address translation unit comprising an address translation control unit that outputs a search request signal to the central processing unit when the virtual address that has been registered is not registered in the transfer address translation table,
The central processing unit is
A shared address translation table that translates all virtual addresses into physical addresses;
Based on a search request signal of the address translation control unit, a shared address search comprising an address search translation unit that searches the shared address translation table for a physical address that matches the specified virtual address and outputs the physical address to the DMA controller. A semiconductor integrated circuit device comprising a conversion unit. The semiconductor integrated circuit device according to claim 1.
The address conversion control unit
The specified virtual address is compared with the virtual address registered in the forwarding address conversion table, and it is determined whether or not the addresses match. When the addresses match, the first hit signal is output. Is a comparison control unit that outputs a search request signal;
A semiconductor integrated circuit device comprising: a first selection unit that converts the virtual address into a corresponding physical address based on a transfer address conversion table and outputs the physical address when a first hit signal is input. The semiconductor integrated circuit device according to claim 1 or 2,
The address search conversion unit
A control unit that compares the specified virtual address with the virtual address of the shared address translation table when a search request signal is input, and outputs a second hit signal when they match;
And a second selection unit that selects and outputs a physical address corresponding to the virtual address of the searched shared address translation table based on the second hit signal output from the control unit. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 2.
The peripheral module is
A semiconductor integrated circuit device comprising at least the semiconductor memory. The semiconductor integrated circuit device according to any one of claims 2 to 4,
The comparison control unit
A function of registering the physical address selected by the second selection unit and the designated virtual address in the forwarding address translation table when the designated virtual address is not registered in the forwarding address translation table; A semiconductor integrated circuit device.

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