JP2008117304A - Power unit and power control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely supply required power to an electronic device while suppressing the increase of a circuit scale. <P>SOLUTION: In a flyback period during which the load current of an H-Dr (horizontal transfer circuit) 326 decreases to a prescribed threshold or less, a load circuit 328 operated by a power supply in common to the H-Dr 326 supplies the load current for offsetting the decrease of the load current of the H-Dr 326. Thus, the fluctuation of a power supply voltage at the beginning of an image read period is prevented while suppressing the increase of the circuit scale. Thus, the occurrence of distortion in read image signals is prevented, and high quality images are obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply device and a power control method, and is particularly suitable for use in stabilizing the power supplied to an electronic device.

  2. Description of the Related Art Conventionally, there are imaging devices that process a signal having a video signal period and a blanking period, such as a TV (Television) and a video camera. In these image pickup devices, high-speed transfer of charges called frame transfer is performed during a blanking period. For this reason, about twice as much electric power as the video signal period is consumed in the blanking period. When the current supply capability of the power supply for supplying power to the imaging device is low and the power supply does not have a sufficient capacity to keep the power supply voltage constant, a blanking period with a heavy load as shown in FIG. At the beginning of the video signal period 1702 after the end of 1701, the power supply voltage fluctuates. Therefore, an image distortion period 1703 in which the video signal is distorted occurs at the beginning of the video signal period. As a conventional technique for reducing such distortion of a video signal without increasing the weight and volume of the apparatus as much as possible, there is a technique described in Patent Document 1.

  FIG. 18 is a block diagram showing a configuration of a conventional power supply device for reducing the distortion of the video signal described above. 18, the power supply device includes an unstabilized power supply 201, a control unit 202, a comparison unit 203, a reference voltage generation unit 204, a load (imaging device) 205, a switch 206, and a sub control unit 207. Have.

Here, when the voltage V1 output from the unstabilized power supply 201 is received, the stabilized voltage V is applied to the load 205 by a circuit including the control unit 202 and the sub-control unit 207.
With reference to the reference voltage V0 generated by the reference voltage generator 204, the stabilization voltage V applied to the load 205 during the return period with a heavy load is (V0 + ΔV). During the blanking period, a vertical drive pulse is input to the switch 206 and the sub-control unit 207 operates.

  The comparison unit 203 obtains a difference voltage ΔV indicating a difference between the stabilization voltage V applied to the load 205 and the reference voltage V0. The sub-control unit 207 receives the difference voltage ΔV obtained by the comparison unit 203 and outputs a voltage V2 such that the difference voltage ΔV becomes 0 (zero). Here, the voltage V2 output from the sub-control unit 207 is made approximately equivalent to the stabilization voltage to be supplied (that is, the reference voltage V0). In the technique described in Patent Document 1, a vertical drive pulse having the same time width as the blanking period is used as a control signal. By increasing the current supply capability only during the blanking period, the power supply voltage against the load fluctuation is increased. Fluctuation is suppressed. In addition, since the current supply capability is increased only during the retrace period, the period for increasing the current supply capability is only 8% of the total period compared to the case where the current supply capability is increased uniformly throughout the entire period. Therefore, the weight and volume of the power supply device can be reduced to about 60%.

Japanese Patent Laid-Open No. 7-131691

However, since the technique described in Patent Document 1 increases the current supply capability and supplies a stable voltage only during a return period with a heavy load, there is a large load variation difference between the return period and the video signal period. As a result, the scale of the circuit for stabilizing the voltage with high accuracy becomes large. In addition, when the video signal is greatly amplified by a subsequent amplifier, a high-precision circuit is required in order to make the distortion of the video signal invisible, and this also increases the scale of the circuit. . Furthermore, since the current supply capability is increased during the retrace period, the power consumption increases.
As described above, in the conventional technology, it is difficult to realize both the increase of the amplification degree in both analog and digital signal processing and the improvement of the image quality in an electronic device such as a digital camera. there were. It has also been difficult to reduce power consumption.

The present invention has been made in view of such problems, and a first object of the present invention is to reliably supply necessary electric power to an electronic device while suppressing an increase in circuit scale.
Furthermore, the second object is to make it possible to reduce power consumption.

  The power supply apparatus according to the present invention includes a first circuit that operates by receiving power supply from a power supply, and a second circuit that operates by receiving power supply from the same power supply as the power supply to which the first circuit receives power supply. The second circuit supplies a suppression current for suppressing power fluctuations of the power supply caused by a change in the operating state of the first circuit.

  The power control method of the present invention includes a first circuit that operates by receiving power from a power source, and a first circuit that operates by receiving power from the same power source as the power source that receives power. 2 is a power control method for controlling a second circuit, wherein a control current is supplied to the second circuit for suppressing a power fluctuation of the power source caused by a change in an operation state of the first circuit. It has a step.

According to the present invention, the second circuit allows a suppression current to flow in order to suppress power fluctuations of the power supply caused by a change in the operating state of the first circuit. Therefore, the power fluctuation of the power source can be reduced with a simpler configuration than before, and the power necessary for the electronic device can be supplied as reliably as possible.
According to another feature of the present invention, the timing at which the second circuit starts to flow the suppression current is controlled, so that the second load circuit can flow the suppression current only during a necessary period. . Therefore, power consumption can be further reduced.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

[Digital camera configuration]
FIG. 1 is a block diagram illustrating an example of the overall configuration of a digital camera. Here, a case where a power supply device is mounted on a digital camera using a CCD (Charge Coupled Devices) sensor as a solid-state imaging device will be described as an example.

  In FIG. 1, a lens 301 is for forming an image of a subject on an image plane. The diaphragm 302 is for controlling the amount of light incident on the image plane from the lens 301. The shutter 303 is for causing light to enter the image plane from the lens 301 for a necessary time. The solid-state imaging device 304 is for converting the imaged light image into an electrical signal. As described above, a CCD sensor is used as the solid-state image sensor 304.

  The timing pulse generation circuit 305 generates the following pulse signals, for example. First, a read drive pulse necessary for driving the solid-state imaging device 304 which is a CCD sensor is generated. Second, a sample hold pulse for correlating double sampling the output signal (CCD output signal) of the solid-state imaging device 304 is generated in a CDS (Correlated Double Sampling) circuit 306.

  Third, a clamp pulse for clamping an OB (Optical Black) pixel serving as a black reference of an image to a reference voltage is generated for the clamp circuit 308. Fourth, a pulse for converting an analog imaging signal output from a PGA (Programmable Gain Amplifier) circuit 307 into a digital signal is generated in the AD conversion circuit 309. The pulse signal generated by the timing pulse generation circuit 305 is not limited to the one described above.

  A read drive pulse necessary for driving the solid-state imaging device 304 is output from a horizontal transfer pulse driver (H-Driver) 326 and a vertical transfer pulse driver (V-Driver) 327. The CPU 314 can control the output timing, drive capability, phase, duty, and the like of the transferred pulse.

  The CDS circuit 306 performs correlated double sampling on the output from the solid-state image sensor 304. The PGA circuit 307 amplifies the signal output from the CDS circuit 306. The clamp circuit 308 clamps the voltage value of the OB pixel signal to a reference voltage. The AD conversion circuit 309 converts the analog imaging signal output from the PGA circuit 307 into a digital signal. The video processing circuit 310 measures the photometric quantity from the level of the video signal processing circuit 311 that processes the imaging signal converted into the digital signal as a luminance and color video signal, and the output signal (CCD output signal) of the solid-state imaging device 304. And a photometric circuit 312 or the like.

  The CPU 314 is for overall control of the digital camera. For example, the CPU 314 issues a command to change the gain to the PGA circuit 307 to control the sensitivity and exposure based on the information of the photometric quantity measured by the photometric circuit 312, and the command for how to perform the exposure. Output to the control circuit 316. In addition, the CPU 314 reads out the value adjusted for the camera set from the ROM 321, and sets each part of the digital camera according to the condition of each part based on the read value or operates the load circuit 328. Control for.

  The ROM 321 is a memory used for various setting information and calculations of the digital camera. An LCD (Liquid Crystal Display) 324 is a display device (medium) for displaying an image based on the image signal output from the video signal processing circuit 311. Similar to the LCD 324, the video monitor 325 is a medium for displaying an image based on the image signal output from the video signal processing circuit 311 and is used as an external output of the digital camera.

The power switch 317 is a switch operated by the user to turn on / off the power of the digital camera. The shutter switch 318 is a switch operated by the user at the time of shooting. The shutter switch 318 can be operated in two steps, and includes a switch SW1 that is detected when the shutter button is half-pressed and a switch SW2 that is detected when the shutter switch 318 is pressed to the end. At the stage when the shutter switch 318 is half-pressed and the switch SW1 is pressed, the digital camera performs focus adjustment and determines the shutter time and aperture value during the main exposure. Here, the shutter time is determined based on the time from when the shutter 303 is opened to start exposure until the shutter 303 is closed. The aperture value is determined based on the aperture diameter of the aperture 302. The exposure condition is determined based on an output from the solid-state imaging device 304 when the finder is driven when the switch SW1 is pressed.
When the shutter switch 318 is pressed to the end and the switch SW2 is pressed, actual shooting is performed. The exposure conditions during the main photographing are determined based on the shutter speed and the aperture value determined when the switch SW1 is pressed.

  The battery 322 supplies power for operating the digital camera. The AC power source 323 is for supplying power to the digital camera by a method other than the battery 322. The strobe 320 emits light to compensate for the brightness when the brightness of the subject is low during the main shooting. The load circuit 328 operates with a power source common to each circuit of the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, and the AD conversion circuit 309, and controls a predetermined load current under the control of the CPU 314 and the like. It is a circuit that flows. In other words, the load circuit 328 is provided on the same power supply line as the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, and the AD conversion circuit 309.

[Description of pixel signal readout method]
Next, an example of a pixel signal readout method in the solid-state imaging device (CCD sensor) 304 will be described.
In the present embodiment, a case where the solid-state image sensor (CCD sensor) 304 is a primary color sensor and all pixels are divided into two fields for reading will be described as an example. In addition, the digital camera is assumed to have a frame readout mode for reading all pixels and a thinning readout mode for performing pixel thinning as pixel signal readout modes.

[Description of frame readout mode]
First, a pixel signal readout method in the frame readout mode will be described.
In the frame readout mode, as shown in FIG. 2, in the pixel area of the solid-state imaging device (CCD sensor) 304, one frame is divided into two fields, a first field and a second field, and is read out. The frame readout mode is a mode used at the time of actual photographing. In the following description, the frame reading mode is referred to as a main photographing mode.

  The horizontal scanning line of the solid-state image sensor (CCD sensor) 304 used in this embodiment is assumed to be 1000 lines. The first field is a pixel region of odd lines (1, 3, 5,..., 995, 997, 999 lines), and the second field is even lines (2, 4, 6,... 996, 998, and 1000 lines). In FIG. 2, an OB pixel 401 is a light shielding portion, and an effective pixel 402 is a light receiving portion.

  FIG. 3 is a diagram conceptually illustrating an example of how pixel signals are read out in the main photographing mode. As shown in FIG. 3A, pixel signals of odd lines are read out as pixel signals of the first field (R, Gr) from the lower part of the solid-state imaging device (CCD sensor) 304. Further, as shown in FIG. 3B, the pixel signals of the even lines are read out as the pixel signals of the second field (Gb, B). A specific method for reading the pixel signal will be described later.

  FIG. 4 is a timing chart showing an example of a pixel signal reading operation in the main photographing mode with reference to the vertical synchronization signal VD. FIG. 5 is a timing chart showing an example of the pixel signal readout operation in the main photographing mode with reference to the horizontal synchronization signal HD. The vertical synchronizing signal VD defines a predetermined unit section for obtaining a signal representing one image. The horizontal synchronization signal HD defines a predetermined unit section indicating a horizontal scanning line of one image.

  In FIG. 4, vertical transfer pulses V 1 A, V 1 B, V 2, V 3 A, V 3 B, and V 4 are supplied to a solid-state image sensor (CCD sensor) 304 by a timing pulse generation circuit 305. Further, the blanking signal PBLK is supplied to the CDS circuit 306 by the timing pulse generation circuit 305, and the clamp timing pulse OBCLP is supplied to the clamp circuit 308. The blanking signal PBLK is a negative-polarity signal, and is valid in a period other than the reading period of the OB pixel signal in the horizontal scanning line and the reading period of the effective pixel signal in the horizontal scanning line. In a section where the blanking signal PBLK is valid, smear components of the solid-state image sensor (CCD sensor) 304 are removed, and settings of the CDS circuit 306, the PGA circuit 307, the timing pulse generation circuit 305, etc. are switched. Or The clamp timing pulse OBCLP is a pulse output at a timing at which the clamp circuit 308 corrects an error in the outputs of the PGA 307 circuit and the AD conversion circuit 309 with reference to a preset optical black reference level. The clamp circuit 308 performs a clamp operation for each predetermined horizontal scanning line.

In the main photographing mode, as shown in FIG. 4, the vertical synchronization signal VD, the horizontal synchronization signal HD, the blanking signal PBLK, and the clamp timing pulse OBCLP each take two values, high (High) and low (Low). . The vertical transfer pulses V1A, V1B, V3A, and V3B have three values, high, middle, and low, respectively. The vertical transfer pulses V2 and V4 have two values, middle and low, respectively.
A section 601 in the vertical transfer pulses V1A, V1B, V2, V3A, V3B, and V4 is a section provided to remove smear components of the solid-state imaging device (CCD sensor) 304. In this section 601, charges are transferred at high speed. Is done. The CCD output signal CCD_OUT indicates an output for each horizontal scanning line of each pixel (CCD pixel) of the solid-state imaging device (CCD sensor) 304. In FIG. 4, the numbers written in the CCD output signal CCD_OUT indicate the read horizontal scanning lines. The CCD output signal CCD_OUT is divided into a signal in the first field and a signal in the second field.

As described above, pixel signals are read in the order of the first field and the second field in synchronization with the vertical synchronization signal VD. In each field, as shown in FIG. 5, the pixel signal of each horizontal scanning line is read in synchronization with the horizontal synchronizing signal HD.
In FIG. 5, a timing pulse generation circuit 305 generates horizontal transfer pulses H1 and H2 at the same cycle as the reference timing clock MCLK. The reference timing clock MCLK is a reference clock for one pixel of the solid-state imaging device (CCD sensor) 304.

  Each pulse shown in FIG. 5 is a signal for reading out a pixel signal in each horizontal scanning line in the field defined by the vertical synchronization signal VD. The horizontal transfer pulses H1 and H2 are output in the same cycle as the reference timing clock MCLK which is a reference clock for one pixel. Using these two transfer pulses H1 and H2, pixel signals are sequentially output. The blanking signal PBLK is also used in reading out pixel signals in the horizontal scanning line, as in FIG. During a period in which the ranking signal PBLK is valid, pixel signals are not read by the horizontal transfer pulses H1 and H2. Note that each pulse shown in FIG. 5 takes a binary value of High and Low.

Next, an example of a pixel signal readout procedure in the main photographing mode will be described.
As shown in FIG. 4, reading of the first field is started at times 602 and 603 when the vertical transfer pulses V1A and V1B are at a high level (High level). As described above, the high-level vertical transfer pulses V1A and V1B are read pulses for the first field. With this readout pulse, the charges photoelectrically converted by the photodiodes provided on the odd lines of the photoelectric conversion unit (CCD sensor) 604 are transferred to the vertical transfer registers 501a and 501b as pixel signals (see FIG. 3A). ).

  When vertical transfer pulses V 1 A, V 1 B, V 2, V 3 A, V 3 B, and V 4 are supplied to the vertical transfer register 501, the charges photoelectrically converted by the photodiodes on the first line of the photoelectric conversion unit 604 are horizontal as pixel signals. Moved to the transfer register 503. In the third and subsequent lines, the charge photoelectrically converted by the photodiode is transferred to the horizontal transfer register 503 as a pixel signal. Here, in the first field, only the pixel signals (that is, the R signal and the Gr signal) of the line outputting the R signal and the Gr signal are transferred to the horizontal transfer register 503.

  The pixel signal of the first line transferred to the horizontal transfer register 503 is output to the output stage amplifier 505 pixel by pixel by the horizontal transfer pulses H1 and H2 (see FIG. 3A). The pixel signal amplified by the output stage amplifier 505 is output to the CDS circuit 306 as an analog electric signal. When reading of odd lines from the first line to the 999th line is performed as described above, reading of the first field is completed.

  Subsequently, the second field is read. As shown in FIG. 4, reading of the second field is started at times 604 and 605 when the vertical transfer pulses V3A and V3B become high level (high level). As described above, the high-level vertical transfer pulses V3A and V3B are read pulses for the second field. With this readout pulse, the charges photoelectrically converted by the photodiodes provided in the even lines of the photoelectric conversion unit (CCD sensor) 604 are transferred to the vertical transfer registers 501a and 501b as pixel signals (see FIG. 3B). ).

  When vertical transfer pulses V 1 A, V 1 B, V 2, V 3 A, V 3 B, and V 4 are supplied to the vertical transfer register 501, the charges photoelectrically converted by the photodiodes on the second line of the photoelectric conversion unit 604 are horizontal as pixel signals. Moved to the transfer register 503. In the fourth and subsequent lines, the charge photoelectrically converted by the photodiode is transferred to the horizontal transfer register 503 as a pixel signal. Here, in the second field, only the pixel signal of the line outputting the Gb signal and the B signal is transferred to the horizontal transfer register 503.

The pixel signal of the second line transferred to the horizontal transfer register 503 is output to the output stage amplifier 505 pixel by pixel by the horizontal transfer pulses H1 and H2 (see FIG. 3B). The pixel signal amplified by the output stage amplifier 505 is output to the CDS circuit 306 as an analog electric signal. When the even lines from the second line to the 1000th line are read as described above, the reading of the second field is completed.
As described above, at the time of the main shooting for shooting the subject, the operation is performed in the main shooting mode, and all pixel signals are read out.

[Description of thinning readout mode]
Next, a pixel signal readout method in the thinning readout mode will be described. FIG. 6 is a diagram conceptually illustrating an example of how pixel signals are read in the thinning-out reading mode.
The thinning readout mode is a mode in which the user searches for a subject to be photographed while looking at the LCD 324 or the video monitor 325, and is a mode in which pixels are repeatedly read at high speed. When the user searches for the subject to be photographed, if all the pixel signals are read out every frame, the frame rate is extremely lowered. Therefore, as shown in FIG. 6, pixel signals are thinned out in the vertical direction to increase the frame rate. As described above, in the thinning-out readout mode, the frame rate is higher than that in the main photographing mode, but the resolution is lowered accordingly. Hereinafter, the thinning readout mode is referred to as an EVF (Electronic ViewFinder) mode.

  In FIG. 6, the pixel signal on the first line in the EVF mode is obtained by adding the pixel signal on the first line and the pixel signal on the fifth line in the main photographing mode. Specifically, the R signal and the Gr signal are read out as the pixel signal of the first line in the EVF mode. Similarly, the sum of the pixel signal of the 10th line and the pixel signal of the 14th line in the main photographing mode becomes the pixel signal of the 2nd line in the EVF mode. Specifically, the Gb signal and the B signal are read as the pixel signals on the second line in the EVF mode. In this manner, the frame rate can be increased by thinning out and reading out pixel signals in the vertical direction.

  FIG. 7 is a timing chart showing an example of a pixel signal readout operation in the EVF mode with reference to the vertical synchronization signal VD. FIG. 8 is a timing chart showing an example of a pixel signal readout operation in the EVF mode with reference to the horizontal synchronization signal HD.

In FIG. 7, vertical transfer pulses V 1 A, V 1 B, V 2, V 3 A, V 3 B, and V 4 are supplied from a timing pulse generation circuit 305 to a solid-state image sensor (CCD sensor) 304. Further, the blanking signal PBLK is supplied to the CDS circuit 306 by the timing pulse generation circuit 305, and the clamp timing pulse OBCLP is supplied to the clamp circuit 308.
In the EVF mode, as shown in FIG. 7, the vertical synchronization signal VD, the horizontal synchronization signal HD, the blanking signal PBLK, and the clamp timing pulse OBCLP each take a binary value of high (High) and low (Low). . The vertical transfer pulses V1A and V3A have three values of high, middle, and low, respectively. The vertical transfer pulses V1B, V2, V3B, and V4 each have a binary value of middle and low.

  The CCD output signal CCD_OUT indicates an output for each horizontal scanning line of each pixel (CCD pixel) of the solid-state imaging device (CCD sensor) 304. In FIG. 7, the numbers written in the CCD output signal CCD_OUT indicate the read horizontal scanning lines. As described above, in the EVF mode, pixel signals in two predetermined horizontal scanning lines are added and read out.

  The clamp timing pulse OBCLP is a pulse output at a timing at which the clamp circuit 308 corrects an error in the outputs of the PGA 307 circuit and the AD conversion circuit 309 with reference to a preset optical black reference level. The blanking signal PBLK is a negative-polarity signal, and is valid in a period other than the reading period of the OB pixel signal in the horizontal scanning line and the reading period of the effective pixel signal in the horizontal scanning line. In a section where the blanking signal PBLK is valid, smear components of the solid-state image sensor (CCD sensor) 304 are removed, and settings of the CDS circuit 306, the PGA circuit 307, the timing pulse generation circuit 305, etc. are switched. Or

As described above, one field pixel signal is read out in synchronization with the vertical synchronization signal VD. In each field, as shown in FIG. 8, the pixel signal of each horizontal scanning line is read out in synchronization with the horizontal synchronizing signal HD.
In FIG. 8, a timing pulse generation circuit 305 generates horizontal transfer pulses H1 and H2 at the same cycle as MCLK which is a reference timing clock. As described above, the reference timing clock MCLK is a reference clock for one pixel of the solid-state imaging device (CCD sensor) 304.

  Each pulse shown in FIG. 8 is a signal for reading out a pixel signal in each horizontal scanning line in the field defined by the vertical synchronization signal VD. The horizontal transfer pulses H1 and H2 are output in the same cycle as the reference timing clock MCLK which is a reference clock for one pixel. The blanking signal PBLK is also used in reading out pixel signals in the horizontal scanning line, as in FIG. During a period in which the ranking signal PBLK is valid, pixel signals are not read by the horizontal transfer pulses H1 and H2. In addition, each pulse shown in FIG. 8 takes a binary value of High and Low.

Next, an example of a pixel signal reading procedure in the EVF mode will be described.
As shown in FIG. 7, readout of each field is started at times 701 and 702 when the vertical transfer pulses V1A and V3A are at a high level (High level). As described above, the high-level vertical transfer pulses V1A and V3A are read pulses for each field. With this readout pulse, the charges photoelectrically converted by the photodiode provided in the photoelectric conversion unit (CCD sensor) 604 are transferred to the vertical transfer registers 501a and 501b as pixel signals (see FIG. 6).

When vertical transfer pulses V1A, V1B, V2, V3A, V3B, and V4 are supplied to the vertical transfer register 501, electric charges photoelectrically converted by the first-line and fifth-line photodiodes of the photoelectric conversion unit 604 are arrayed. It is added every time. The added charge is transferred to the horizontal transfer register 503 as a pixel signal on the first line in the EVF mode.
The pixel signals on and after the second line in the EVF mode are also transferred to the horizontal transfer register 503 as in the first line. In the odd lines, only the pixel signals (that is, the R signal and the Gr signal) of the line that outputs the R signal and the Gr signal are transferred to the horizontal transfer register 503. The pixel signal of the first line transferred to the horizontal transfer register 503 is output to the output stage amplifier 505 pixel by pixel by horizontal transfer pulses H1 and H2 (see FIG. 6). The pixel signal amplified by the output stage amplifier 505 is output to the CDS circuit 306 as an analog electric signal. As described above, in the EVF mode, readout is performed by thinning out pixel signals.

[Detailed description of digital camera]
FIG. 9 is a diagram showing in detail an example of the configuration of the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, the AD conversion circuit 309, the load circuit 328, and their peripheral portions. Here, the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, the AD conversion circuit 309, and the load circuit 328 receive power from the same power source (for example, the battery 322) via the same power supply line 910. It shall be supplied.

The crystal oscillation circuit 813 is a CMOS inverter type Colpitts crystal oscillation circuit and oscillates the operation clock of the timing pulse generation circuit 305. The operation clock oscillated by the crystal oscillation circuit 813 is input to the timing pulse generation circuit 305.
A first frequency dividing circuit (1/2 clk) 811 in the timing pulse generation circuit 305 divides the operation clock output from the crystal oscillation circuit 813 by two. The selector 831 selects whether or not to further divide the operation clock frequency-divided by 2 by the first frequency divider 811 by the control of the CPU 314. The second frequency dividing circuit (1/2 clk) 833 further divides the operation clock frequency-divided by 2 by the first frequency dividing circuit 811 into two according to the selection operation by the selector 831. That is, when the operation clock output from the crystal oscillation circuit 813 passes through the second frequency dividing circuit 833, it is divided by four.

As described above, the timing pulse generation circuit 305 uses either the clock obtained by dividing the operation clock output from the crystal oscillation circuit 813 by 2 or the clock obtained by dividing by 4 as the reference timing clock MCLK that is a reference clock for one pixel. Can be selected. That is, the timing pulse generation circuit 305 operates using a clock having a frequency divided by 2 or 4 with respect to the operation clock output from the crystal oscillation circuit 813 as the reference timing clock MCLK. The timing pulse generation circuit 305 outputs a pulse at a timing corresponding to the pixel signal readout mode based on the reference timing clock MCLK. This reference timing clock MCLK is shown in FIGS.
In the present embodiment, a case where a clock obtained by dividing the operation clock output from the crystal oscillation circuit 813 by 4 is used as a reference timing clock MCLK will be described as an example.

  The high-speed pulse generator 809 in the timing pulse generation circuit 305 generates and outputs the following signals based on the reference timing clock MCLK, the vertical synchronization signal VD, and the horizontal synchronization signal HD. First, the high-speed pulse generator 809 generates a sample hold pulse S / H for sampling the output CCD output signal CCD_OUT of the solid-state imaging device (CCD sensor) 304 and outputs it to the CDS circuit 821. Second, the high-speed pulse generator 809 generates an AD conversion instruction clock ADCLK for instructing analog / digital conversion and outputs the AD conversion instruction clock ADCLK to the AD conversion circuit 827.

Third, the high-speed pulse generator 809 generates a clamp timing pulse OBCLP and outputs it to the clamp circuit 823. Fourth, the high-speed pulse generator 809 generates a blanking signal PBLK and outputs it to the CDS circuit 821. Fifth, the high-speed pulse generator 809 generates horizontal transfer pulses H1 and H2 for reading pixel signals and outputs them to the solid-state imaging device (CCD sensor) 304.
The high-speed pulse generator 809 outputs a reference timing clock MCLK to the video processing circuit 310 as a synchronization signal when processing the imaging signal converted into a digital signal by the AD conversion circuit 827. Note that the clock generated by the high-speed pulse generator 809 as described above is an example, and the clock generated by the high-speed pulse generator 809 is not limited to that described above.

  In FIG. 9, it is assumed that the vertical synchronizing signal VD and the horizontal synchronizing signal HD are supplied to a high-speed pulse generator 809 from a microcomputer (not shown). However, the timing pulse generation circuit 805 may internally generate the vertical synchronization signal VD and the horizontal synchronization signal HD based on the reference timing clock MCLK.

  The CPU 314 controls the horizontal transfer pulse driver (H-Driver) 326 such as the output timing, drive capability, phase, and duty of the horizontal transfer pulses H1 and H2 in accordance with the pixel signal readout mode. A horizontal transfer pulse driver (H-Driver) 326 outputs horizontal transfer pulses H1 and H2 to the solid-state imaging device (CCD sensor) 304 under the control of the CPU 314. A CCD output signal CCD_OUT obtained by the solid-state imaging device (CCD sensor) 304 is output to the CDS circuit 306.

  As described above, the horizontal transfer pulses H1 and H2 have the same frequency as the reference timing clock MCLK. The timing pulse generation circuit 305 can switch the drive currents (drive currents) of the horizontal transfer pulses H1 and H2 under the control of the CPU 314. Further, the timing pulse generation circuit 305 can perform output timing, phase adjustment, and the like for each of the horizontal transfer pulses H1 and H2 under the control of the CPU 314.

  The V transfer pulse generator 807 outputs vertical transfer pulses V1A, V1B, V2, V3A, V3B, and V4 for reading out pixel signals to the solid-state imaging device (CCD sensor) 304. The CPU 314 controls the vertical transfer pulse V1A, V1B, V2, V3A, V3B, and V4 output timing, drive capability, phase, duty, and the like according to the pixel signal readout mode, and controls the vertical transfer pulse driver (V-Driver). ) To 327. A vertical transfer pulse driver (V-Driver) 327 outputs vertical transfer pulses V 1 A, V 1 B, V 2, V 3 A, V 3 B, and V 4 to a solid-state image sensor (CCD sensor) 304 according to control by the CPU 314.

As shown in FIG. 9, the configuration of the load circuit 328 is a constant current source circuit. The load circuit 328 operates as follows.
The blanking signal PBLK output from the timing pulse generation circuit 305 is inverted by the inverter 835 and input to the transistor Q1 through the resistor R1. The resistor R1 is a resistor for current limitation. The resistor R1 has a resistance value of several [kΩ]. In this embodiment, the voltage input to the transistor Q1 via the resistor R1 during the period when the inverted pulse of the blanking signal PBLK is at a high level (High level) is a voltage sufficient to turn on the transistor Q1. To be. The operating current (load current) of the load circuit 328 is determined by the emitter voltage value of the transistor Q1 and the resistance value of the resistor R4. Therefore, in the present embodiment, the value of the resistor R4 is determined so that the operating current (load current) of the load circuit 328 becomes a value to be set.

  The transistor Q2 and the resistors R2 and R3 are current limiting circuits. When the emitter current of the transistor Q1 increases, the transistor Q2 is turned on. Therefore, the voltage value that is the product of the emitter current of the transistor Q1 and the resistor R4 is limited by a value based on the emitter current of the transistor Q1 necessary to turn on the transistor Q2. The values of the resistors R2 and R3 are determined so that the operating current (load current) of the load circuit 328 is within a desired range. In the present embodiment, the load circuit 328 allows a predetermined operating current (load current) to flow only when the blanking signal PBLK is at a low level (Low).

[Problems when no load circuit is provided]
Before describing the operation in the load circuit 328, distortion (power supply waveform distortion and image signal distortion) that occurs when the load circuit 328 is not operated (not mounted) will be described. FIG. 10 is a diagram showing an example of the relationship between the value of a signal generated by a digital camera not equipped with the load circuit 328 and time. Specifically, FIG. 10 shows waveforms of the horizontal synchronization signal HD, the horizontal transfer pulses H1, H2, and H-Dr (horizontal transfer circuit) 326, the load current, the power supply voltage, and the image signal.

  The power supply voltage is a power supply voltage that is commonly used in the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, and the AD conversion circuit 309. The horizontal synchronization signal HD is a negative polarity signal. Further, it is assumed that the horizontal transfer pulses H1 and H2 are output during a period indicated by “x”.

  In FIG. 10, the horizontal transfer pulses H1 and H2 are not output (stopped) during a period in which the pixel signal is not read. Therefore, the load current of the H-Dr (horizontal transfer circuit) 326 varies by several tens of mA between when the horizontal transfer pulses H1 and H2 are output and when they are not output. Thus, when the load current of the H-Dr (horizontal transfer circuit) 326 fluctuates, the power supply circuit tries to keep the power supply voltage constant. However, the power supply voltage temporarily decreases until the power supply circuit responds to the load fluctuation of the H-Dr (horizontal transfer circuit) 326. This fluctuation of the power supply voltage affects the load current of the H-Dr (horizontal transfer circuit) 326 of the timing pulse generation circuit 305. Then, under the influence of such power supply voltage fluctuation, the image signal is read as a shading image at the beginning of the reading period.

  As described above, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, and the AD conversion circuit 309 are also operated with a power supply common to the timing pulse generation circuit 305. For this reason, these circuits 306 to 309 are also affected by fluctuations in the power supply voltage, similarly to the timing pulse generation circuit 305. Therefore, the influence of fluctuations in the power supply voltage on the image signal is greater than when only the H-Dr (horizontal transfer circuit) 326 of the timing pulse generation circuit 305 fluctuates. Digital cameras in recent years are required to be small and low in cost. In order to meet such a demand, it is difficult to provide an independent power supply circuit for the timing pulse generation circuit 326. Therefore, in the present embodiment, the above-described load circuit 328 is used to eliminate the stabilization of the power supply voltage and the elimination of the distortion of the image signal.

[Operation when a load circuit is provided]
Next, an example of the operation in the load circuit 328 for realizing the stabilization of the power supply and the elimination of the distortion of the image signal will be described. FIG. 11 is a diagram showing an example of the relationship between the value of a signal generated by the digital camera of this embodiment equipped with the load circuit 328 and time. Specifically, in FIG. 11, the horizontal synchronization signal HD, the horizontal transfer pulses H1, H2, the blanking signal PBLK, the pulse signal input to the base terminal of the transistor Q1, the load current of the load circuit 329, the load current of the H-Dr 326, The power supply voltage and the waveform of an image signal are shown.

  The power supply voltage is a power supply voltage that is commonly used in the load circuit 328, the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, and the AD conversion circuit 309. The horizontal synchronization signal HD is a negative polarity signal. Further, it is assumed that the horizontal transfer pulses H1 and H2 are output during a period indicated by “x”. In addition, the load circuit 328 is assumed to operate in any reading mode of the main photographing mode and the EVF mode.

  In FIG. 11, the horizontal transfer pulses H1 and H2 are not output (stopped) during a period in which the pixel signal is not read. Therefore, as described above, the load current of the H-Dr (horizontal transfer circuit) 326 varies by several tens of mA depending on whether the horizontal transfer pulses H1 and H2 are output or not. Here, the blanking signal PBLK is input to the CDS circuit 306 at the same timing as the period in which the horizontal transfer pulses H 1 and H 2 are not output. The blanking signal PBLK separates the CDS circuit 306 and the timing pulse generation circuit 305 during a period when the pixel signal is not read, that is, during a period when the CCD output signal CCD_OUT is not transferred from the solid-state imaging device (CCD sensor) 304. Used for such purposes.

  As described above, the blanking signal PBLK is inverted by the inverter 835 and input to the load circuit 328. That is, the blanking signal PBLK is also used as a trigger signal for the load circuit 328. As described above, the waveform of the pulse signal input to the base terminal of the transistor Q1 of the load circuit 328 is synchronized with the output period and the non-output period of the horizontal transfer pulses H1 and H2. Further, the value of the resistor R4 is adjusted so that the load current of the load circuit 328 is the same as the load current of the H-Dr (horizontal transfer circuit) 326. Further, the range of variation in the load current of the load circuit 328 is set by the resistors R2 and R3.

  As described above, the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, the AD conversion circuit 309, and the load circuit 328 are supplied with power from the same power source. When the horizontal transfer pulses H1 and H2 are not output, the load current and the value of the H-Dr (horizontal transfer circuit) 326 in the timing pulse generation circuit 305 are substantially the same value and different in sign (the absolute value is substantially the same). A load circuit 328 generates a load current. Therefore, the load current fluctuation (that is, power supply voltage fluctuation) caused by the H-Dr (horizontal transfer circuit) 326 can be canceled by the load current of the load circuit 328. The fluctuation of the load current of the H-Dr (horizontal transfer circuit) 326 occurs when the horizontal transfer pulses H1 and H2 are not output (during the stop period), but the H-Dr (horizontal transfer circuit) 326 during this period. The fluctuation of the load current is suppressed by the operation of the load circuit 328. Therefore, fluctuations in the power supply voltage in these circuits as a whole can be prevented, and distortion of the image signal can be prevented from occurring at the beginning of the image signal readout period (image signal period).

In the power supply apparatus described in the background art, as the fluctuation difference of the load current of the load (H-Dr (horizontal transfer circuit) 326) increases, the circuit scale for stabilizing the voltage with high accuracy increases. For example, even if the voltage can be stabilized to a predetermined accuracy, it is very difficult to make the distortion of the image signal invisible when the image signal is greatly amplified by a subsequent amplifier.
However, in this embodiment, fluctuations in the load (load current of the H-Dr (horizontal transfer circuit) 326) are canceled out, so fluctuations in the load current of the H-Dr (horizontal transfer circuit) 326 are It is settled by the operation of the circuit 328. Therefore, distortion of the image signal can be prevented more reliably than before with a circuit configuration as simple as possible while suppressing an increase in circuit scale.

  As described above, in the present embodiment, in the blanking period in which the load current of the H-Dr (horizontal transfer circuit) 326 decreases below a predetermined threshold, the load current that cancels the decrease in the load current of the H-Dr 326 is A load circuit 328 operating with a power supply common to H-Dr 326 is supplied. Therefore, it is possible to prevent fluctuations in the power supply voltage at the beginning of the image reading period while suppressing an increase in circuit scale. As a result, distortion of the read image signal can be prevented, and a high-quality image can be obtained.

  In the present embodiment, the case where the load circuit 328 is provided in the digital camera which is an example of the imaging apparatus and the fluctuation of the power supply voltage is suppressed is described as an example. However, this is not necessarily required. For example, a load circuit 328 may be provided in a video camera or a mobile phone with a camera. Further, the configuration of the load circuit 328 is not limited to that shown in FIG. What is the configuration and operating conditions of the load circuit as long as the circuit generates a current that cancels the load current of a circuit (for example, H-Dr (horizontal transfer circuit) 326) that operates with a power supply common to the load circuit? It may be.

  In the present embodiment, the H-Dr (horizontal transfer circuit) 326 has been described as an example of a circuit that causes load fluctuation, but the circuit that causes load fluctuation is not limited to the H-Dr (horizontal transfer circuit) 326. For example, when similar load fluctuations occur in other circuits such as the CDS circuit 306, the load fluctuations can be flexibly dealt with. Also, the peripheral circuit connected to the same power source as the circuit causing the load fluctuation is not limited to the one described in the present embodiment.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment described above, the case where the load circuit 328 is operated using the blanking signal PBLK inverted by the inverter 835 as a trigger has been described as an example. On the other hand, in this embodiment, the load circuit 328 is operated based on an instruction from the CPU. This eliminates the need for the load circuit to flow the load current that cancels the fluctuation of the load current of the H-Dr (horizontal transfer circuit) 326 in all the non-output periods of the horizontal transfer pulses H1 and H2. The period during which the current flows can be minimized and power consumption can be reduced. As described above, the present embodiment is different from the first embodiment described above mainly in part of the operation when the load current is passed through the load circuit. Therefore, the same parts as those in the first embodiment described above are denoted by the same reference numerals as those in FIGS.

  FIG. 12 is a diagram showing in detail an example of the configuration of the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, the AD conversion circuit 309, the load circuit 328, and their peripheral portions. Here, power is supplied to the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, the AD conversion circuit 309, and the load circuit 901 from the same power source (for example, the battery 322) via the same power supply line 910. It is assumed that

  An operation clock oscillated by the crystal oscillation circuit 813 is input to the timing pulse generation circuit 305. The input operation clock is frequency-divided into two by the first frequency divider (1/2 clk) 811. According to the selection operation by the selector 831, the operation clock frequency-divided by 2 by the first frequency divider 811 is further frequency-divided by 2 by the second frequency divider (1/2 clk) 833.

As described above, the timing pulse generation circuit 305 uses either the clock obtained by dividing the operation clock output from the crystal oscillation circuit 813 by 2 or the clock obtained by dividing by 4 as the reference timing clock MCLK that is a reference clock for one pixel. Can be selected. The timing pulse generation circuit 305 outputs a pulse at a timing corresponding to the pixel signal readout mode based on the reference timing clock MCLK. This reference timing clock MCLK is shown in FIGS.
In this embodiment, the case where the operation clock output from the crystal oscillation circuit 813 is divided by four is used as the reference timing clock MCLK.

As in the first embodiment, the high-speed pulse generator 809 generates and outputs a sample hold pulse S / H, an AD conversion instruction clock ADCLK, a clamp timing pulse OBCLP, a blanking signal PBLK, and horizontal transfer pulses H1 and H2. .
The high-speed pulse generator 809 outputs a reference timing clock MCLK to the video processing circuit 310 as a synchronization signal when processing the imaging signal converted into a digital signal by the AD conversion circuit 827.

In FIG. 12, it is assumed that the vertical synchronizing signal VD and the horizontal synchronizing signal HD are supplied to the high-speed pulse generator 809 from a microcomputer (not shown), for example.
The CPU 903 controls the horizontal transfer pulse driver (H-Driver) 326 to control the output timing, drive capability, phase, duty, and the like of the horizontal transfer pulses H1 and H2 in accordance with the pixel signal readout mode. A horizontal transfer pulse driver (H-Driver) 326 outputs horizontal transfer pulses H1 and H2 to the solid-state imaging device (CCD sensor) 304 under the control of the CPU 314. A CCD output signal CCD_OUT obtained by the solid-state imaging device (CCD sensor) 304 is output to the CDS circuit 306.

  As described above, the horizontal transfer pulses H1 and H2 have the same frequency as the reference timing clock MCLK. The timing pulse generation circuit 305 can switch the drive currents (drive currents) of the horizontal transfer pulses H1 and H2 under the control of the CPU 903. Further, the timing pulse generation circuit 305 can perform output timing, phase adjustment, and the like for each of the horizontal transfer pulses H1 and H2 under the control of the CPU 903.

  The V transfer pulse generator 807 outputs the vertical transfer pulses V1A, V1B, V2, V3A, V3B, and V4 to the solid-state image sensor (CCD sensor) 304. The CPU 903 controls the vertical transfer pulse V1A, V1B, V2, V3A, V3B, and V4 output timing, drive capability, phase, duty, and the like in accordance with the pixel signal readout mode, and controls the vertical transfer pulse driver (V-Driver). ) To 327. A vertical transfer pulse driver (V-Driver) 327 outputs vertical transfer pulses V 1 A, V 1 B, V 2, V 3 A, V 3 B, and V 4 to a solid-state image sensor (CCD sensor) 304 according to control by the CPU 903.

[Operation of load circuit]
As shown in FIG. 12, the configuration of the load circuit 901 is a constant current source circuit, similar to the load circuit 328 of the first embodiment shown in FIG. The load circuit 901 operates as follows.
The CPU 903 outputs a control signal during a period when the load circuit 901 is desired to operate, and does not output a control signal during other periods. The control signal is input to the transistor Q1 through the resistor R1. The resistor R1 is a resistor for current limitation. The resistor R1 has a resistance value of several [kΩ]. The control signal output from the CPU 903 is a pulse signal having a high level (High) and a low level (Low), and the CPU 903 outputs only a high level (High) control signal. That is, the CPU 903 forms a low-level control signal by not outputting the control signal.

  In the present embodiment, the voltage input to the transistor Q1 via the resistor R1 during the period when the control signal is output from the CPU 903 is set to a voltage sufficient to turn on the transistor Q1. . The operating current of the load circuit 901 is determined by the emitter voltage value of the transistor Q1 and the resistance value of the resistor R4. Therefore, in the present embodiment, the value of the resistor R4 is determined so that the operating current of the load circuit 901 becomes a value to be set.

  Transistor Q2, resistors R2 and R3 are current limiting circuits. When the emitter current of the transistor Q1 increases, the transistor Q2 is turned on. Therefore, the voltage value that is the product of the emitter current of the transistor Q1 and the resistor R4 is limited by a value based on the emitter current of the transistor Q1 necessary to turn on the transistor Q2. The values of the resistors R2 and R3 are determined so that the operating current of the load circuit 901 is within a desired range. The load circuit 901 of this embodiment allows a predetermined load current to flow only during a period when a high-level control signal is output from the CPU 903.

  Next, an example of an operation in the load circuit 901 for realizing the stabilization of the power source and the elimination of the distortion of the image signal will be described. FIG. 13 is a diagram showing an example of the relationship between the value of a signal generated by the digital camera of this embodiment equipped with the load circuit 901 and time. Specifically, in FIG. 13, the horizontal synchronization signal HD, the horizontal transfer pulses H1, H2, the blanking signal PBLK, the pulse signal input to the base terminal of the transistor Q1, the load current of the load circuit 901, the load current of the H-Dr 326, The power supply voltage and the waveform of an image signal are shown.

  The power supply voltage is a power supply voltage that is commonly used in the load circuit 328, the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, and the AD conversion circuit 309. The horizontal synchronization signal HD is a negative polarity signal. Further, it is assumed that the horizontal transfer pulses H1 and H2 are output during a period indicated by “x”. Further, it is assumed that the load circuit 328 operates in any reading mode of the main photographing mode and the EVF mode.

  In FIG. 13, the horizontal transfer pulses H1 and H2 are not output (stopped) during a period in which the pixel signal is not read out. Therefore, as described above, the load current of the H-Dr (horizontal transfer circuit) 326 varies by several tens of mA depending on whether the horizontal transfer pulses H1 and H2 are output or not. The CPU 903 outputs a control signal only during a predetermined period immediately before the horizontal transfer pulses H1 and H2 are output. That is, the waveform of the pulse signal input to the base terminal of the transistor Q1 of the load circuit 901 becomes high level (High) only during a predetermined period immediately before the operation of the horizontal transfer pulses H1 and H2 starts, and only during this period. The load circuit 901 operates. Also, the value of the resistor R4 is adjusted so that the load current (operating current) of the load circuit 901 is the same as the load current (operating current) of the H-Dr (horizontal transfer circuit) 326. Further, the range of variation of the load current (operating current) of the load circuit 328 is set by the resistors R2 and R3.

  As described above, the timing pulse generation circuit 305, the CDS circuit 306, the PGA circuit 307, the clamp circuit 308, the AD conversion circuit 309, and the load circuit 901 are supplied with power from the same power source. When the horizontal transfer pulses H1 and H2 are not output, the load circuit 901 generates a load current having a value substantially the same as the load current of the H-Dr (horizontal transfer circuit) 326 but having a different sign (absolute value is substantially the same). generate. Therefore, the fluctuation of the load current caused by the H-Dr (horizontal transfer circuit) 326 can be canceled by the load current of the load circuit 328. The fluctuation of the load current of the H-Dr (horizontal transfer circuit) 326 occurs when the horizontal transfer pulses H1 and H2 are not output (during the stop period), but the H-Dr (horizontal transfer circuit) 326 during this period. The fluctuation of the load current is suppressed by the operation of the load circuit 328. Therefore, fluctuations in the power supply voltage in these circuits as a whole can be prevented, and distortion of the image signal can be prevented from occurring at the beginning of the image signal readout period (image signal period).

  As described above, in the present embodiment, the control signal is output from the CPU 903 only during the period immediately before the horizontal transfer pulses H1 and H2 are output, and the load circuit 901 is operated during this period to load the H-Dr 326. A load current that offsets the decrease in current was supplied. That is, the load current is allowed to flow through the load circuit 901 only during the minimum necessary period (a period immediately before the end of the blanking period) that can prevent distortion of the image signal at the beginning of the image signal readout period. Therefore, in addition to the effect described in the first embodiment, the read image signal can be prevented from being distorted while suppressing an increase in power consumption, and a high-quality image can be obtained. Is obtained.

In this embodiment, the case where the period immediately before the horizontal transfer pulses H1 and H2 is output is described as an example, but the period immediately before the horizontal transfer pulses H1 and H2 are output is the CPU 903. May be changed.
Also in this embodiment, various modifications described in the first embodiment can be adopted.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the second embodiment described above, the load current is always supplied to the load circuits 328 and 901 immediately before the horizontal transfer pulses H1 and H2 are output. On the other hand, in the present embodiment, the operation and stop of the load circuit are switched according to the value of the load current of the circuit (H-Dr (horizontal transfer circuit) 326) that causes the load fluctuation. As described above, this embodiment is different from the first embodiment described above mainly in part of the operation (the processing of the CPU 903 shown in FIG. 12) when a load current is passed through the load circuit. Therefore, the same parts as those in the first and second embodiments described above are denoted by the same reference numerals as those in FIGS.

An example of the processing operation of the CPU in this embodiment will be described with reference to the flowchart of FIG. Hereinafter, the above-described pixel signal readout mode is referred to as a camera mode.
First, the CPU waits until the power switch 317 of the digital camera is turned on (step S1401). When the power switch 317 is turned on, the CPU determines whether the camera mode is the main shooting mode or the EVF mode (step S1402). This determination can be made based on, for example, a switch provided in the digital camera.

  In the present embodiment, the load current of the H-Dr (horizontal transfer circuit) 326 is 100 [mA] in the main photographing mode, and the load current of the H-Dr (horizontal transfer circuit) 326 is 50 [mA] in the EVF mode. mA]. As the load current value of H-Dr (horizontal transfer circuit) 326 increases, it becomes more difficult to operate the power supply circuit following the load fluctuation, and the fluctuation of the power supply voltage becomes larger, so that the distortion of the image signal is visible. It becomes easy. Therefore, in this embodiment, the load circuit 901 is operated on the assumption that the distortion of the image signal due to the fluctuation of the power supply voltage is not seen until the fluctuation of the load current of the H-Dr (horizontal transfer circuit) 326 is 50 [mA]. I will not let you. That is, when the fluctuation of the load current of H-Dr (horizontal transfer circuit) 326 is larger than 50 [mA], the load circuit 901 is operated. As described above, in the present embodiment, the load circuit 901 is not operated in the EVF mode, and the load circuit 901 is operated only in the main photographing mode, thereby achieving high quality with minimum power consumption. Make sure the image quality is obtained.

  If the result of determination in step S1402 is that the camera mode is main shooting mode, processing proceeds to step S1406 described later. On the other hand, when the camera mode is the EVF mode, the process proceeds to step S1403.

Then, the CPU stops the output operation of the control signal to the load circuit 901 (step S1403).
Next, the CPU determines whether or not the camera mode has been switched (step S1404). If the result of this determination is that camera mode has been switched, processing returns to step S1402 described above. On the other hand, if the camera mode is not switched, the process proceeds to step S1405, and the CPU performs other processing according to the camera mode and ends the processing.

  If it is determined in step S1402 that the camera mode is the main shooting mode, the process advances to step S1406. Then, the CPU stands by until the timing for outputting the control signal to the load circuit 901 is reached. When it is time to output a control signal to the load circuit 901, the CPU outputs a control signal to the load circuit 901 to operate the load circuit 901, and proceeds to step S1404 described above (step S1407). The operation of the load circuit 901 when a control signal is output to the load circuit 901 is the same as in the second embodiment (see FIG. 13). The timing for outputting the control signal to the load circuit 901 is a preset period immediately before the horizontal transfer pulses H1 and H2 are output, as described above.

  As described above, in this embodiment, the control signal is output from the CPU 903 in the main photographing mode, and the control signal is not output from the CPU 903 in the EVF mode. As a result, in addition to the effects described in the first and second embodiments described above, it is possible to prevent distortion of the read image signal while further suppressing increase in power consumption, and to produce a high-quality image. The effect that it can be obtained is acquired.

As described above, in this embodiment, the fluctuation of the load current of the H-Dr (horizontal transfer circuit) 326 in the EVF mode is 50 [mA], and the load of the H-Dr (horizontal transfer circuit) 326 in the main photographing mode. The fluctuation of the current is 100 [mA]. Therefore, the load current fluctuation threshold of the H-Dr (horizontal transfer circuit) 326, which is the operating condition of the load circuit 901, is set to 50 [mA], and the load current fluctuation of the H-Dr (horizontal transfer circuit) 326 is 50 [mA]. The load circuit 901 is operated in the main photographing mode exceeding [mA]. That is, as the threshold value of the operating condition of the load circuit 901, the difference value of the load current before and after the load fluctuation of the H-Dr (horizontal transfer circuit) 326 that is a circuit that causes the load fluctuation is set, and the load It is determined whether or not the circuit 901 is operated.
Thus, in this embodiment, the value of the load current of the H-Dr (horizontal transfer circuit) 326 varies between 0 [mA] and the value of the load current set for each camera mode. He said. Therefore, whether or not to output a control signal to the load circuit 901 is determined using the load current value (50 [mA]) set for the EVF mode as a threshold value. However, the factor causing the load fluctuation is a difference value of the load current value before and after the load fluctuation of the H-Dr (horizontal transfer circuit) 326. That is, the threshold for determining whether or not to output a control signal to the load circuit 901 is determined based on the difference value of the load current value before and after the load fluctuation of the H-Dr (horizontal transfer circuit) 326. Therefore, it is not always necessary to determine the threshold value as described above.

Further, in this embodiment, as described in the second embodiment, a case where a control signal is output to the load circuit 901 during a preset period immediately before the horizontal transfer pulses H1 and H2 are output is taken as an example. I gave it as an explanation. However, this is not always necessary. For example, as described in the first embodiment, the control signal may be output to the load circuit 901 during the entire period in which the horizontal transfer pulses H1 and H2 are not output.
Also in the present embodiment, various modifications described in the first embodiment can be employed.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In the second embodiment described above, the load current is always supplied to the load circuits 328 and 901 immediately before the horizontal transfer pulses H1 and H2 are output. On the other hand, in the present embodiment, the operation and stop of the load circuit are switched according to the ISO sensitivity of the digital camera (amplification degree in the PGA circuit 307). As described above, this embodiment is different from the first embodiment described above mainly in part of the operation (the processing of the CPU 903 shown in FIG. 12) when a load current is passed through the load circuit. Therefore, the same parts as those in the first and second embodiments described above are denoted by the same reference numerals as those in FIGS.

An example of the processing operation of the CPU in this embodiment will be described with reference to the flowchart of FIG.
First, the CPU waits until the power switch 317 of the digital camera is turned on (step S1501). When the power switch 317 is turned on (ON), the CPU determines whether or not the ISO sensitivity set for the digital camera is equal to or higher than ISO400 (step S1502). This determination can be made based on, for example, a switch provided in the digital camera.

  In the present embodiment, the value of the load current of the H-Dr (horizontal transfer circuit) 326 is the same value in the main photographing mode and the EVF mode. Further, the influence of the load fluctuation of the H-Dr (horizontal transfer circuit) 326 on the image signal is not dependent on the camera mode, and the load circuit 901 operates in common in each camera mode (main photographing mode and EVF mode). Shall be

  The image signal (CCD output signal CCD_OUT) is sampled by the CDS circuit 306 and then amplified by the PGA circuit 307 with a predetermined amplification degree. As described above, the H-Dr (horizontal transfer circuit) 326, the CDS circuit 306, and the PGA circuit 307 are supplied with power from the same power source. Therefore, when there is a load fluctuation of the H-Dr (horizontal transfer circuit) 326, the greater the amplification degree in the PGA circuit 307, the easier it is to see the distortion of the image signal. Therefore, in this embodiment, when the ISO sensitivity set in the digital camera is up to ISO 200, it is assumed that distortion of the image signal is not seen, and the load circuit 901 is not operated and the ISO sensitivity is ISO 400 or higher. The load circuit 901 is operated. In the present embodiment, this makes it possible to obtain a high-quality image with minimum power consumption.

  As a result of the determination in step S1502, if the ISO sensitivity is not ISO 400 or higher (when the ISO sensitivity is ISO 200 or lower), the process proceeds to step S1507 described later. On the other hand, if the ISO sensitivity is ISO 400 or higher, the CPU waits until the timing for outputting the control signal to the load circuit 901 is reached (step S1502). When it is time to output a control signal to the load circuit 901, the CPU outputs a control signal to the load circuit 901 to operate the load circuit 901 (step S1503). The operation of the load circuit 901 when a control signal is output to the load circuit 901 is the same as that of the second embodiment (see FIG. 13). The timing for outputting the control signal to the load circuit 901 is a preset period immediately before the horizontal transfer pulses H1 and H2 are output, as described above.

  Then, the CPU determines whether or not the ISO sensitivity has been switched (step S1505). If it is determined that the ISO sensitivity has been switched, the process returns to step S1502 described above. On the other hand, if the ISO sensitivity has not been switched, the process proceeds to step S1506, where the CPU performs other processes according to the camera mode and ends the process.

  As a result of the determination in step S1502, if the ISO sensitivity is not ISO 400 or higher (when the ISO sensitivity is ISO 200 or lower), the process proceeds to step S1507. Then, the CPU stops the output operation of the control signal to the load circuit 901. Then, the process proceeds to step S1505 described above.

  As described above, in this embodiment, the control signal is output from the CPU 903 when the ISO sensitivity is ISO 400 or higher, and the control signal is not output from the CPU 903 when the ISO sensitivity is ISO 200 or lower. As a result, in addition to the effects described in the first and second embodiments described above, it is possible to prevent distortion of the read image signal while further suppressing increase in power consumption, and to produce a high-quality image. The effect that it can be obtained is acquired.

  In the present embodiment, the ISO sensitivity set in the digital camera is used as a threshold value, and the amplification factor of the PGA circuit 307 is described as an example as a factor that makes distortion of the image signal easy to see. However, for example, it is sufficiently conceivable to amplify the image signal with a digital circuit provided in the video signal processing circuit 311 shown in FIG. Therefore, whether the load circuit 901 is operated using a threshold based on the total amplification degree including the analog circuit and the digital circuit that process the image signal (CCD output signal) output from the solid-state imaging device (CCD sensor) 304. It may be determined whether or not.

Further, in this embodiment, as described in the second embodiment, a case where a control signal is output to the load circuit 901 during a preset period immediately before the horizontal transfer pulses H1 and H2 are output is taken as an example. Explained and explained. However, this is not always necessary. For example, as described in the first embodiment, the control signal may be output to the load circuit 901 during the entire period in which the horizontal transfer pulses H1 and H2 are not output.
Also in this embodiment, various modifications described in the first embodiment can be adopted.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. In the second embodiment described above, the load current is always supplied to the load circuits 328 and 901 immediately before the horizontal transfer pulses H1 and H2 are output. On the other hand, in the present embodiment, the operation and stop of the load circuit are switched according to the drive frequency of the digital camera. As described above, this embodiment is different from the first embodiment described above mainly in part of the operation (the processing of the CPU 903 shown in FIG. 12) when a load current is passed through the load circuit. Therefore, the same parts as those in the first and second embodiments described above are denoted by the same reference numerals as those in FIGS.

An example of the processing operation of the CPU in this embodiment will be described with reference to the flowchart of FIG.
First, the CPU waits until the power switch 317 of the digital camera is turned on (step S1601). When the power switch 317 is turned on, the CPU determines whether the camera mode is the main shooting mode or the EVF mode (step S1602). This determination can be made based on, for example, a switch provided in the digital camera.

  In the present embodiment, in the EVF mode, the timing pulse generation circuit 305 drives a clock having a frequency obtained by dividing the operation clock oscillated by the crystal oscillation circuit 813 by 2 as the reference timing clock MCLK. On the other hand, in the case of the main photographing mode, the timing pulse generation circuit 305 drives a clock having a frequency obtained by dividing the operation clock oscillated by the crystal oscillation circuit 813 by 4 as the reference timing clock MCLK. That is, the frequency (drive frequency) of the reference timing clock MCLK in the EVF mode is set lower than the frequency of the reference timing clock MCLK in the main photographing mode. Specifically, in the present embodiment, the frequency of the reference timing clock MCLK in the EVF mode is 20 [MHz], and the frequency of the reference timing clock MCLK in the main photographing mode is 40 [MHz]. In the present embodiment, it is assumed that the load fluctuation of the H-Dr (horizontal transfer circuit) 326 is smaller in the EVF mode than in the main photographing mode. When the frequency of the reference timing clock MCLK is up to 20 [MHz], the load circuit 901 is not operated and the frequency of the reference timing clock MCLK is higher than 20 [MHz], assuming that the image signal is not distorted. Then, the load circuit 901 is operated. That is, the load circuit 901 is not operated in the EVF mode, and the load circuit 901 is operated in the main photographing mode. In the present embodiment, by doing so, a high-quality image can be obtained with a minimum power consumption.

  If the result of determination in step S1602 is that the camera mode is main shooting mode, processing proceeds to step S1606 described later. On the other hand, when the camera mode is the EVF mode, the process proceeds to step S1603.

Then, the CPU stops the output operation of the control signal to the load circuit 901 (step S1603).
Next, the CPU determines whether or not the camera mode has been switched (step S1604). If the result of this determination is that the camera mode has been switched, processing returns to step S1602 described above. On the other hand, if the camera mode is not switched, the process proceeds to step S1605, and the CPU performs other processing according to the camera mode and ends the processing.

  If it is determined in step S1602 that the camera mode is the main shooting mode, the process advances to step S1606. Then, the CPU waits until it is time to output a control signal to the load circuit 901 (step S1606). When it is time to output a control signal to the load circuit 901, the CPU outputs a control signal to the load circuit 901 to operate the load circuit 901, and proceeds to the above-described step S1404 (step S1607). The operation of the load circuit 901 when a control signal is output to the load circuit 901 is the same as in the second embodiment (see FIG. 13). The timing for outputting the control signal to the load circuit 901 is a preset period immediately before the horizontal transfer pulses H1 and H2 are output, as described above.

  As described above, in this embodiment, the control signal is output from the CPU 903 when the drive frequency is higher than 20 [MHz], and the control signal is not output from the CPU 903 when the drive frequency is 20 [MHz] or less. I made it. As a result, in addition to the effects described in the first and second embodiments described above, it is possible to prevent distortion of the read image signal while further suppressing increase in power consumption, and to produce a high-quality image. The effect that it can be obtained is acquired.

  In this embodiment, the higher the drive frequency, the larger the load current value of the H-Dr (horizontal transfer circuit) 326, and it is determined whether or not to operate the load circuit 901 according to the drive frequency. I did it. However, this is not always necessary. When the margin of the timing of sampling performed by the CDS circuit 306 is reduced, it becomes difficult to avoid distortion of the image signal due to power supply fluctuation. That is, in order to determine whether or not to operate the load circuit 901 in consideration of the total of the ability (margin) of the signal processing circuit for avoiding the distortion of the image signal in addition to the influence of the load fluctuation. The driving frequency can be set for each camera mode as a threshold value.

(Other embodiments of the present invention)
In order to operate various devices to realize the functions of the above-described embodiments, program codes of software for realizing the functions of the above-described embodiments are provided to an apparatus or a computer in the system connected to the various devices. You may supply. What was implemented by operating said various devices according to the program stored in the computer (CPU or MPU) of the system or apparatus is also included in the category of the present invention.

  In this case, the program code of the software itself realizes the functions of the above-described embodiment. The program code itself and means for supplying the program code to a computer, for example, a recording medium storing the program code constitute the present invention. As a recording medium for storing the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, the functions of the above-described embodiments are not only realized by executing the program code supplied by the computer. It goes without saying that the program code is also included in the embodiment of the present invention even when the function of the above-described embodiment is realized in cooperation with an operating system or other application software running on the computer. Yes.

Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer, the CPU provided in the function expansion board performs part or all of the actual processing based on the instruction of the program code. Needless to say, the present invention includes the case where the functions of the above-described embodiments are realized by the processing.
Further, after the supplied program code is stored in the memory provided in the function expansion unit connected to the computer, the CPU or the like provided in the function expansion unit performs part or all of the actual processing based on the instruction of the program code. Do. Needless to say, the present invention includes the case where the functions of the above-described embodiments are realized by the processing.

  Note that each of the above-described embodiments is merely a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. . That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 is a block diagram illustrating an example of an overall configuration of a digital camera according to a first embodiment of the present invention. It is the figure which showed the 1st Embodiment of this invention and showed an example of the pixel area | region of a solid-state image sensor (CCD sensor). FIG. 5 is a diagram conceptually illustrating an example of a state in which a pixel signal is read in a main shooting mode according to the first embodiment of this invention. 5 is a timing chart illustrating an example of a pixel signal readout operation in the main photographing mode according to the first embodiment of the present invention with reference to a vertical synchronization signal. 5 is a timing chart illustrating an example of a pixel signal reading operation in the main photographing mode according to the first embodiment of the present invention with reference to a horizontal synchronization signal. It is the figure which showed the 1st Embodiment of this invention and showed an example of a mode that a pixel signal was read in EVF mode. 5 is a timing chart illustrating an example of a pixel signal readout operation in the EVF mode according to the first embodiment of the present invention on the basis of a vertical synchronization signal. 5 is a timing chart illustrating an example of a pixel signal reading operation in the EVF mode according to the first embodiment of the present invention with reference to a horizontal synchronization signal. BRIEF DESCRIPTION OF THE DRAWINGS It is the figure which showed the 1st Embodiment of this invention and showed in detail the example of a structure of a timing pulse generation circuit, a CDS circuit, a PGA circuit, a clamp circuit, an AD converter circuit, a load circuit, and those peripheral parts. It is the figure which showed the 1st Embodiment of this invention and showed an example of the relationship between the value of the signal which generate | occur | produces with the digital camera which does not mount a load circuit, and time. It is the figure which showed the 1st Embodiment of this invention and showed an example of the relationship between the value of the signal which generate | occur | produces with the digital camera carrying a load circuit, and time. FIG. 6 is a diagram illustrating a second embodiment of the present invention and illustrating in detail an example of the configuration of a timing pulse generation circuit, a CDS circuit, a PGA circuit, a clamp circuit, an AD conversion circuit, a load circuit, and their peripheral portions. It is the figure which showed the 2nd Embodiment of this invention and showed an example of the relationship between the value of the signal which generate | occur | produces with the digital camera carrying a load circuit, and time. 10 is a flowchart illustrating an example of a processing operation of a CPU according to the third embodiment of this invention. It is a flowchart which shows the 4th Embodiment of this invention and demonstrates an example of processing operation of CPU. It is a flowchart which shows 5th Embodiment of this invention and demonstrates an example of processing operation of CPU. It is a figure which shows the prior art and shows a mode that a power supply voltage and a video signal are distorted in the beginning of a video signal period. It is a block diagram which showed the prior art and showed the structure of the conventional power supply device for reducing the distortion of a video signal.

Explanation of symbols

301 Lens 302 Aperture 303 Shutter 304 Solid-state imaging device (CCD sensor)
305 Timing pulse generation circuit 306 CDS circuit 307 PGA circuit 308 Clamp circuit 309 AD conversion circuits 314 and 903 CPU
321 ROM
322 Battery 323 AC power source 326 Horizontal transfer pulse driver (H-Driver)
327 Vertical transfer pulse driver (V-Driver)
328, 901 Load circuit 401 OB pixel 402 Effective pixel 501 Vertical transfer register 503 Horizontal transfer register 505 Output stage amplifier 807 V transfer pulse generator 809 High-speed pulse generator 811 First frequency divider 813 Crystal oscillation circuit 831 Selector 833 Second component Circuit

Claims (16)

A first circuit that operates by receiving power from a power source;
The first circuit has a second circuit that operates by receiving power supply from the same power source as the power source receiving power supply;
The power supply apparatus, wherein the second circuit passes a suppression current for suppressing power fluctuation of the power supply caused by a change in an operation state of the first circuit.   2. The power supply device according to claim 1, wherein the second circuit allows the suppression current to flow from when the first circuit is changed from an operating state to a stopped state until the second circuit returns to the operating state.   The power supply apparatus according to claim 1, wherein the second load circuit changes a time during which the suppression current flows. Control means for controlling the timing at which the second circuit starts to flow the suppression current;
4. The power supply device according to claim 1, wherein the second circuit starts to flow the suppression current based on control by the control unit. 5.   The value of the suppression current that the second circuit passes is substantially the same as the current value during operation of the first circuit, according to any one of claims 1 to 4. Power supply.   6. The power supply device according to claim 1, wherein the second circuit causes the suppression current to flow according to a value of a current during operation of the first circuit. 7. Photoelectric conversion means for converting an optical image of a subject into an electrical signal;
Amplifying means for amplifying the electrical signal photoelectrically converted by the photoelectric conversion means,
The power supply device according to claim 1, wherein the second circuit passes the suppression current in accordance with an amplification degree of the amplification unit. Drive signal generating means for generating a drive signal for reading out the electrical signal photoelectrically converted by the photoelectric conversion means;
6. The power supply device according to claim 1, wherein the second circuit passes the suppression current in accordance with a frequency of the drive signal generated by the drive signal generation unit. A first circuit that operates by receiving power from a power source;
A power control method for controlling a second circuit that operates by receiving power from the same power source as the power source that receives power from the first circuit,
A power control method comprising a power control step of causing a suppression current for suppressing power fluctuations of the power supply caused by a change in an operating state of the first circuit to flow to the second circuit.   The power control step allows the suppression current to flow through the second circuit until the first circuit returns from the operating state to the operating state after the first circuit is stopped from the operating state. The power control method described.   The power control method according to claim 9 or 10, wherein the power control step changes a time during which the suppression current is passed through the second load circuit.   12. The power control method according to claim 9, wherein the power control step controls a timing at which the second circuit starts to flow the suppression current.   The value of the suppression current that the second circuit passes is substantially the same as the current value during operation of the first circuit, according to any one of claims 9 to 12. Power control method.   14. The power control step according to claim 9, wherein in the power control step, the suppression current is caused to flow through the second circuit in accordance with a current value during operation of the first circuit. Power control method. A photoelectric conversion step for converting an optical image of a subject into an electrical signal;
An amplification step for amplifying the electrical signal photoelectrically converted by the photoelectric conversion step,
The power control method according to any one of claims 9 to 13, wherein the power control step causes the suppression current to flow through the second circuit in accordance with an amplification degree of the electric signal. A drive signal generation step of generating a drive signal for reading out the electrical signal photoelectrically converted by the photoelectric conversion step;
The power control step causes the suppression current to flow through the second circuit according to the frequency of the drive signal generated by the drive signal generation step. The power control method described.

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