JP2008112945A - Memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory which operates stably by suppressing a characteristic degradation of a storage element. <P>SOLUTION: The memory has a plurality of memory cells 10 which comprise: a nonvolatile resistance change type storage element 5 in which a storage layer is formed between two electrodes, an electric field having a different polarity is applied to between these two electrodes, thereby shifting atoms or ions, and a resistance value of the storage layer changes reversibly; and a switching field-effect transistor 6 series-connected to this resistance change type storage element 5, wherein information is stored in the memory cells 10. This structure is that an on current of the field-effect transistor 6 in the memory cells 10 is smaller than the on current of the field-effect transistor in a portion excluding the memory cells 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory device in which a memory cell is configured by a nonvolatile resistance change memory element.

  As a semiconductor nonvolatile memory, a flash memory is the most common, and a NOR flash memory and a NAND flash memory are widely used for code storage applications and data storage applications.

Since the NAND flash memory uses an FN (Fowler-Nordheim) tunnel current for a rewrite operation, a high voltage of about 20 V is required in principle.
For this reason, after the 32 nm generation, it is said that it is difficult to advance the miniaturization of the element, that is, increase the capacity while maintaining the current performance (particularly, the number of repetitions).

On the other hand, since the NOR flash memory uses HE (hot electron) injection for the rewrite operation, the movement of the electron only exceeds the energy barrier of 3.8 eV between Si (silicon) and SiO ₂ (silicon dioxide). It is necessary to apply energy, and in principle, a voltage of 5 to 6 V must be applied between the source and drain of the transistor constituting the memory cell.
For this reason, it is difficult to miniaturize the cell transistor after the 45 nm generation.

  Furthermore, in terms of performance, both the NAND type and the NOR type have a slow rewrite speed of 5 to 250 microseconds, and the number of rewrites is limited to about 100,000 times. Even if it is suitable, it is difficult to say that it is a general-purpose nonvolatile memory.

Further, a phase change memory has been proposed as a new nonvolatile memory that should replace the flash memory.
However, this phase change memory is sensitive to changes in environmental temperature because the rewrite operation is performed on the storage element by temperature control of 600 ° C. or higher.
For this reason, when a cell is miniaturized, there is a problem that it may interfere with an adjacent cell.

  Therefore, as a non-volatile memory having a simple element structure that can be easily miniaturized, a resistance change type non-volatile memory such as PMC (Programmable Metallization Cell) or RRAM (Resistive RAM) having a structure in which a memory element is sandwiched between upper and lower electrodes. Memory has been proposed (see, for example, Patent Document 1 and Patent Document 2).

  Among these variable resistance nonvolatile memories, PMC and some RRAMs reversibly change the resistance value by moving metal elements in the state of atoms or ions in the variable resistor thin film by heat and electric field. It is thought that is realized.

JP-A-2005-322942 JP 2005-216387 A

  However, Joule heat is generated by electric current in the process of movement of atoms or ions of the metal element described above. If the amount of generated heat is too large, the variable resistor thin film may be damaged by heat and an electric field during rewriting (writing / erasing), and the characteristics of the memory element may be deteriorated.

  In order to solve the above-described problems, the present invention provides a storage device that operates stably by suppressing deterioration in characteristics of the storage element.

  In the memory device of the present invention, a memory layer is provided between two electrodes. When an electric field having a different polarity is applied between the two electrodes, atoms or ions move, and the resistance value of the memory layer is reversibly changed. A configuration in which a plurality of non-volatile variable resistance memory elements and switching field-effect transistors connected in series to the variable resistance memory elements are provided, and information is stored in the memory cells. Thus, the on-current of the field effect transistor in the memory cell is smaller than the on-current of the field effect transistor in a portion other than the memory cell.

According to the configuration of the memory device of the present invention described above, the memory cell includes the nonvolatile resistance change storage element and the switching field effect transistor connected in series to the resistance change storage element. The voltage applied to the memory cell during operation (write operation, erase operation, read operation) is divided between the resistance change storage element and the field effect transistor.
Then, the on-current of the field effect transistor in the memory cell is configured to be smaller than the on-current of the field effect transistor in a portion other than the memory cell, so that the resistance change type memory connected in series to the field effect transistor. The current flowing through the element can be reduced. Thus, the amount of heat generated in the memory layer of the memory element can be reduced during the operation in which the resistance change type memory element is in the high resistance state (during the erase operation).
Therefore, it is possible to solve the problem that the storage element (particularly the storage layer) undergoes characteristic deterioration due to a high electric field in a high temperature state.

According to the above-described present invention, it is possible to solve the problem that the storage element (particularly the storage layer) undergoes characteristic deterioration due to a high electric field in a high temperature state, thereby rewriting (writing or erasing) many times. In addition, data retention performance can be improved.
Therefore, a highly reliable storage device with stable operation can be realized.

  Embodiments of the storage device of the present invention will be described below. In the present invention, a memory device is configured using a resistance change type memory element as a memory cell.

First, FIG. 1 shows a film configuration of one form of a resistance change type memory element used in the memory device of the present invention.
This resistance change type storage element 5 has a film configuration having an insulator film 3 and a conductor film 4 between two electrodes (lower electrode 1 and upper electrode 2).

Examples of the material for the insulator film 3 include oxides of rare earth elements such as Gd ₂ O ₃ and other oxides such as SiO ₂ .
Examples of the material of the conductor film 4 include a metal film, an alloy film (for example, a CuTe alloy film), a metal compound film, and the like containing one or more metal elements selected from Cu, Ag, and Zn. Preferably, a chalcogenide compound of Cu, Ag, Zn (compound containing S, Se, Te) is used as the material of the conductor film 4.

When such a material is used, the metal element (for example, Cu, Ag, Zn) contained in the conductor film 4 has a property of being ionized and attracted to the low potential side electrode.
Similarly, a metal element other than Cu, Ag, and Zn having the property of being easily ionized may be used for the conductor film 4. For example, it is known that cations such as Li, Na, K, Au, and H move easily. Furthermore, it is generally known that anions such as oxygen move, even in a thin film containing oxygen and a transition metal element that can take a stable state with a plurality of valences, for example, Ni, Ti, W, etc. Similarly, it is considered that the resistance value is reversibly changed by the movement of oxygen.
Moreover, the structure which metal elements, such as Cu, Ag, Zn, move in the state of an atom by the electric field between both the electrodes 1 and 2 may be sufficient.

Therefore, when a voltage is applied between the electrodes 1 and 2 so that the lower electrode 1 on the insulator film 3 side has a low potential, a downward current Iw flows, and metal element ions are attracted to the lower electrode 1. Then, it enters the insulator film 3. And when ion reaches | attains the lower electrode 1, between both the electrodes 1 and 2 will conduct | electrically_connect and a resistance value will fall. In this manner, data (information) is written into the resistance change type storage element 5.
On the other hand, when a voltage is applied between the electrodes 1 and 2 so that the upper electrode 2 on the conductor film 4 side has a low potential, an upward current Ie flows, and the metal element is ionized and attracted to the upper electrode 2. Since the insulating film 3 is removed, the insulation between the electrodes 1 and 2 is increased, and the resistance value is increased. In this manner, data (information) is erased from the resistance change type storage element 5.

By repeating the above-described change, the resistance value of the resistance change storage element 5 can be reversibly changed between the high resistance state and the low resistance state.
Actually, since the resistance value of the insulator film 3 varies depending on the amount of metal element ions in the insulator film 3, the insulator film 3 may be regarded as a storage layer in which information is stored and held. it can.

  A memory (storage device) can be formed by forming a memory cell using this resistance change type storage element 5 and providing a large number of memory cells.

Next, with respect to the resistance change type memory element 5 shown in FIG. 1, its voltage-current characteristics are shown in FIG. 2A, and its voltage-resistance characteristics are shown in FIG. 2B.
In an initial state, a metal element (for example, Cu) is distributed in the conductor film (for example, chalcogenide compound) 4. In this state, the resistance value is high and current does not flow easily.
First, when the voltage V between the electrodes 1 and 2 is increased in FIG. 2A, a current flows at a certain threshold (point A), and the insulating film 3 that has been high resistance changes to low resistance until then. (Point B).
This operation is defined as “write operation”.
At this time, a slight leakage current flows in the insulator film 3 due to the applied electric field, and the nearby temperature rises due to the heat generated by the current, and the metal element (for example, Cu ions) moves, so that the metal element is rich. It is considered that the resistance of the insulator film 3 is reduced by forming the region in the insulator film 3 in a columnar shape and the region serving as a conductive path for conducting electrical conduction. Since the insulator film 3 has a sufficiently higher resistance than the other films 1, 2, and 4 of the memory element 5, the resistance value of the memory element 5 as a whole is lowered by reducing the resistance of the insulator film 3.
Then, the memory element 5 changes to ohmic characteristics, and a current flows in proportion to the voltage.
Thereafter, even when the voltage V is returned to 0 V, the resistance value (low resistance value) is kept.

Next, when the voltage V between the electrodes 1 and 2 is increased in the negative direction in FIG. 2A, the insulator film 3 which has been low resistance until then changes to high resistance at a certain threshold (point C). (D point).
This operation is defined as “erase operation”.
At this time, a current flows through the conductive path by the applied electric field, and the temperature of the conductive path and the surrounding insulator film 3 rapidly increases. In a region rich in a metal element (for example, Cu) that forms a conductive path at a high temperature, the metal element is ionized and moves in the direction of the upper electrode 2 by an electric field opposite to the writing operation, and the conductive path is cut off. Thus, the resistance of the insulator film 3 is increased. Since the insulating film 3 has a sufficiently higher resistance than the other films 1, 2, and 4 of the memory element 5, the resistance value of the entire memory element 5 is also increased by increasing the resistance of the insulating film 3.
Thereafter, even when the voltage V is returned to 0 V, the resistance value (high resistance value) is kept.

  As described above, the resistance value R of the resistance change memory element 5 has a hysteresis characteristic as shown in the voltage-resistance characteristic of FIG. 2B due to the change of the resistance value of the insulator film 3. The resistance change type storage element 5 can be used as a nonvolatile storage element.

  If writing and erasing are repeated many times for the resistance change type memory element 5 having the configuration shown in FIG. 1, the characteristics of the memory element 5 may deteriorate as described above.

Subsequently, as an embodiment of the present invention, FIG. 3 shows a circuit configuration diagram of one memory cell of a memory device in which a memory cell is configured using the resistance change type memory element 5 shown in FIG.
As shown in FIG. 3, this memory device is formed by connecting the resistance change type memory element 5 shown in FIG. 1 and a field effect transistor (FET) 6 such as an NMOS field effect transistor (NMOS-FET) in series. A memory cell 10 is configured.
The field effect transistor 6 side of the memory cell 10 is connected to the bit line 7, and the resistance change storage element 5 side of the memory cell 10 is connected to the source line 8. The gate of the field effect transistor 6 is connected to the word line 9.
In the memory cell 10 having the configuration of FIG. 3, the field effect transistor 6 controls access to the resistance change storage element 5 of each memory cell 10.

In the memory cell 10 shown in FIG. 3, since the high electric field is applied to the insulator film 3 of the memory element 5 at a high temperature at the moment when the resistance of the memory element 5 is increased during the erase operation, the insulator film 3 is most damaged. It is considered that the characteristics are easily deteriorated.
On the other hand, during the write operation, the on-resistance of the switching field effect transistor 6 is applied in series to the memory element 5, so that a conductive path is formed and simultaneously applied to the insulator film 3 of the memory element 5. Since the electric field is reduced and then the temperature rises due to heat generation, a high electric field is not applied at a high temperature.

  Therefore, it can be said that it is important to appropriately control the conditions during the erasing operation, in particular, the heat generation due to the current during the erasing operation, in order to reduce the characteristic deterioration due to the repeated operations of writing and erasing.

  Therefore, in the memory device of the present embodiment, in particular, the field effect transistor 6 in the memory cell 10 is compared with the field effect transistor in a portion (peripheral circuit or the like) other than the memory cell 10 of the memory device. The transistor characteristics are small.

Various configurations are conceivable as specific configurations for achieving transistor characteristics with low on-current. For example, the following configurations can be adopted.
(1) The ratio (W / L) of the channel width W to the channel length L of the field effect transistor 6 is reduced. For example, a field effect transistor other than the memory cell 10 generally uses W / L = 1 as the minimum size, but the field effect transistor 6 of the memory cell 10 satisfies W / L ≦ 0.8.
(2) The impurity concentration of the source / drain region of the field effect transistor 6 is lowered. In general, an impurity concentration of 1 × 10 ¹⁹ / cm ^{3 to} 5 × 10 ²⁰ / cm ³ is used for the source / drain region, and this is about 1 × 10 ¹⁷ / cm ^{3 to} 5 × 10 ¹⁸ / cm ³ , for example. By reducing it to ON, the on-current can be effectively reduced. The impurity concentration reduction may be performed locally in the entire source / drain region or only in the vicinity of the channel region.
(3) The impurity concentration of the channel region of the field effect transistor 6 is increased. In general, the impurity concentration of the channel region is 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁷ / cm ³ , and this is increased to, for example, about 5 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁷ / cm ^3. By doing so, the on-current can be reduced. The impurity concentration may be increased locally in the entire channel region, only in the vicinity of the source / drain region, or may have a concentration distribution in the depth direction.

  More preferably, the field effect transistor 6 is designed so as not to cause breakdown voltage degradation between the terminals of the field effect transistor 6 even when the operating voltage of the field effect transistor 6 is 3 V or higher. In order to suppress the resistance deterioration in this way, the impurity concentration in the region of the field effect transistor 6 may be set as described in (2) and (3).

According to the above-described embodiment, the field effect transistor 6 in the memory cell 10 has a smaller on-current than the field effect transistor in a portion (peripheral circuit or the like) other than the memory cell 10 of the memory device. By setting the characteristics, the current flowing through the insulator film 3 of the memory element 5 can be reduced. As a result, the amount of heat generated by the insulator film 3 of the memory element 5 can be reduced during the erase operation in which the memory element 5 is in a high resistance state.
Therefore, it is possible to solve the problem that the insulator film 3 of the memory element 5 is deteriorated in characteristics by a high electric field in a high temperature state.

According to the present embodiment, it is possible to solve the problem that the insulator film 3 of the memory element 5 is deteriorated in characteristics by a high electric field in a high temperature state, so that many rewrites (writing and erasing) are performed. The data holding performance can be improved, and the data retention performance can be improved.
Therefore, a highly reliable storage device with stable operation can be realized.

<Operation experiment>
Here, a device of the memory device is actually manufactured, and it is quantitatively evaluated how much the on-current of the field effect transistor 6 of the memory cell 10 needs to be suppressed. The required electrical characteristics were estimated.

FIG. 4 shows a circuit configuration diagram used for the experiment including the memory cell 10 shown in FIG.
The configuration in the memory cell 10 is similar to the circuit configuration diagram shown in FIG. In the circuit configuration of FIG. 4, a unit in which a switch 11 and an ammeter 12 are connected in parallel is provided in the middle of the bit line 7.

The voltage application conditions in each process of writing, erasing, and reading were set as shown in the timing charts of FIGS. 5A to 5C.
As shown in FIG. 5A, in the writing process, with the switch 11 closed and the writing voltage Vw applied to the source line 8, the potential of the word line 9 is changed from 0 V to Vgw to turn on the field effect transistor 6. After that, the potential of the bit line 7 is changed from Vw to 0V. Thereby, the source line 8 side of the memory element 5 becomes a high potential.
As shown in FIG. 5B, in the erasing process, the switch 11 is closed and the potential of the word line 9 is changed from 0 V to Vge while the potential of the source line 8 is set to 0 V (ground potential). Is turned on, the potential of the bit line 7 is changed from 0V to the erase voltage Ve. Thereby, the source line 8 side of the memory element 5 becomes a low potential.
As shown in FIG. 5C, in the reading process, the switch 11 is opened so that a current flows toward the ammeter 12. With 0.1 V applied to the source line 8, the potential of the word line 9 is changed from 0 V to VDD (power supply potential) to turn on the field effect transistor 6, and then the potential of the bit line 7 is set to 0.1 V. To 0V. As a result, the source line 8 side of the memory element 5 becomes a little higher potential, and a small amount of current for reading flows. In this reading process, the voltage applied to both electrodes 1 and 2 of the memory element 5 is made sufficiently smaller than in the writing process so that the state of the insulator film 3 of the memory element 5 does not change.
In the reading process, the current flowing through the memory element 5 is measured by the ammeter 12, so that the voltage applied to the memory cell 10 (0.1 V) and the on-resistance value of the field effect transistor 6 are determined. The resistance value can be obtained. When the on-resistance value of the field effect transistor 6 is sufficiently smaller than the resistance value of the memory element 5, the on-resistance value can be ignored and calculated.

(Experiment 1)
The size of the field effect transistor 6 of the memory cell 10 was changed, and the rewriting repetitive operation and the data retention test after the repetitive operation were performed at each size.
As a result, the relationship between the size of the field effect transistor 6 and the number of repeated operations and the data retention characteristics were examined.

As the size of the field effect transistor 6 of the memory cell 10, when the channel width of the field effect transistor 6 is W and the channel length is L, a ratio represented by W / L is used as a parameter.
Specific application voltage conditions are as follows. Each voltage shown in FIGS. 5A to 5C is obtained by using VDD (power supply potential): 2.5 V, write voltage Vw: 3.0 V, erase voltage Ve: 2.0 V, Vge: 3.. Each was set to 0V. Note that the potential Vgw of the word line 9 in the writing process was changed in accordance with the size parameter W / L of the field effect transistor 6.

The writing process and the erasing process were alternately performed on the memory cell 10, and the two processes were set as one time and repeated a predetermined number of times (10 ⁿ times; n is an integer of 1 to 7). At this time, the memory cell 10A in which the last process of repetition is a writing process (should be in a low resistance state) and the memory cell 10B in which the last process of repetition is an erasing process (should be in a high resistance state) 30 bits each (total of 60 bits) were prepared.
A read process is performed on the memory cell 10A that should be in the low resistance state and the memory cell 10B that should be in the high resistance state for each 30 bits, and the ammeter 12 shown in FIG. 5 was measured, and the resistance value of the memory element 5 was determined.
Subsequently, after this repeated operation, each memory cell 10 was held at 130 ° C. for 1 hour as a data holding test.
Then, after the data retention test, the reading process was performed again on the memory cells 10A and 10B each having the same 30 bits and a total of 60 bits, and the resistance value of the memory element 5 was obtained.

The conditions of the data retention test described above (130 ° C./1 hour) were determined by the data retention performance required for the storage element 5. Even if a condition different from this condition is required, if the relative data retention capability under the same condition is compared, the superiority or inferiority of the data retention capability under different conditions can be estimated. .
Therefore, it is possible to find a relative condition required for the characteristics of the transistor 6 in the memory cell 10 in order to reduce the characteristic deterioration due to the repeated operation of writing / erasing from the result of the data retention test described above. It is.

The procedure for this experiment was as follows.
The parameter W / L of the size of the field effect transistor 6 is fixed, and the number of repetitions 10 ⁿ is increased from 1 in order, and a memory cell of 60 bits is prepared for each n value, and repeated operation And a data retention test.
When the resistance value after repeated operation and after the data retention test has little variation and the low resistance state and the high resistance state are sufficiently separated, the data retention test is determined to be “pass”. . On the other hand, when the resistance value after repeated operation or the resistance value after the data retention test has a large variation, or when the low resistance state and the high resistance state are not sufficiently separated, it was determined as “fail”.
The experiment of the corresponding size W / L was ended when n was increased and a judgment of failure was given.

  Then, the size parameter W / L of the field effect transistor 6 is set to three types of small (W / L = 0.5), medium (W / L = 2), and large (W / L = 6). The above tests were performed on size.

  As experimental results, distributions of resistance values of the memory element 5 before and after the data retention test are shown in FIGS.

First, the memory cell 10 was fabricated with a configuration in which the size of the field effect transistor 6 was medium (parameter W / L = 2), n was increased, and each test was performed. Note that the potential Vgw of the word line 9 in the writing process was set to 2.0V.
In the case of n = 1 (10 times), although not shown in the figure, the resistance value variation was slight, and the low resistance state and the high resistance state were sufficiently separated, and it was determined to be acceptable.
FIG. 6 shows the distribution of resistance values of the memory element 5 when n = 2 (100 times). As shown in FIG. 6, the resistance values in the low resistance state and the high resistance state are not changed before and after the data retention test, and the separation width between the two is sufficiently secured. Therefore, the data retention test was determined to be acceptable.
FIG. 7 shows a distribution of resistance values of the memory element 5 when n = 3 (1000 times). As shown in FIG. 7, in this case as well, each resistance value in the low resistance state and the high resistance state does not change before and after the data retention test, and a sufficient separation width can be secured. Therefore, the data retention test was determined to be acceptable.
FIG. 8 shows a distribution of resistance values of the memory element 5 when n = 4 (10,000 times). As shown in FIG. 8, even before the data retention test, the resistance value variation in the high resistance state is increased and the distribution is disturbed, and some of the memory cells are in a state opposite to the state that should originally be. After the data retention test, the distribution on the high resistance side has shifted to the low resistance side. Therefore, this condition was determined to be unacceptable.

Next, the memory cell 10 was fabricated with a configuration in which the size of the field effect transistor 6 was small (parameter W / L = 0.5), n was increased, and each test was performed. Note that the potential Vgw of the word line 9 in the writing process was set to 1.8V.
In each of the cases of n = 1, 2, 3, 4, and 5, although not shown, the resistance value variation was slight, and the low resistance state and the high resistance state were sufficiently separated, and it was determined to be acceptable.
FIG. 9 shows the distribution of resistance values of the memory element 5 when n = 6 (10 ⁶ times). As shown in FIG. 9, the resistance values in the low resistance state and the high resistance state are not changed before and after the data retention test, and the separation width between the two is sufficiently secured. Therefore, this condition was also determined to pass the data retention test.
FIG. 10 shows a distribution of resistance values of the memory element 5 when n = 7 (10 ⁷ times). As shown in FIG. 10, the variation in the resistance value in the high resistance state is slightly increased even before the data retention test. After the data retention test, the distribution on the low resistance side has shifted to the high resistance side. Therefore, this condition was determined to be unacceptable.

Next, the memory cell 10 was fabricated with a configuration in which the size of the field effect transistor 6 was large (parameter W / L = 6), n was increased, and each test was performed. Note that the potential Vgw of the word line 9 in the writing process was set to 1.3V.
FIG. 11 shows a distribution of resistance values of the memory element 5 when n = 1 (10 times). As shown in FIG. 11, the resistance values in the low resistance state and the high resistance state both change little before and after the data retention test, and a sufficient separation width can be secured. Therefore, the data retention test was determined to be acceptable.
FIG. 12 shows a distribution of resistance values of the memory element 5 when n = 2 (100 times). As shown in FIG. 12, even before the data retention test, the dispersion of the resistance value in the high resistance state is increased and the distribution is disturbed, and some of the memory cells are in a state opposite to the state that should originally be. After the data retention test, the distribution on the high resistance side has shifted to the low resistance side. Therefore, this condition was determined to be unacceptable.

In this way, the relationship between the on-current during the erasing operation of the field effect transistor 6 of the memory cell 10 and the number of repetitions was obtained based on the result of determining whether the data retention test was accepted or not under each condition.
When the size of the transistor 6 is medium (W / L = 2), the on-current during the erase operation is 300 μA.
When the size of the transistor 6 is small (W / L = 0.5), the on-current during the erase operation is 75 μA.
When the size of the transistor 6 is large (W / L = 6), the on-current during the erase operation is 900 μA.
The graph of FIG. 13 shows the relationship between the on-current during the erase operation and the number of repetitions. The thick curve in FIG. 13 shows the estimated limit for passing.

As shown in FIG. 13, it can be seen that the number of possible repetitions increases as the size of the field effect transistor 6 is reduced to reduce the on-current.
Here, the use of criterion that 100,000 is a flash memory guaranteed value (10 ⁵ times), the on-current of the transistor 6 is 120μA is the upper limit. This value corresponds to W / L = 0.8 in the size of the field effect transistor 6.

In general, in order to minimize the size of the memory cell 10 in the 1T-1R type memory cell 10, it is desirable to set the parameter W / L = 1 for the size of the field effect transistor. It will be 150 μA.
Therefore, in order to reduce the on-current to the above-described upper limit value (120 μA), a series resistance having a resistance value of 25% or more of the on-resistance value is added to the field effect transistor 6 of the memory cell 10.
That is, for example, in the circuit configuration diagram of FIG. 3, a series resistance is provided between the field effect transistor 6 and the storage element 5 or between the field effect transistor 6 and the bit line 7.

  Further, in order to guarantee a withstand voltage between each terminal of the field effect transistor 6 to a certain value or more, the impurity concentration of the source / drain region of the field effect transistor 6 is reduced or the impurity concentration of the channel region of the field effect transistor 6 is increased. Also, it is possible to reduce the on-state current.

  As described above, the memory cell 10 uses the field effect transistor 6 with a design different from the high performance design field effect transistor for each generation of logic used in the peripheral circuit portion, and reduces its on-current. There is a need.

Note that, as a general method of suppressing the on-current of the field effect transistor of the memory cell, a method of reducing the on-current by setting the gate potential low can be considered.
However, in this method, as can be seen from the circuit configuration diagram of FIG. 3, the voltage applied to the memory element during the erase operation is
(Transistor gate potential)-(transistor voltage threshold)
Therefore, the erase operation may not be performed properly due to insufficient applied voltage.

  Therefore, when the size of the field effect transistor 6 was set, it was examined how much the applied voltage to the memory element 5 during the erasing operation, that is, the erasing voltage Ve in FIG.

(Experiment 2)
Subsequently, the relationship between the stability of the repetitive operation and the erase voltage Ve was examined by changing the magnitude of the erase voltage Ve.
With the size of the field effect transistor 6 set as described above (parameter W / L = 2), the same cell is repeatedly operated, and the low resistance state and the high resistance state of the memory element 5 are changed every predetermined number of repetitions. Each resistance value was measured.

Specific application voltage conditions are as follows. Each voltage shown in FIGS. 5A to 5C is obtained by using VDD (power supply potential): 2.5 V, write voltage Vw: 3.0 V, Vgw: 1.8 V, Vge: 3.0 V, And set each.
Then, the erase voltage Ve was changed to 1.1 V, 1.5 V, and 1.9 V, and the repetitive operation and the resistance value were measured, respectively.

FIG. 14A and FIG. 14B show the measurement results when the erase voltage Ve = 1.1V. FIG. 14A shows the relationship between the number of repetitions and the resistance values of the memory element 5 in the low resistance state and the high resistance state. FIG. 14B shows the distribution of resistance values (degree of variation) in each state measured in FIG. 14A as a cumulative probability distribution.
Similarly, measurement results when the erase voltage Ve = 1.5V are shown in FIGS. 15A and 15B, and measurement results when the erase voltage Ve = 1.9V are shown in FIGS. 16A and 16B.

As shown in FIGS. 14A and 14B, when the erasing voltage Ve = 1.1 V, the resistance value in the high resistance state greatly moves up and down, and the variation in the resistance value in the high resistance state is large. .
As shown in FIGS. 15A and 15B, when the erasing voltage Ve = 1.5V, the resistance value in the high resistance state slightly increases and decreases slightly, but the resistance value in the high resistance state still varies.
As shown in FIGS. 16A and 16B, when the erasing voltage Ve = 1.9 V, the vertical movement of the resistance value in the high resistance state is further reduced, and is within the same digit except for a part.
That is, it can be seen that the voltage applied to the memory element 5 (erase voltage Ve) during the erase process needs to be 1.9 V (about 2 V) or more for stable operation.

  Therefore, the method of reducing the current by setting the gate potential low is not preferable in terms of stable operation because the voltage applied to the memory element 5 during the erasing process becomes small.

  In the present invention, the resistance change type storage element is not limited to the configuration of the storage element 5 shown in FIG. 1, and other configurations are possible.

  For example, (1) the structure in which the stacking order is reversed from that in FIG. 1 and an insulator film is stacked on the conductor film, (2) the conductor film also serves as an electrode, and (3) instead of providing the conductor film, A configuration in which a metal element used for the conductor film is included in the insulator film is conceivable.

In addition to the above-described memory element having a metal element that is easily ionized and an insulator film, the resistance change type memory element has various configurations.
Even if the resistance variable element has other configurations, it is possible to move atoms or ions by applying electric fields having different polarities between the two electrodes, so that the resistance value of the memory layer changes reversibly. By applying the present invention, it is possible to suppress deterioration of element characteristics due to a high electric field in a high temperature state.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is sectional drawing which shows the film | membrane structure of one form of the resistance change memory element used for the memory | storage device of this invention. A is a voltage-current characteristic of the resistance change type storage element of FIG. B is a voltage-resistance characteristic of the resistance change type memory element of FIG. FIG. 2 is a circuit configuration diagram of a memory cell configured using the resistance change type storage element illustrated in FIG. 1. It is the circuit block diagram used for experiment including a memory cell. It is a figure which shows the voltage application conditions in each process of AC experiment. This is a distribution of resistance values of the memory element when the size of the field effect transistor is medium and n = 2. This is a distribution of resistance values of the memory element when the size of the field effect transistor is medium and n = 3. This is a distribution of resistance values of the memory element when the size of the field effect transistor is medium and n = 4. This is a distribution of resistance values of the memory element when the size of the field effect transistor is small and n = 6. This is a distribution of resistance values of the memory element when the size of the field effect transistor is small and n = 7. This is a distribution of resistance values of the memory element when the size of the field effect transistor is large and n = 1. This is a distribution of resistance values of the memory element when the size of the field effect transistor is large and n = 2. It is a graph which shows the relationship between the ON current at the time of erase | eliminating operation, and the repetition frequency. A is a diagram showing the relationship between the number of repetitions and the resistance value when the erase voltage Ve = 1.1V. B is a diagram showing a distribution of resistance values in each state of FIG. 14A. A is a diagram showing the relationship between the number of repetitions and the resistance value when the erase voltage Ve = 1.5V. B is a diagram showing a distribution of resistance values in each state of FIG. 15A. A is a diagram showing the relationship between the number of repetitions and the resistance value when the erase voltage Ve = 1.9V. B is a diagram showing a distribution of resistance values in each state of FIG. 16A.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 Upper electrode, 3 Insulator film | membrane, 4 Conductor film | membrane, 5 Resistance change memory element, 6 Field effect transistor, 7 Bit line, 8 Source line, 9 Word line, 10 Memory cell

Claims (6)

A non-volatile type in which a memory layer is provided between two electrodes, atoms or ions move by applying electric fields of different polarities between the two electrodes, and the resistance value of the memory layer changes reversibly. A storage device having a plurality of memory cells each including a resistance change storage element and a switching field effect transistor connected in series to the resistance change storage element, and storing information in the memory cell,
The memory device, wherein an on-current of the field effect transistor in the memory cell is smaller than an on-current of a field effect transistor in a portion other than the memory cell.   The memory device according to claim 1, wherein the atom or the ion moving by the electric field of the resistance change type memory element is an atom or an ion of one or more elements selected from Cu, Ag, and Zn. .   The memory device according to claim 1, wherein the field effect transistor in the memory cell has a channel width W and a channel length L satisfying a relationship of W / L ≦ 0.8.   A series resistor is connected to the field effect transistor in the memory cell, and a resistance value of the series resistor is 25% or more of an on-resistance value of the field effect transistor in the memory cell. The storage device according to claim 1.   2. The memory according to claim 1, wherein the field effect transistor in the memory cell has a lower impurity concentration in a source / drain region than the field effect transistor in a portion other than the memory cell. apparatus.   The memory device according to claim 1, wherein the field effect transistor in the memory cell has a higher impurity concentration in a channel region than the field effect transistor in a portion other than the memory cell.

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