JP2008083117A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of providing display of high quality in spite of temporal deterioration of a current driven type light emitting element such as an organic EL element. <P>SOLUTION: Pixel formation parts P(i,j) are programmed so that first to fourth switching TFTs 11 to 14 controlled through control lines Ri and Wi and gate lines Gi connected respective gate terminals have their gate potentials held at the potentials of video display data from source lines Sj after a driving TFT 15 is placed in operation to compensate variance in threshold voltage of the driving TFT 15, and then an organic EL element 16 is made to illuminate. Then, the organic EL element 16 decreases in luminance owing to temporal deterioration even when applied with the same voltage, but a first capacitor 17 can hold the gate-source voltage of the driving TFT 15 at a desired value; so display of high quality can be provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device using a current-driven light-emitting element and a driving method thereof, and more particularly to an active matrix display device having a transistor for driving the light-emitting element and a driving method thereof.

  In recent years, as demand for lightweight, thin, and high-speed displays increases, research and development of display devices such as organic EL (Electro Luminescence) displays and FEDs (Field Emission Display) have been actively conducted. In addition, matrix display devices are roughly classified into passive matrix display devices and active matrix display devices. In response to demands for an increase in the number of display pixels and an increase in display speed associated with higher resolutions. In recent years, active matrix display devices have become mainstream.

  Therefore, in recent years, many active matrix organic EL displays are seen. However, in this display device, the relationship between the luminance and voltage of the organic EL element easily changes due to the influence of driving time, ambient temperature, and the like. In the voltage control type driving method in which the luminance of the EL element is controlled by the voltage, it is very difficult to suppress the luminance variation of each organic EL element. In this respect, since the relationship between the luminance and current of the organic EL element is stable, the influence of external factors such as ambient temperature is small. For this reason, as a driving method of the organic EL display that suppresses luminance variation, a current control type driving method in which the luminance of the organic EL element is controlled by current is preferable.

  In addition, a pixel circuit and a driving circuit used in an active matrix display device include a TFT (Thin Film Transistor) as a switching element. The TFT is generally made of a material such as amorphous silicon, low-temperature polycrystalline silicon, or CG (Continuous Grain) silicon. However, such TFTs tend to have variations in characteristics such as threshold voltage and mobility as compared with transistors made of single crystal silicon. For this reason, a configuration that suppresses variations in luminance by providing a circuit that compensates for these variations is common.

  Further, in the current control type driving method, the configuration of the pixel circuit for compensating for the variation in TFT characteristics is roughly divided into two methods: a current program method and a voltage program method. The current programming method is a method for defining (programming) a current value flowing in a TFT for driving an organic EL element (hereinafter referred to as “driving TFT”) by a current signal, and the voltage programming method is the driving TFT described above. Is defined (programmed) by a voltage signal.

  In this current programming method, variations in threshold voltage and mobility of the driving TFT can be compensated, but in the voltage programming method, only the threshold voltage can be corrected. In this respect, the current programming method is excellent. However, since this method handles very small current values, it is difficult to design the pixel circuit and the driver circuit, and parasitic current is required during the period required for programming the current values. Since the effect of capacitance is large, it is not easy to increase the area.

  In contrast to such a current programming method, the voltage programming method cannot correct the mobility of the driving TFT, but since the current value is programmed by a voltage signal, the influence of parasitic capacitance and the like is slight. There is an advantage that the circuit design is relatively simple. Furthermore, the influence of the mobility variation on the current value is smaller than the influence of the threshold voltage variation, and the influence can be suppressed to some extent by devising the TFT fabrication process. Even a display device of the type can obtain a sufficient display quality.

  In such a voltage control type driving method, the configuration and operation of a conventional pixel circuit (hereinafter referred to as “first conventional example”) in an organic EL display adopting a circuit configuration capable of compensating for variations in threshold voltage. Will be described with reference to FIG. 9 (see Non-Patent Document 1).

  FIG. 9A is a circuit diagram showing the configuration of the pixel circuit in the first conventional example, and FIG. 9B is a timing chart showing its operation. As shown in FIG. 9A, this pixel circuit includes four switching TFTs 901 to 904, an organic EL element 906, and a driving TFT 905 for driving the organic EL element 906. Prepare.

  The switching TFT 901 has its gate terminal connected to the scanning signal line SLT (n−1) for selecting the (n−1) th row, which is the previous row of the nth row including the pixel circuit, and its drain. The terminal (or source terminal) is connected to the drain terminal of the driving TFT 905, and the source terminal (or drain terminal) is connected to the gate terminal of the driving TFT 905.

  The switching TFT 902 has a gate terminal connected to the scanning signal line SLTn for selecting the n-th row including the pixel circuit, and a drain terminal connected to the data line DT that supplies the pixel circuit with a voltage indicating light emission luminance. The source terminal is connected to the gate terminal of the driving TFT 905 via the capacitor C1.

  The switching TFT 903 has a gate terminal connected to the control signal line TNO, a drain terminal connected to the power supply line VDD, and a source terminal connected to the drain terminal of the driving TFT 905.

  The switching TFT 904 has its gate terminal connected to the scanning signal line SLT (n−1), its drain terminal connected to the source terminal of the switching TFT 902, and its source terminal supplying a reference voltage. Connected to the signal line Vref.

  Here, referring to FIG. 9B, when the voltage signal applied to the control signal line TNO becomes active in the period T1, the switching TFT 903 is turned on and applied to the scanning signal line SLT (n−1). When the voltage signal to be activated becomes active, the switching TFT 901 is turned on. As a result, the reference voltage of the reference voltage signal line Vref is charged to one end of the capacitor C1, so that the gate potential of the driving TFT 905 is held at a voltage corresponding to the current flowing through the organic EL element 906. Next, since the voltage TFT applied to the control signal line TNO becomes inactive in the period T2, the switching TFT 903 is turned off, so that the current path to the organic EL element 906 is cut off, but the driving TFT 905 is turned off. As a result, the gate potential of the driving TFT 905 shifts in a self-compensating manner toward the threshold voltage. After that, in the period T3, the voltage signal applied to the scanning signal line SLTn is activated, so that the switching TFT 902 is turned on. Therefore, the signal voltage of the data line DT is applied to the gate potential of the driving TFT 905, so Data indicating luminance is written, and then the voltage signal applied to the control signal line TNO becomes active, whereby the switching TFT 903 is turned on, and the organic EL element 903 emits light with the light emission luminance.

  With such a circuit configuration, in the first conventional example, the first and second periods required for threshold voltage compensation and the like are such that the voltage signal applied to the scanning signal line SLTn is active. That is, it has an advantage that is not influenced by the length of the selection period in one frame. Further, by performing charging using the reference voltage signal line Verf that hardly flows current separately from the power supply line VDD through which a large current flows, variation in the gate potential of the driving TFT 905 at that time can be suppressed. It has the advantage that can be improved.

  Next, a configuration of a conventional pixel circuit (hereinafter referred to as “second conventional example”) different from the first conventional example in an organic EL display employing a circuit configuration capable of compensating for variations in threshold voltage, and The operation will be described with reference to FIG. 10 (see Patent Document 2).

  FIG. 10 is a circuit diagram showing a configuration of the pixel circuit of the second conventional example. This pixel circuit includes switching TFTs 911 to 914, which are four switching elements, a driving TFT 915, and an organic EL element 916, and the configuration thereof is the same as that of the first conventional example described above. Is omitted. As shown in FIG. 10, the second conventional example differs from the first conventional example in that the signal lines Geln, Ginin, Gsetn are used instead of the scanning signal line SLT (n−1) in the pixel circuit. Is provided.

In the second conventional example, the gate potential holding capacitance of the driving TFT 916 during the light emission period of the organic EL element 916 is a combined capacitance of the parasitic capacitance of the driving TFT 916, the parasitic capacitance of the organic EL element 916, and the wiring capacitance. With such a configuration, the area of the pixel circuit can be reduced.
JP 2005-309150 A JHJung et al., “14.1 inch full emission AMOLED display with top emission”, SID05 digest, 2005, p. 1558-1541

  Here, it is known that the internal resistance of the current-controlled light-emitting element, particularly the organic EL element, increases due to deterioration over time. That is, even when the same current is passed through the element, it is known that the drive voltage applied to both ends of the element rises compared to the beginning after aging. Therefore, in the configuration of the pixel circuit as in the first conventional example, even if the source potential of the driving TFT varies, the gate potential does not follow it. Later, there was a problem that the gate-source voltage in the driving TFT at the time of light emission decreased from the beginning, and as a result, the current for driving the organic EL element decreased.

  In the configuration of the second conventional example, the gate-source voltage can be held by the combined capacitance including the parasitic capacitance of the driving TFT 916. However, the gate-source parasitic capacitance varies greatly. There is a problem in the accuracy of the held voltage value.

  Further, in the second conventional technique, the presence of the parasitic capacitance Vds between the gate and the drain of the driving TFT 916 is also a problem. That is, when the signal potential of the control wiring Geln is activated, a path is formed between the gate terminal of the driving TFT 916 and the control wiring Geln via the parasitic capacitance of the switching TFT 914 and the parasitic capacitance Vds. The potential fluctuation of the wiring Geln is applied to the gate potential as noise. This noise appears particularly prominently when the size of the driving TFT 916 becomes large, for example, when an amorphous silicon substrate with low mobility is used.

  Therefore, in the present invention, in order to solve the above problems, the influence of noise based on parasitic capacitance in the driving TFT is minimized, and the current of the current driving light emitting element such as an organic EL element is also deteriorated over time. An object of the present invention is to provide a display device capable of maintaining a gate-source voltage at a desired value and performing high-quality display and a driving method thereof.

The first invention includes a plurality of pixel forming units including current-driven electro-optic elements that form an image to be displayed, a plurality of video signal lines for transmitting a video signal representing the image to be displayed, A plurality of scanning signal lines which are provided so as to intersect with the plurality of video signal lines and transmit a scanning signal for selecting the pixel formation portion; and first and second power supplies for causing a current to flow through the electro-optic element An active matrix display device in which the plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively,
The pixel forming portion includes:
The first power supply line and the second power supply line are provided in series so as to be connected to the source terminal of the electro-optic element on the first path connecting the first power supply line and the second power supply line, and applied to the gate terminal. A driving transistor for determining a current to be passed through the first path in response to the video signal to be transmitted;
The scanning that is provided on the second path connecting the video signal line and the gate terminal of the driving transistor and is given to the gate terminal in a second period among the predetermined first to third periods. First switching means for connecting or blocking the second path by a signal;
A second switching unit that is on the first path, connects the first power supply line and the driving transistor in the third period, and cuts off in the first period;
Third switching means for connecting the gate terminal of the driving transistor and the drain terminal of the driving transistor in the first period and blocking in the second and third periods;
A first capacitor provided between a gate terminal of the driving transistor and a source terminal of the driving transistor is interposed on the second path, and one end thereof is used as the first switching means. And a second capacitor connected at the other end to the gate terminal of the driving transistor.

According to a second invention, in the first invention,
The first capacitor is formed between a gate electrode corresponding to the gate terminal of the driving transistor and a source electrode corresponding to the source terminal of the driving transistor, and the gate-drain of the driving transistor The capacitance value is larger than the capacitance value between them.

According to a third invention, in the second invention,
The driving transistor is formed on a predetermined substrate, and has a first overlapping region between the gate electrode of the driving transistor and the source electrode of the driving transistor in a direction perpendicular to the substrate. And there is a second overlapping region between the gate electrode of the driving transistor and a drain electrode corresponding to the drain terminal of the driving transistor, the size of the second overlapping region is It is characterized by being smaller than one overlapping region.

According to a fourth invention, in the third invention,
The driving transistor is a multi-finger type having two or more source regions and one or more drain regions, wherein the number of the source regions is larger than the number of the drain regions.

According to a fifth invention, in the first invention,
A third power line to which a predetermined constant voltage is applied;
The pixel forming portion connects a connection point of the first switching means and the second capacitor and the third power supply line in the first period, and cuts off in the second and third periods. And further includes fourth switching means.

According to a sixth invention, in the fifth invention,
The third and fourth switching means are transistors;
The fourth switching means is formed such that its gate length, gate width, and parasitic capacitance are substantially equal to the gate length, gate width, and parasitic capacitance of the third switching means, respectively. It is characterized by.

According to a seventh invention, in the first invention,
A third power line to which a predetermined fixed voltage is applied;
The pixel formation unit further includes fifth switching means for connecting the source terminal of the driving transistor and the third power supply line in the first period and blocking in the second and third periods. It is characterized by that.

In an eighth aspect based on the first aspect,
The electro-optical element is an organic EL (Electro Luminescence) element.

According to a ninth invention, in the first invention,
At least one of the driving transistor and the second switching means is an insulated gate field effect transistor.

In a tenth aspect based on the first aspect,
The driving transistor and the first to third switching means are thin film transistors.

In an eleventh aspect based on the tenth aspect,
11. The display device according to claim 10, wherein all of the thin film transistors are n-channel transistors.

In a twelfth aspect based on the tenth aspect,
The thin film transistor is made of amorphous silicon.

A thirteenth aspect of the invention includes a plurality of pixel forming portions including current-driven electro-optic elements that form an image to be displayed, a plurality of video signal lines for transmitting a video signal representing the image to be displayed, A plurality of scanning signal lines which are provided so as to intersect with the plurality of video signal lines and transmit a scanning signal for selecting the pixel formation portion; and first and second power supplies for causing a current to flow through the electro-optic element A plurality of pixel forming portions arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively. ,
The pixel forming portion includes:
The first power supply line and the second power supply line are provided in series so as to be connected to the source terminal of the electro-optic element on the first path connecting the first power supply line and the second power supply line, and applied to the gate terminal. A driving transistor for determining a current to be passed through the first path in response to the video signal to be transmitted;
A first switching means which is on a second path connecting the video signal line and the gate terminal of the driving transistor and connects or blocks the second path by the scanning signal applied to the gate terminal. When,
Second switching means on the first path for connecting or blocking the first power supply line and the driving transistor;
Third switching means for connecting the gate terminal of the driving transistor and the drain terminal of the driving transistor in the first period and blocking in the second and third periods;
A first capacitor provided between a gate terminal of the driving transistor and a source terminal of the driving transistor is interposed on the second path, and one end thereof is used as the first switching means. And a second capacitor connected at the other end to the gate terminal of the driving transistor,
In the first period of the predetermined first to third periods, the first and second switching means are controlled to be cut off, and the third switching means is connected. A first step of controlling;
A second step of controlling to connect to the first switching means and to cut off to the third switching means according to the scanning signal in the second period;
And a third step of controlling the first and third switching means to be shut off and controlling to connect to the second switching means in the third period. To do.

  According to the first invention, the gate-source voltage of the driving transistor is held and stabilized by the first capacitor provided between the gate terminal and the source terminal of the driving transistor. Even with this deterioration over time, the gate-source voltage of the driving transistor can be maintained at a desired value by the first capacitor, and high-quality display can be performed.

  According to the second aspect of the invention, the first capacitor can be easily configured, and the capacitance value is larger than the capacitance value between the gate and the drain of the driving transistor, so that the gate potential of the driving transistor is stabilized. can do.

  According to the third aspect of the present invention, the source electrode and the drain electrode of the driving transistor are appropriately arranged in relation to the gate electrode to increase the capacity of the first capacitor. The gate potential can be stabilized.

  According to the fourth invention, the capacity of the first capacitor can be easily increased by utilizing the multi-finger type configuration.

  According to the fifth aspect of the invention, the fourth switching means can connect the connection point of the second capacitor and the third power supply line in order to make the driving transistor compensate the threshold voltage. Without using the switching means, it is possible to realize the compensation action even outside the selection period based on the scanning signal.

  According to the sixth invention, the third and fourth switching means, which are transistors, are turned on and off at the same time, so that the gate length, the gate width, and the parasitic capacitance thereof are formed to be approximately equal, so that these transistors Therefore, the influence on the second capacitor can be eliminated.

According to the seventh aspect, since the source potential of the driving transistor is quickly reset to the potential of the third power supply line, the compensation action can be reliably realized within the first period, and Unlike the first power supply wiring through which a large amount of current flows, by applying an initial voltage from the third power supply line through which almost no current flows, it is possible to suppress a decrease in luminance and variations in luminance due to a voltage drop.

  According to the eighth aspect of the invention, high-quality display can be performed while suppressing the above-described decrease in luminance of a display device using an organic EL element that is a typical electro-optic element that causes a decrease in luminance due to deterioration over time.

  According to the ninth aspect, by using a general insulated gate field effect transistor, at least one of the driving transistor and the second switching means can be easily configured.

  According to the tenth aspect, since the first to third switching means are thin film transistors, a thin and high-definition display device can be obtained.

  According to the eleventh aspect, since all are n-channel transistors, it is possible to avoid complication of the production process, and transistors having the same channel polarity are arranged closer to each other than transistors having different channel polarities. Therefore, the circuit can be further downsized or the light emitting area can be increased.

  According to the twelfth aspect, by using amorphous silicon, the manufacturing cost can be reduced and the display section can be enlarged.

  According to the thirteenth aspect, the same effect as that of the first aspect can be achieved in the display device control method.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall Configuration and Operation of Display Device>
FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention. The display device 101 includes a display control circuit 112, a source driver circuit (also referred to as “column electrode driving circuit” or “video signal line driving circuit”) 111, and a gate driver circuit (“row electrode driving circuit” or “scanning signal”. 103) and an active matrix type display portion (organic EL panel) 113.

  The display unit 113 as a display unit in the display device includes n (n is a natural number) gate lines (“scanning signal”) corresponding to horizontal scanning lines in an image represented by image data Dv received from a CPU or the like in an external computer. Line ”or“ row electrode ”), m source lines (also referred to as“ video signal lines ”or“ column electrodes ”) that intersect each of the n gate lines (where m is a natural number), and and a plurality of pixel formation portions provided corresponding to the intersections of the n gate lines and the m source lines. The configuration of each pixel formation portion is basically the same as that in a conventional active matrix display device (details will be described later).

  In the present embodiment, image data (in a narrow sense) representing an image to be displayed on the display unit 113 and data for determining the timing of a display operation (for example, data indicating the frequency of a display clock) (hereinafter referred to as “display control data”). Is sent to the display control circuit 112 from a CPU or the like in an external computer (hereinafter, these data Dv sent from the outside are referred to as “broadly defined image data”). That is, an external CPU or the like supplies image data and display control data (narrow sense) constituting image data Dv in a broad sense to the display control circuit 112 by supplying an address signal ADw, and a display memory in the display control circuit 112 and Write to each register.

  The display control circuit 112 is based on the display control data written in the register, the clock signal CK, the start pulse signal SP, and the latch pulse signal LP given to the source driver circuit 111 for display, and the gate driver circuit 103 for display. And various signals including a clock signal YCK, a start pulse signal YI, and a predetermined timing signal OE. Since these signals are publicly known, detailed description is omitted.

  As described above, the data representing the image to be displayed on the display unit 113 is supplied to the source driver circuit 111 as the digital image signal DA in units of pixels, and the clock signal CK and the source start signal are used as signals indicating timing. A pulse signal SP is supplied. Based on the digital image signal DA, the clock signal CK, the source start pulse signal SP, and the latch pulse signal LP, the source driver circuit 111 drives a video signal for driving the display unit 113 (hereinafter referred to as “driving video signal”). Is also applied to each source line of the display unit 113.

  More specifically, the source driver circuit 111 includes an m-bit shift register 104, m registers 108, m latch circuits 107, and m D / A converters 110. In the source driver circuit 111, the shift register 104 includes m registers connected in cascade, and the start pulse SP input to the first register included in the display control circuit 112 is sequentially synchronized with the clock CLK. The data is transferred and output from each output stage to the register 108 as a timing pulse DLP. Display data DA is input from the display control circuit 112 to the register 108 at the timing when the timing pulse DLP is input. When the display data DA is stored for one display row in the register 108, the display data DA for one row is input to the latch circuit 107 in synchronization with the latch pulse LP input from the display control circuit 112 to the latch circuit 107. Is done. Each of the display data DA held in the latch circuit 107 is output to the corresponding D / A converter 110. One D / A converter 110 is provided corresponding to each source line, and the display data DA input from the latch circuit 107 is supplied to the corresponding source line as an analog voltage signal.

  The source driver circuit 111 employs a so-called line-sequential driving method, which is a driving method for transmitting data to a pixel circuit corresponding to one gate line at a time. You may employ | adopt what is called a dot sequential drive system which is a drive system which transmits data sequentially.

  Based on the clock signal YCK, the start pulse signal YI, and a predetermined timing signal OE, the gate driver circuit 103 scans to be applied to each gate line in order to sequentially select the gate lines in the display unit 113 by one horizontal scanning period. Signals G1, G2, G3,... Are generated, and application of an active scanning signal for sequentially selecting all the gate lines to each gate line is repeated with one vertical scanning period as a cycle.

  More specifically, the gate driver circuit 103 includes a shift register circuit, a logic operation circuit, and a buffer (not shown). In the gate driver circuit 103, the input start pulse signal YI is sequentially transferred in the shift register circuit in synchronization with the clock signal YCK, and the pulse output from each output stage of the shift register circuit by the logic operation circuit. And a timing signal OE, a predetermined logical operation is performed, and a predetermined voltage signal is output to the corresponding gate line and control wirings Wi and Ri through the buffer. Each gate line is connected to m pixel circuits, and the pixel circuit is selected by the gate line Gi to be connected.

  In the display unit 113, the video signals S1, S2, S3,... For driving based on the digital image signal DA are applied to the source line by the source driver circuit 111 as described above, and the gate driver circuit 103 is applied to the gate line. The scanning signals G1, G2, G3,. Thereby, the display unit 113 displays an image represented by the image data Dv received from an external CPU or the like.

<1.3 Configuration and operation of display unit>
Next, the configuration of the display unit 113 and the configuration of the pixel formation unit arranged thereon will be described with reference to FIG. Here, FIG. 2 shows an equivalent circuit of the pixel formation portion P (i, j) in the display portion 113. Note that i is a natural number of n or less, and j is a natural number of m or less.

  As shown in FIG. 2, each pixel formation portion P (i, j) (hereinafter also abbreviated as “pixel circuit Aij”) includes four switching elements, first to fourth switching TFTs 11 to 14, and organic An EL element 16, a driving TFT 15 for driving the organic EL element 16, and first and second capacitors 17 and 18 are provided.

  The first to fourth switching TFTs 11 to 14 and the driving TFT 15 are n-channel transistors, and may be composed of low-temperature polysilicon, CG (Continuous Grain) silicon, or amorphous silicon. Since the configuration and the creation process are well known, the description thereof is omitted here. However, if all TFTs are of n-channel type, it is possible to avoid complication of the production process such as providing a mask for each channel, and transistors with the same channel polarity are brought closer to each other than transistors with different channel polarities. Therefore, the circuit can be further downsized or the light emitting area can be increased.

  Moreover, since the structure of an organic EL element, a creation process, etc. are well known, the description is abbreviate | omitted here. Further, as shown in FIG. 2, the pixel circuit Aij includes a power supply wiring Vp functioning as a first wiring, a common cathode Vcom functioning as a second wiring, and a reference power supply wiring functioning as a third wiring. Vref (or a cathode wiring CAi that functions as a third wiring (not shown)) is disposed, and control wirings Ri and Wi are disposed. This will be described later.

  The first switching TFT 11 has a gate terminal connected to the gate line Gi passing through the intersection corresponding to the pixel circuit Aij and a source terminal connected to the source line Sj passing through the intersection.

  When the scanning signal applied to the gate line Gi becomes active, the first switching TFT 11 is selected and becomes conductive. A voltage corresponding to the driving video signal is applied to the gate terminal of the driving TFT 15 via the source line Sj. Thereby, a current corresponding to the voltage of the applied driving video signal is transferred from the drain terminal of the driving TFT 15 connected to the power supply wiring Vp to the source terminal of the driving TFT 15 connected to the anode terminal of the organic EL element 16. The organic EL element 16 emits light with a desired luminance corresponding to the current flowing to the common cathode Vcom connected to the cathode terminal. The first capacitor 17 is connected between the gate terminal and the source terminal of the driving TFT 15, and this function will be described later in detail.

  The third switching TFT 13 has its gate terminal connected to the control wiring Ri, its drain terminal (or source terminal) connected to the drain terminal of the driving TFT 15, and its source terminal (or drain terminal) connected to the driving TFT 15. Is connected to the gate terminal.

  The second switching TFT 12 has its gate terminal connected to the control wiring Ri, its drain terminal connected to the power supply wiring Vp, and its source terminal connected to the drain terminal of the driving TFT 15.

  The fourth switching TFT 14 has its gate terminal connected to the control wiring Wi, its drain terminal connected to the source terminal of the first switching TFT 11, and its source terminal for supplying a reference voltage. Connected to the power supply wiring Vref.

  A constant predetermined potential VDD is applied to the power supply wiring Vp from a power supply unit (not shown). Similarly, a constant predetermined potential VSS (where VDD> VSS) is applied to the common cathode Vcom. The common cathode Vcom is an electrode common to the organic EL elements in each pixel circuit.

  Here, as shown in FIG. 2, the second switching TFT 12, the driving TFT 15, and the organic EL element 16 have a current path from the power supply wiring Vp to the common cathode Vcom (hereinafter, this path is referred to as "first path"). 1 ”) in series. A connection point between the driving TFT 15 (source terminal thereof) and the organic EL element 16 on the first path is called a connection point B, and a voltage at the connection point (node) is a voltage Vs.

  Further, as shown in FIG. 2, the first switching TFT 11, the second capacitor 18, and the gate terminal of the driving TFT 15 are connected to a current path from the source line Sj (hereinafter, this path is referred to as a "first path"). Are arranged in series in order. A connection point between the source terminal (or drain terminal) of the first switching TFT 11 on the second path and one end of the second capacitor 18 is referred to as a connection point A.

  FIG. 3 is a timing chart showing the operation of the display unit 113 focusing on the pixel circuit Aij. The pixel circuit Aij is controlled by receiving a driving video signal from the source driver circuit 111 and a scanning signal from the gate driver circuit 103 based on various control signals supplied from the display control circuit 112 described above. .

  FIG. 3 shows the potential change timing of the voltage signal applied to the gate line Gi, the control wirings Wi and Ri, and the source line Sj. First, at time t1, the potential of the control wiring Wi is GH (High). That is, since the signal flowing through the control wiring Wi is active, the third switch TFT 13 and the fourth switch TFT 14 are in a conductive state. As a result, the potential at the connection point A becomes the potential of the power supply line Vref. Further, when the third switching TFT 13 becomes conductive, the potential of the gate terminal of the driving TFT 15 becomes VDD. Further, the potential of the control wiring Ri is GL (Low). That is, since the signal flowing through the control wiring Ri is inactive, the second switch TFT 12 is in a non-conductive state.

  During the period from time t1 to time t2 when the potential of the control wiring Wi becomes GL, current flows to the organic EL element 16 through the driving TFT 15 when the third switching TFT 13 becomes conductive. The electric charge held in the TFT 15 is discharged. For this reason, the potential at the gate terminal of the driving TFT 15 gradually decreases, and the potential at the gate terminal of the driving TFT 15 finally becomes a value corresponding to the threshold voltage Vth of the driving TFT 15 (ie, the source voltage Vs of the driving TFT 15). When the threshold voltage Vth is added), the driving TFT 15 is turned off. As described above, the gate potential of the driving TFT 15 shifts toward the threshold voltage Vth in a so-called self-compensation manner, so that variations in the threshold voltage of the TFT are automatically compensated. Due to this compensation action, no matter what threshold voltage the driving TFT 15 has, the driving TFT 15 is in the threshold state during the period from the time t1 to the time t2 (that is, the first period T1 shown in FIG. 3). It can be. The gate potential of the driving TFT 15 at this time is stored by the first capacitor 17 when the driving TFT 15 is turned off.

  Next, when the potential of the control wiring Wi becomes GL at time t2, the third switch TFT 13 and the fourth switch TFT 14 are turned off. Therefore, the second capacitor 18 can hold a potential corresponding to the threshold voltage of the driving TFT 15.

  Here, when the potential of the control wiring Wi changes from GH to GL in the vicinity of time t2, the third switching TFT 13 and the fourth switching TFT 13 and the fourth switching TFT 14 are caused by the parasitic capacitance of the third switching TFT 13 and the fourth switching TFT 14. The gate potential of the switching TFT 14 may fluctuate, and this potential change may be applied as noise to the potential across the second capacitor 18. Therefore, in the present embodiment, the third switch TFT 13 and the fourth switch TFT 14 have the same size. Specifically, these TFTs have the same gate length, gate width, and parasitic capacitance. By doing so, it is possible to prevent the potential held by the second capacitor 18 at the connection point B from being affected.

  At this time, the potential of the connection point A is the potential of the power supply line Vref (hereinafter abbreviated as Vref), and the potential difference held in the second capacitor 18 is Vs + Vth− when the potential on the source line Sj side is used as a reference. The voltage obtained by Vref. Therefore, in order to control so that a desired current flows through the driving TFT 15, the gate-source voltage of the driving TFT 15 may be changed thereafter from the threshold voltage to a voltage corresponding to the desired current. .

  Therefore, by setting the potential of the gate line Gi to GH at time t3, the first switching TFT 11 is turned on, and the driving TFT 15 in which a desired current flows through the organic EL element 16 through the source line Sj. The source driver circuit 111 supplies a potential Da set so as to obtain the potential of the gate terminal.

At this time, the potential Vda of the gate terminal of the driving TFT 15 can be expressed by the following equation (1). Ca is the capacitance value of the first capacitor 17, and Cb is the capacitance value of the second capacitor 18.
Vda = (Vs + Vth−Vref) + Da {Ca / (Ca + Cb)} (1)

  As described above, the threshold voltage Vth of the driving TFT 15 in each pixel circuit is compensated for the voltage corresponding to each driving TFT 15 in the first period T1 from time t1 to time t2. The flowing current is determined according to the potential difference between Vref and Da without being affected by variations in the threshold voltage Vth.

  As described above, since the channel polarity of the driving TFT 15 is n-type, the relationship of Da ≧ Vref is satisfied, and the current flowing through the driving TFT 15 increases as the potential of Da increases.

  Next, by setting the potential of the gate line Gi to GL at time t4, the first switching TFT 11 is made non-conductive, and thereby the first capacitor 17 is set so that the potential at the connection point A becomes the data potential Da. The above potential difference is maintained. Therefore, the potential of the gate terminal of the driving TFT 15 is held at the potential Vda through which a desired current flows, and so-called display data programming is completed. That is, the program is performed during a period from time t3 to time t4 when the potential of the gate line Gi is GH (that is, the second period T2 shown in FIG. 3).

  Finally, by setting the potential of the control wiring Ri to GH at time t5, the second switch TFT 12 is turned on, and thereby a desired current flows from the driving TFT 15 to the organic EL element 16. Therefore, the organic EL element 16 emits light with a luminance corresponding to the designated display data. A period from time t5 to the next time point when the control wiring Wi becomes GH (that is, the third period T3 shown in FIG. 3) is a period in which the organic EL element emits light with luminance corresponding to the designated display data. .

  As described above, this pixel circuit can compensate for the threshold voltage variation of the driving TFT 15, but can also compensate for a decrease in luminance due to aging of the organic EL element. This will be described in detail below.

  As described above, it is known that the organic EL element has a high resistance due to aging. That is, in a general pixel circuit, even when the same current flows through the organic EL element as before the aging deterioration, the driving voltage applied to both ends of the organic EL element after the aging increases, so that the emission luminance decreases. End up.

  However, in the pixel circuit in the present embodiment, the gate potential rises as the source potential of the driving TFT 15 rises by the first capacitor 17 whose both ends are connected to the source terminal and gate terminal of the driving TFT 15. That is, as shown in the above equation (1), when the source terminal voltage Vs of the driving TFT 15 that is the voltage at the connection point B increases, the potential Vda of the gate terminal of the driving TFT 15 increases by the same voltage. Therefore, when the same analog signal voltage Da is applied to the pixel circuit before and after the organic EL element 16 deteriorates over time, the gate-source voltage of the driving TFT 15 does not change, so that the driving TFT 15 operates in the saturation region. As long as the same current can be supplied to the organic EL element 16. Therefore, it is possible to compensate for a decrease in luminance due to aging of the organic EL element.

  As described above, the first capacitor 17 has a function of stabilizing the gate-source voltage of the driving TFT 15, but the parasitic capacitance between the gate and drain of the driving TFT 15 is the gate potential of the driving TFT 15. It becomes a factor to fluctuate. For example, when the potential of the control line Ri changes from GL to GH, the potential fluctuation is caused by the parasitic capacitance between the gate and the source of the second switching TFT 12 and the parasitic capacitance between the gate and the drain of the driving TFT 15. (That is, using these parasitic capacitances as paths), the gate potential of the driving TFT 15 is changed. Therefore, the capacitance of the first capacitor 17 that forms the capacitance between the gate and the source of the driving TFT 15 is preferably larger than the parasitic capacitance between the gate and the drain of the driving TFT 15, and further, the first capacitor 17 is as much as possible. More preferably, the capacitance of the gate TFT and the drain capacitance of the driving TFT 15 is small. Therefore, the first capacitor 17, which is a capacitive element having a relatively large capacitance, may be connected between the gate and source of the driving TFT 15, but the driving TFT 15 of the present embodiment is for realizing this. It has a special structure different from the conventional one. Hereinafter, a description will be given with reference to FIGS.

  FIG. 4 is a simple plan view of a pixel formation portion including such a driving TFT as viewed from a direction perpendicular to the plane of the display portion. As shown in FIG. 4, the pixel forming portion P (i, j) includes each element and each wiring in a region sandwiched between the source line Sj and the power supply wiring Vp. Since it is the same as each element and each wiring included in the pixel circuit shown in FIG. 2, its description is omitted. These arrangement relationships are well known except for the first capacitor 17, and the structure of the first capacitor 17 will be described in more detail.

  The first capacitor 17 is formed between the gate and the source of the driving TFT 15, and this driving TFT 15 is a so-called multi-finger type field effect transistor. FIG. 5 is a diagram showing an equivalent circuit of the multi-finger type driving TFT 15. As shown in FIG. 5, this driving TFT 15 has two sources for one drain. By adopting such a multi-finger type, the source region is wider than the drain region. can do. In addition, with such a multi-finger type configuration, the driving TFT 15 can reduce its gate resistance, and since the channel is divided into a plurality of elements, the element characteristics can be averaged and the characteristic variation can be reduced. Furthermore, it is possible to make the shape easy to fit in the pixel forming portion having a normal rectangular planar shape.

  In addition to the above configuration, the driving TFT 15 further arranges the source electrode and the drain electrode at suitable positions so that the area of the overlapping region between the source region and the gate region is reduced to the overlapping region between the drain region and the gate region. It is comprised so that it may become larger than the area of. Hereinafter, with reference to FIG. 6 and FIG. 7, the difference in the size of the overlapping region will be described.

  FIG. 6 is a plan view simply showing the configuration of the driving TFT 15. As shown in FIG. 6, the driving TFT 15 is provided so that many portions of the source electrode 56 overlap with the gate electrode 58, but the drain electrode 57 hardly overlaps with the gate electrode 58. It is provided as follows. Further, FIG. 7 shows a sectional view of the driving TFT 15 cut in the left-right direction of FIG.

  FIG. 7 is a partial cross-sectional view of the pixel formation portion including the driving TFT 15. This cross-sectional view corresponds to a cross-sectional view in which the vicinity of the driving TFT 15 included in the pixel formation portion P (i, j) shown in FIG. 4 is cut in the direction along the source line Sj (or the power supply wiring Vp). Referring to FIG. 7, in the pixel forming portion, a gate electrode 58 is formed on a glass substrate 61, and an amorphous silicon thin film 59 serving as an active layer is formed with a gate insulating film interposed therebetween. A wiring layer such as a source electrode 56 and a drain electrode 57 is formed thereon, and a planarizing film 55 for planarizing the surface is formed. A light shielding layer 54 is formed inside the planarizing film 55. Further, a transparent conductive film 53 made of, for example, ITO (Indium Tin Oxide) to be the anode electrode of the organic EL element 16 is formed, and after the insulating film 52 is formed in a portion not containing the organic EL material or the like, the transparent conductive film 53 is further formed. A metal conductive layer 51 to be a cathode electrode (common cathode Vcom) of the organic EL element 16 is formed thereon. Although not shown, a hole transport layer made of, for example, α-NPD or the like is formed on the transparent conductive film 53 in a portion corresponding to the organic EL element 16, and further a fluorescent material is formed thereon. A light-emitting layer made of a known organic light-emitting material is formed, and a well-known electron transport layer and electron injection layer are formed thereon, and then a metal conductive layer 51 is formed. Since such a manufacturing process is well known, detailed description thereof is omitted. By using amorphous silicon as the silicon thin film, the manufacturing cost can be reduced and the display portion can be enlarged.

  Here, as shown in FIG. 7, the source electrode 56 is provided so as to largely cover the upper portion of the gate electrode 58 so as to overlap the gate electrode 58 in many portions. Is provided so as not to cover the upper portion of the gate electrode 58 so as not to overlap the gate electrode 58. Therefore, the area of the overlapping region between the source region and the gate region can be made much larger than the area of the overlapping region between the drain region and the gate region. As a result, the capacitance of the first capacitor 17 formed between the gate electrode and the drain electrode of the driving TFT 15 can be made as large as possible than the parasitic capacitance between the gate and the drain of the driving TFT 15. Therefore, the gate-source voltage of the driving TFT 15 can be stabilized.

<1.4 Effect>
As described above, in this embodiment, the capacitance of the first capacitor 17 formed between the gate electrode and the drain electrode of the driving TFT 15 can be made larger than the parasitic capacitance between the gate and the drain of the driving TFT 15. By making it as large as possible, the gate-source voltage of the driving TFT 15 is stabilized, thereby minimizing the influence of noise based on the parasitic capacitance in the driving TFT 15 and deterioration of the organic EL element 16 over time. Therefore, the gate-source voltage of the driving TFT 15 can be maintained at a desired value by the first capacitor 17 and high-quality display can be performed.

<2. Second Embodiment>
The configuration of the display device according to the present embodiment is the same as the configuration of the display device according to the first embodiment shown in FIG. In addition, since the configuration of the pixel circuit in the present embodiment is substantially the same as the configuration of the pixel circuit in the first embodiment shown in FIG. 2, the same components are denoted by the same reference numerals and description thereof is omitted. Only the different points will be described below with reference to FIG.

  FIG. 8 shows an equivalent circuit of the pixel formation portion P (i, j) in the second embodiment. As shown in FIG. 8, the pixel circuit is further provided with a fifth switching TFT 25 in addition to the pixel circuit in the first embodiment. Since the potential of the control wiring Wi is GH at the time t1 shown in FIG. 3, the fifth switching TFT 25 becomes conductive. Thus, the potential at the connection point B (that is, the source potential Vs of the driving TFT 15) becomes the potential of the power supply line Vref. As described above, the source potential Vs of the driving TFT 15 is quickly reset to the potential of the power supply line Vref before the gate potential of the driving TFT 15 in the period T1 shifts toward the threshold voltage Vth in a self-compensating manner. The compensation operation can be surely realized within the period T1, and the luminance is reduced by a voltage drop by applying an initial voltage from the power supply line Vref in which little current flows unlike the power supply wiring Vp in which a large amount of current flows. And luminance variation can be suppressed.

<3. Modification>
In the present embodiment, an organic EL element is used as an electro-optical element. However, the present invention is not limited to this, and any current-driven electro-optical element may be used. Therefore, a light emitting part of a semiconductor LED (Light Emitting Diode) or an FED (Field Emission Display) can be used as an electro-optical element installed in the pixel circuit.

  Further, as the driving TFT 15, a MOS transistor (herein referred to as a MOS transistor including a silicon gate MOS structure) formed on an insulating substrate such as a glass substrate is used. The present invention can be applied to any voltage control type driving element that controls the output current by the control voltage applied to the element and that has a threshold voltage for determining the presence or absence of the output current in the control voltage. Therefore, a general insulated gate field effect transistor including a MOS transistor formed on a semiconductor substrate can be used.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the embodiments can be obtained by appropriately combining technical means disclosed in different embodiments. The form is also included in the technical scope of the present invention.

It is a block diagram which shows the structure of the display apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the equivalent circuit of the pixel formation part P (i, j) in the display part in the said embodiment. 4 is a timing chart showing the operation of the display unit focusing on the pixel circuit in the embodiment. It is the simple top view which looked at the pixel formation part containing the driving TFT in the said embodiment from the orthogonal | vertical direction with respect to the plane of a display part. It is a figure which shows the equivalent circuit of the multi-finger type drive TFT in the said embodiment. It is a top view which shows simply the structure of the drive TFT in the said embodiment. 4 is a partial cross-sectional view of a pixel formation portion including a driving TFT in the embodiment. FIG. It is a figure which shows the equivalent circuit of pixel formation part P (i, j) of the display apparatus which concerns on the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a configuration of a pixel circuit in a first conventional example and a timing chart showing its operation. It is a circuit diagram which shows the structure of the pixel circuit in a 2nd prior art example.

Explanation of symbols

11-14... First to fourth switching TFTs
15 ... TFT for driving
16 ... Organic EL element 17 ... First capacitor 18 ... Second capacitor 25 ... Fifth switch TFT
56 ... Source electrode 57 ... Drain electrode 58 ... Gate electrode 101 ... Display device 103 ... Gate driver circuit 104 ... Shift register 107 ... Latch circuit 108 ... Register 110 ... A / D converter 111 ... Source driver circuit 112 ... Display control circuit 113 ... Display section Gi ... Gate line Sj ... Source line Wi, Ri ... Control wiring Vcom ... Common cathode

Claims (13)

A plurality of pixel forming units including current-driven electro-optic elements for forming an image to be displayed; a plurality of video signal lines for transmitting a video signal representing the image to be displayed; and the plurality of video signal lines A plurality of scanning signal lines that are provided so as to intersect with each other and transmit a scanning signal for selecting the pixel forming portion, and first and second power supply lines for flowing current to the electro-optic element, An active matrix type display device in which a plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines,
The pixel forming unit includes:
The first power supply line and the second power supply line are provided in series so as to be connected to the source terminal of the electro-optic element on the first path connecting the first power supply line and the second power supply line, and applied to the gate terminal. A driving transistor for determining a current to be passed through the first path in response to the video signal to be transmitted;
The scanning that is provided on the second path connecting the video signal line and the gate terminal of the driving transistor and is given to the gate terminal in a second period among the predetermined first to third periods. First switching means for connecting or blocking the second path by a signal;
A second switching unit that is on the first path, connects the first power supply line and the driving transistor in the third period, and cuts off in the first period;
Third switching means for connecting the gate terminal of the driving transistor and the drain terminal of the driving transistor in the first period and blocking in the second and third periods;
A first capacitor provided between a gate terminal of the driving transistor and a source terminal of the driving transistor is interposed on the second path, and one end thereof is used as the first switching means. And a second capacitor connected at the other end to the gate terminal of the driving transistor.   The first capacitor is formed between a gate electrode corresponding to the gate terminal of the driving transistor and a source electrode corresponding to the source terminal of the driving transistor, and the gate-drain of the driving transistor The display device according to claim 1, wherein the display device has a capacitance value larger than a capacitance value therebetween.   The driving transistor is formed on a predetermined substrate, and has a first overlapping region between the gate electrode of the driving transistor and the source electrode of the driving transistor in a direction perpendicular to the substrate. And there is a second overlapping region between the gate electrode of the driving transistor and a drain electrode corresponding to the drain terminal of the driving transistor, the size of the second overlapping region is The display device according to claim 2, wherein the display device is smaller than one overlapping region.   The driving transistor is a multi-finger type having two or more source regions and one or more drain regions, wherein the number of the source regions is larger than the number of the drain regions. Item 4. The display device according to Item 3. A third power line to which a predetermined constant voltage is applied;
The pixel forming portion connects a connection point of the first switching means and the second capacitor and the third power supply line in the first period, and cuts off in the second and third periods. The display device according to claim 1, further comprising fourth switching means. The third and fourth switching means are transistors;
The fourth switching means is formed such that its gate length, gate width, and parasitic capacitance are substantially equal to the gate length, gate width, and parasitic capacitance of the third switching means, respectively. The display device according to claim 5, wherein: A third power line to which a predetermined fixed voltage is applied;
The pixel formation unit further includes fifth switching means for connecting the source terminal of the driving transistor and the third power supply line in the first period and blocking in the second and third periods. The display device according to claim 1, wherein:   The display device according to claim 1, wherein the electro-optical element is an organic EL (Electro Luminescence) element.   The display device according to claim 1, wherein at least one of the driving transistor and the second switching unit is an insulated gate field effect transistor.   The display device according to claim 1, wherein the driving transistor and the first to third switching units are thin film transistors.   The display device according to claim 10, wherein all of the thin film transistors are n-channel transistors.   The display device according to claim 10, wherein the thin film transistor is made of amorphous silicon. A plurality of pixel forming units including current-driven electro-optic elements for forming an image to be displayed; a plurality of video signal lines for transmitting a video signal representing the image to be displayed; and the plurality of video signal lines A plurality of scanning signal lines that are provided so as to intersect with each other and transmit a scanning signal for selecting the pixel forming portion, and first and second power supply lines for flowing current to the electro-optic element, A control method of an active matrix display device in which a plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
The pixel forming portion includes:
The first power supply line and the second power supply line are provided in series so as to be connected to the source terminal of the electro-optic element on the first path connecting the first power supply line and the second power supply line, and applied to the gate terminal. A driving transistor for determining a current to be passed through the first path in response to the video signal to be transmitted;
A first switching means which is on a second path connecting the video signal line and the gate terminal of the driving transistor and connects or blocks the second path by the scanning signal applied to the gate terminal. When,
Second switching means on the first path for connecting or blocking the first power supply line and the driving transistor;
Third switching means for connecting the gate terminal of the driving transistor and the drain terminal of the driving transistor in the first period and blocking in the second and third periods;
A first capacitor provided between a gate terminal of the driving transistor and a source terminal of the driving transistor is interposed on the second path, and one end thereof is used as the first switching means. And a second capacitor connected at the other end to the gate terminal of the driving transistor,
In the first period of the predetermined first to third periods, the first and second switching means are controlled to be cut off, and the third switching means is connected. A first step of controlling;
A second step of controlling to connect to the first switching means and to cut off to the third switching means according to the scanning signal in the second period;
And a third step of controlling the first and third switching means to be shut off and controlling to connect to the second switching means in the third period. A display device control method.

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