JP2008066734A - Nonvolatile memory structure and method of forming the same - Google Patents

Abstract

Non-volatile memory structures and methods of forming the same are provided.
A non-volatile memory structure includes a plurality of charge storage patterns. An electrical coupling distance Lc between adjacent charge storage patterns is formed to be greater than a linear geometric distance Ls between adjacent charge storage patterns.
[Selection] Figure 3A

Description

  The present invention relates to a storage device, and more particularly, to a non-volatile, electrically erasable semiconductor memory device, such as a flash memory device, and a method of manufacturing the same.

  Nonvolatile memory retains information stored in memory cells even when the power is turned off. Non-volatile memories include mass chrome, EP ROM, and EEPROM ROM.

  Non-volatile memory is a variety of electronic products such as personal computers, portable information terminals (PDAs), mobile phones, digital still image cameras, digital video cameras, video game machines, memory cards, and other electronic devices. Widely used for etc.

  Memory cards include multimedia cards, SD cards, compact flash (registered trademark) cards, memory sticks, smart media cards, and extreme digital cards.

  Among non-volatile memory devices, flash memory is widely used. A flash memory is classified into a NOR type and a NAND type according to a connection structure of cells and bit lines. NOR type flash memory is often used for code memory because reading speed is fast and writing speed is slow. NAND-type flash memory is often used for a large number of storage devices because of its high writing speed and low cost per unit area. In order to write data to the flash memory, an erasing operation is performed first. The flash memory has a characteristic that the erase unit is larger than the write unit.

  The program and erase operations are basic operations of the NAND element, and will be described with reference to FIGS. 1A and 1B. As can be seen from FIGS. 1A and 1B, a high electric field is generated between the floating gate and the channel region. If the charge moves along one direction or the other direction of the tunneling oxide film, the threshold voltage Vth of the memory cell changes.

  The read operation is a basic operation of the NAND element. As can be seen from FIG. 1C, the control gate and the substrate are connected to ground. If the cell is a programmed cell (Vth> 0), the cell is off and the data value is zero. If the cell is an erased cell (Vth <0), the cell is on and the data value is 1.

  FIG. 2A is a wiring diagram and a plan view of a NAND flash memory cell according to the prior art. The NAND flash memory cell includes a string selection line SLL, a ground selection line GSL, a common source line CSL, a direct contact DC, a plurality of word lines WL, a plurality of bit lines BL, a charge storage film SA, an active region 113, and an element isolation region 115. including.

  FIG. 2B is a cross-sectional view of the NAND flash memory cell according to the prior art with respect to the direction of the bit line BL and the direction of the word line WL. The conventional NAND flash memory cell includes a tunnel insulating layer, a charge storage layer, a blocking layer, and a control gate layer. The charge storage film is a floating gate film. Floating gate interference is a transition in the threshold voltage of a cell that is proportional to the change in the threshold voltage of an adjacent cell. The charge storage film is a charge trap film.

  2C is a cross-sectional view of a conventional NAND flash memory cell with respect to the word line direction, and FIG. 2D is a cross-sectional view taken along line A-A 'of FIG. 2C. As shown, the conventional flash memory cell includes a substrate 11, an active region 13, a device isolation region 15, a tunnel insulating film 31, a floating gate 32, a blocking insulating film 34, and a control gate 35.

  As the size of the memory cell is further reduced, the distance between the floating gates 32 is further reduced. As the distance between the floating gates 32 decreases, the parasitic capacitance C increases. In addition, since the boundary between adjacent floating gates 32 faces each other as shown in FIG. 2D, the parasitic capacitance C increases.

  The present invention provides a nonvolatile memory structure having a structure in which parasitic capacitance between floating gates is reduced.

  The present invention provides a method for manufacturing a non-volatile memory structure having a structure in which parasitic capacitance between floating gates is reduced.

  The present invention provides a non-volatile memory structure. The structure includes a plurality of charge storage patterns, and the electrical coupling distance Lc between adjacent charge storage patterns is greater than the linear geometric distance Ls between the adjacent charge storage patterns.

At least one of the plurality of charge storage patterns having a width of W _{1 in} a bit line direction and having a lower surface higher than an upper surface of the plurality of charge storage patterns; the positioned below the plurality of upper control gate further comprises a control gate comprising a plurality of lower control gate, at least one among the plurality of lower control gate has a width of W ₂ in the direction of the bit lines, a _{W 2>} W _1.

The plurality of charge storage patterns that occupy most have a width of W ₁ in the direction of the bit line, and the plurality of lower control gates that occupy most of the width have a width of W ₂ in the direction of the bit line. And W ₂ > W ₁ .

  At least one side wall of the plurality of lower control gates has a sloped surface projecting outward.

  The slope surface projecting outward is a form having a curve, a straight line, or a step.

  At least one sidewall of the plurality of lower control gates and at least one sidewall of the plurality of charge storage patterns have different slope surfaces.

  At least one sidewall of the plurality of charge storage patterns is further vertical than at least one sidewall of the plurality of lower control gates.

  Among the plurality of lower control gates, at least one side wall protrudes in the plurality of charge storage patterns as compared to at least one side wall, and the protruding portion is in the plurality of charge storage patterns. At least one side wall is prevented from facing the side wall of the adjacent charge storage pattern.

  At least one of the sidewalls of the plurality of lower control gates protrudes compared to a mask pattern used to form the plurality of upper control gates.

  The protruding portion is in the form of a spacer.

  At least one sidewall of the plurality of charge storage patterns is recessed relative to at least one sidewall of the plurality of lower control gates, and the recessed portion is at least one of the plurality of charge storage patterns. One side wall is prevented from facing the side wall of the adjacent charge storage pattern.

  At least one of the sidewalls of the plurality of lower control gates is recessed compared to a mask pattern used to form the plurality of upper control gates.

  A substrate including an active region under the plurality of charge storage patterns and a device isolation region under and between the plurality of charge storage patterns; a tunnel insulating layer on the active region; and the plurality of charge storage patterns And a blocking insulating layer on the isolation region of the device.

  A mask layer is further included on the plurality of upper control gates.

  The substrate is a bulk silicon substrate, a silicon-on-insulator substrate, or a stacked substrate.

  The blocking insulating film is made of any one of silicon oxide, silicon nitride, hafnium aluminate, HfAlO, HfAlON, hafnium silicate, HfSiO, and HfSiON.

  The plurality of charge storage patterns are a dot film, a charge trap film, or a conductive film.

  The control gate is made of polysilicon or polysilicon and metal silicide.

  The doping concentration of the plurality of charge storage patterns is greater than the doping concentration of the control gate.

  The present invention also provides a method for forming a non-volatile memory structure. The method includes forming a plurality of charge storage patterns, and an electrical coupling distance Lc between the plurality of charge storage patterns is a linear geometric distance between the plurality of charge storage patterns. Greater than Ls.

At least one has a width of W ₁ in the direction of the bit lines, a plurality of upper control gate and said with a high bottom surface than the top surface of said plurality of charge storage pattern among the plurality of electronic storage pattern And forming a control gate including a plurality of lower control gates located below the plurality of upper control gates, wherein at least one of the plurality of lower control gates has a width of W ₂ in the direction of the bit line. And W ₂ > W ₁ .

  Forming the control gate includes forming a blocking insulating film on the plurality of charge storage patterns, forming a control gate film on the blocking insulating film, and on the control gate film. Forming a mask pattern, and etching the control gate layer using the mask pattern to form the plurality of upper control gates and the plurality of lower control gates.

  Forming the plurality of charge storage patterns includes forming a pad oxide film on the substrate, forming a mask pattern on the pad oxide film, and forming a trench defining an active region. Etching the substrate, filling the trench to form an isolation region, removing the mask pattern and the pad oxide film to expose the active region, and exposing the exposed active region. Forming a tunneling insulating film on the region; and forming the plurality of charge storage patterns on the tunneling insulating film.

  Etching the control gate film includes etching the control gate film until the blocking insulating film is exposed, and exposing a sidewall of the plurality of upper control gates and an upper part of the control gate film. Etching and etching the control gate film with an etching gas.

  The method further includes repeating polymer etching and etching of the control gate film with the etching gas.

  The etching gas contains carbon.

  The plurality of charge storage patterns are a plurality of floating gates, and forming the plurality of floating gates includes forming a gate oxide film, a polysilicon film and a nitride film on a substrate, a nitride film pattern, The gate oxide film, the polysilicon film and the nitride film are patterned to form a floating gate pattern and a gate oxide film pattern including the plurality of floating gates, and a trench defining an active region is formed. For this purpose, the method includes etching an exposed portion of the substrate, forming a trench oxide film inside the trench, and filling the trench with a field oxide film to form an isolation region.

  Forming the control gate includes forming an interlayer dielectric film on the plurality of floating gates, forming a control gate film on the interlayer dielectric film, and forming a mask pattern on the control gate film. Forming the plurality of upper control gates and the plurality of lower control gates using the mask pattern to form the plurality of upper control gates and the plurality of lower control gates.

  Patterning the polysilicon film to form the floating gate pattern includes doping the polysilicon film with a first concentration level impurity and doping the control gate film with a second concentration level impurity. The second concentration level is higher than the first concentration level.

  Etching the control gate film using the mask pattern to form the plurality of upper control gates and the plurality of lower control gates includes etching the control gate films at a plurality of different etching rates. including.

  The plurality of charge storage patterns are charge trapping films, and the formation of the charge trapping film includes forming a tunneling film, a memory storage film and a blocking film on the substrate, a tunneling film pattern, Patterning the tunneling film, the memory storage film and the blocking film to form a memory storage pattern including a trap film and a blocking film pattern; and exposing the substrate to form a source region and a drain region. Implanting ions into the part.

In addition, the present invention provides other methods of forming non-volatile memory structures. The method includes forming a pad oxide film on a substrate, forming a mask pattern on the pad oxide film, etching the substrate to form a trench or the like defining an active region, The trench and the like are filled to form an isolation region, the mask pattern and the pad oxide film are removed to expose the active region, and a tunneling insulating film is formed on the exposed active region. Forming a plurality of charge storage patterns on the tunneling insulating film, forming a blocking insulating film on the plurality of charge storage patterns, and a control gate film on the blocking insulating film Forming a mask pattern on the control gate film, the plurality of upper control gates and the plurality of lower control gates. Etching the control gate layer using the mask pattern to form a gate, and the plurality of upper control gates have a lower surface higher than an upper surface of the plurality of charge storage patterns; The plurality of lower control gates are positioned below the plurality of upper control gates, and at least one of the plurality of lower control gates has a width of W _{2 in} the bit line direction, and W ₂ > a W _1.

  According to an embodiment of the present invention, a protrusion is formed on a side surface of the control gate so that the control gate has a width wider than that of the charge storage pattern. Capacitive coupling can be effectively suppressed. Thereby, the parasitic capacitance is reduced and the operation characteristics of the nonvolatile memory structure are further improved.

  Hereinafter, the technical configuration of the present invention will be described in detail with reference to the accompanying drawings in which embodiments of the present invention are illustrated. However, the present invention is not limited to the embodiment and the like, and can be embodied in other forms. Rather, embodiments and the like of the present invention are provided so that the contents of the present invention can be well understood, and for those skilled in the art to fully convey the idea of the present invention.

  For example, in the embodiments of the present invention, a floating gate type flash memory device is described from an exemplary viewpoint. However, the present invention is not limited to this example, and can be applied to various memory devices such as a charge trap type flash memory device. The thicknesses of the layers and regions in the drawings have been exaggerated for purposes of illustration. Also, when a layer is described “on” another layer or substrate, it can be formed directly on the other layer or substrate, or a third layer can be interposed between the layers.

  In various embodiments of the present invention, the first, second, and third terms are used to describe various parts, materials, etc., but the parts and materials are not limited by the same terms. . The term is only used to distinguish a given part from a part.

  Accordingly, what is defined as the first part in one embodiment may be defined as the second part in other embodiments.

  FIG. 3A is a perspective view of a nonvolatile memory structure according to an embodiment of the present invention.

  3B is a cross-sectional view taken along the line I-I 'of FIG. 3A. As shown, the nonvolatile memory structure includes a substrate 110, an active region 113, a device isolation region 115, a tunnel insulating film 131, a charge storage pattern 132, a blocking insulating film 134, a control gate 135, a protruding region 135p, and a mask. A pattern 138 is included. The control gate 135 includes an upper control gate 136 and a lower control gate 137.

  3C is a cross-sectional view taken along plane A in FIG. 3A. FIG. 3C includes the charge storage pattern 132, the blocking insulating layer 134, and the control gate 135. Lc represents a coupling distance, and Ls represents a linear geometric distance. Lc is defined as the minimum distance of the electrical interference path between adjacent charge storage patterns.

  In order to reduce or minimize the capacitance that causes cell interference, the coupling distance Lc between the charge storage patterns 132 is greater than the linear geometric distance Ls between the charge storage patterns 132. That is, the relational expression Lc> Ls is established.

  The relation is satisfied as shown in FIG. 3C. As shown in the drawing, in the embodiment of the present invention, the upper control gate 136 has a lower surface higher than the upper surface of the charge storage pattern 132. As shown in the drawing, the lower control gate 137 is located under the upper control gate 136 in the embodiment of the present invention. As shown in the drawings, in the embodiment of the present invention, the side wall of the lower control gate 137 has an inclined surface protruding outward. In an embodiment of the present invention, the outwardly projecting gradient surface is in a curved shape, a straight line shape, or a stepped shape.

  In an embodiment of the present invention, the doping concentration of the charge storage pattern 132 is higher than the doping concentration of the control gate 135.

  In embodiments of the present invention, the sidewalls of the lower control gate 137 and the sidewalls of the charge storage pattern 132 have different slopes. In an embodiment of the present invention, the slope of the side wall of the charge storage pattern 132 is more vertical than the side wall of the lower control gate 137.

  In the embodiment of the present invention, the control gate 135 includes a protrusion 135p for preventing the edges of adjacent charge storage patterns 132 from facing each other. In the embodiment of the present invention, the protrusion 135p is in the form of a spacer.

  In the embodiments of the present invention, the width of the charge storage pattern 132 is smaller than the width of the control gate 135. In another embodiment of the present invention, the charge storage pattern 132 is recessed.

  4A to 4H are views for explaining a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. A mask pattern 112 is formed on the semiconductor substrate 110 as illustrated in FIG. 4A. A pad oxide film 111 is formed between the mask pattern 112 and the substrate 110. In an embodiment of the present invention, the substrate 110 is a bulk silicon substrate, a silicon-on-insulator substrate, or a stacked substrate, and the mask pattern 112 is a silicon nitride SiN, silicon oxynitride SiON, or other suitable substrate. Made of material.

  As shown in FIG. 4B, the substrate 110 is etched to form a trench 114 or the like. The trench 114 defines an active region 113.

As shown in FIG. 4C, the trench 114 is filled with an insulating material to form an isolation region 115 of the device. In an embodiment of the present invention, the insulating material is, for example, high density plasma oxide, plasma enhanced oxide PEOX, or silicon oxide SiO ₂ . In some embodiments of the present invention, the insulating material is a thermal oxide, silicon nitride, or other suitable material. As shown in FIG. 4A, the mask pattern 112 and the device isolation region 115 are planarized by, for example, chemical mechanical polishing (CMP).

  As shown in FIG. 4D, the mask pattern 112 and the pad oxide film 111 are removed to expose the active region 113. In the embodiment of the present invention, the mask pattern 112 and the pad oxide film 111 are removed by an etching process. The etching process is a dry etching process or a wet etching process. As shown in FIG. 4D, the remaining pad oxide film 111 serves as a tunnel insulating film 121, and the remaining mask pattern 112 serves as an electron storage pattern 122. In the embodiment of the present invention, the charge storage pattern 122 is a dot film, a charge trap film, or a floating gate film. In the embodiment of the present invention, the dot film is made of silicon nitride containing conductive dots, for example, polysilicon. In an embodiment of the present invention, the charge trapping film is made of silicon nitride. In the embodiment of the present invention, the conductive film is a floating gate, and the conductive film is made of polysilicon.

  Referring to FIG. 4E, a blocking insulating layer 124 is formed on the semiconductor substrate 110 including the charge storage pattern 122. A control gate film 125 is formed on the blocking insulating film 124.

  In the embodiment of the present invention, the blocking insulating film 124 is made of silicon oxide, silicon nitride, hafnium aluminate such as HfAlO or HfAlON, and hafnium silicate such as HfSiO or HfSiON. In the embodiment of the present invention, the control gate film 125 is made of polysilicon mixed with polysilicon or metal silicide.

  As shown in FIG. 4F, a mask pattern 138 is formed on the control gate layer 125. The control gate layer 125 is etched using the mask pattern 138 as a mask to form an upper control gate 136.

  The control gate layer 125 can be etched by various methods. For example, an upper part and a part of the outside of the control gate layer 125 are removed by oxide etching to form the upper control gate 136. The blocking insulating layer 124 and the charge storage pattern 122 are removed by oxide etching. A part of the lower portion and the inner portion of the control gate layer 125 is removed by polymer etching to form the lower control gate 137.

  If the control gate film 125 is polysilicon, the control gate film 125 is etched using the conventional polysilicon etching method until the blocking insulating film 124 is exposed.

  An example of polymer etching is illustrated in FIG. 4G. A considerable amount of the etching polymer P is left on the control gate film 125 and etched. The etching polymer P is exposed from the sidewalls of the upper control gate 136 and the upper surface of the control gate film 125. The etching polymer P serves as a mask for forming a small curvature having a height of Δ. Etching is repeated N times until a desired shape, for example, the curved protrusion 135p of FIG. 3A is obtained.

  As shown in FIG. 4H, the control gate layer 125 is etched using the mask pattern 138 to form the lower control gate 137. If the control gate film 125 is polysilicon, the control gate film 125 can be etched with an etching gas containing carbon.

  As a result, the sidewall of the lower control gate 137 has a sloped surface projecting outward, and the slope of the sidewall of the charge storage pattern 132 is perpendicular to the sloped surface of the sidewall of the lower control gate 137. The control gate 135 includes a protrusion 135p.

  In the embodiment of the present invention, the cell interference can be reduced by forming the coupling distance Lc between the charge storage patterns 132 to be larger than the linear geometric distance Ls between the charge storage patterns 132. .

  In the embodiment of the present invention, the cell interference can be reduced by forming the control gate 135 so as to protrude from the charge storage pattern 132 as shown in FIG. 3A. In the embodiment of the present invention, the cell interference can be reduced by forming the charge storage pattern 132 so as to be recessed as compared with the control gate 135 as shown in FIG. 3A.

  In an embodiment of the present invention, the control gate 135 protrudes compared to the charge storage pattern 132, and the charge storage pattern 132 is recessed compared to the control gate 135.

  As shown in FIG. 5A, in the embodiment of the present invention, the control gate 135 protrudes compared to the mask pattern 138. As illustrated in FIG. 5B, in the embodiment of the present invention, the charge storage pattern 132 is recessed compared to the mask pattern 138.

  In some embodiments of the present invention, some of the side walls of the control gate have a sloped surface projecting outward. In some embodiments of the present invention, some sidewalls of the control gate and some sidewalls of the charge storage pattern have different slopes. In some embodiments of the present invention, the side wall slope of the charge storage pattern is perpendicular to the side wall slope of the control gate. By preventing the adjacent charge storage pattern boundaries from facing each other as described above, parasitic capacitance can be reduced. There are many other configurations that can accomplish this goal. For example, some of the sidewalls of the control gate have a sloped surface that projects outwardly larger than the sidewalls of the charge storage pattern. Some sidewalls of the charge storage pattern have sloped surfaces that enter the inside smaller than the sidewalls of the control gate. In the embodiment of the present invention, the portion of the inclined surface or the like that protrudes outside or enters the inside may have a curved shape, a linear shape, or a stepped shape.

  In the embodiments of the present invention, the plurality of charge storage patterns are dot films, charge trap films, or conductive films. The storage pattern arrangement can be applied to a floating gate and a charge trapping film. The floating gate is made of a conductive material such as polysilicon. The charge trapping film is made of a nonconductive material such as a nitride film. In addition, the nitride film is a part of a Sonos (SONOS) array or a Tanos (TANOS) array.

6 is a diagram illustrating operations of erasing and reading a program of a NAND device according to the related art. 6 is a diagram illustrating operations of erasing and reading a program of a NAND device according to the related art. 6 is a diagram illustrating operations of erasing and reading a program of a NAND device according to the related art. FIG. 2 is a wiring diagram and a plan view of a NAND flash memory cell according to the prior art. 1 is a cross-sectional view of a conventional NAND flash memory cell with respect to a bit line direction and a word line direction. FIG. 6 is a cross-sectional view of a NAND flash memory cell according to the prior art with respect to a word line direction. It is sectional drawing cut | disconnected by the A-A 'line | wire of FIG. 2c. 1 is a perspective view of a nonvolatile memory structure according to an embodiment of the present invention. It is sectional drawing cut | disconnected by the I-I 'line | wire of FIG. 3a. 3b is a cross-sectional view taken along plane A of FIG. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 3 is a diagram illustrating a method of manufacturing a nonvolatile memory structure according to an embodiment of the present invention. 5 is a diagram illustrating a control gate protruding from a mask pattern according to an exemplary embodiment of the present invention. 5 is a diagram illustrating a charge storage pattern that is recessed compared to a mask pattern according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 110 Semiconductor substrate 111 Pad oxide film 112 Mask pattern 113 Active region 114 Trench 115 Element isolation pattern 121 Gate insulating film 122 Preliminary charge storage pattern 124 Blocking insulating film 125 Control gate conductive film 131 Tunnel insulating film 132 Charge storage pattern 134 Blocking Insulation Pattern 135 Control Gate 135p Protrusion 136 Upper Control Gate 137 Lower Control Gate 138 Mask Pattern P Polymer

Claims (32)

  A plurality of charge storage patterns are included, and an electrical coupling distance Lc between adjacent charge storage patterns is larger than a linear geometric distance Ls between the adjacent charge storage patterns. Non-volatile memory structure. At least one of the plurality of charge storage patterns having a width of W _{1 in} a bit line direction and having a lower surface higher than an upper surface of the plurality of charge storage patterns; together with control gate including a plurality of lower control gate located at the bottom of the plurality of upper control gate, at least one has a width of W ₂ in the direction of the bit lines among the plurality of lower control gate, _2. The nonvolatile memory structure according to claim ₁ , wherein W2> W1. The plurality of charge storage patterns that occupy most of the width have a width of W ₁ in the direction of the bit line, and the plurality of lower control gates that occupy most of the width have a width of W ₂ in the direction of the bit line. The nonvolatile memory structure according to claim ₂ , wherein W ₂ > W ₁ .   The nonvolatile memory structure of claim 2, wherein at least one sidewall of the plurality of lower control gates has a sloped surface protruding outward.   The non-volatile memory structure according to claim 4, wherein the outwardly projecting gradient surface has a curved line, a straight line, or a step.   3. The nonvolatile memory according to claim 2, wherein at least one sidewall of the plurality of lower control gates and at least one sidewall of the plurality of charge storage patterns have different slope surfaces. Construction.   3. The nonvolatile memory structure of claim 2, wherein at least one sidewall of the plurality of charge storage patterns is further vertical than at least one sidewall of the plurality of lower control gates. .   Among the plurality of lower control gates, at least one side wall protrudes in the plurality of charge storage patterns as compared to at least one side wall, and the protruding portion is in the plurality of charge storage patterns. 3. The nonvolatile memory structure according to claim 2, wherein at least one side wall is prevented from facing a side wall of an adjacent charge storage pattern.   9. The non-volatile memory according to claim 8, wherein at least one of the sidewalls of the plurality of lower control gates protrudes compared to a mask pattern used to form the plurality of upper control gates. Construction.   The non-volatile memory structure of claim 8, wherein the protruding portion is in the form of a spacer.   At least one sidewall of the plurality of charge storage patterns is recessed relative to at least one sidewall of the plurality of lower control gates, and the recessed portion is at least one of the plurality of charge storage patterns. 3. The non-volatile memory structure according to claim 2, wherein the non-volatile memory structure is prevented from facing the side wall of the charge storage pattern adjacent to the two side walls.   The nonvolatile memory structure of claim 11, wherein at least one of the sidewalls of the plurality of lower control gates is recessed compared to a mask pattern used to form the plurality of upper control gates. .   A substrate including an active region under the plurality of charge storage patterns and a device isolation region under and between the plurality of charge storage patterns; a tunnel insulating layer on the active region; and the plurality of charge storage patterns The nonvolatile memory structure of claim 1, further comprising a blocking insulating film on the isolation region of the device.   The nonvolatile memory structure of claim 1, further comprising a mask film on the plurality of upper control gates.   14. The nonvolatile memory structure according to claim 13, wherein the substrate is a bulk silicon substrate, a silicon-on-insulator substrate, or a stacked substrate.   The blocking insulating film is any one of silicon oxide, silicon nitride, hafnium aluminate, HfAlO, HfAlON, hafnium silicate, HfSiO, and HfSiON. Non-volatile memory structure.   The nonvolatile memory structure according to claim 1, wherein the plurality of charge storage patterns are a dot film, a charge trap film, or a conductive film.   3. The nonvolatile memory structure according to claim 2, wherein the control gate is made of polysilicon or polysilicon and metal silicide.   The nonvolatile memory structure of claim 2, wherein the doping concentration of the plurality of charge storage patterns is greater than the doping concentration of the control gate.   A plurality of charge storage patterns are formed, and an electrical coupling distance Lc between the plurality of charge storage patterns is greater than a linear geometric distance Ls between the plurality of charge storage patterns. A method for forming a non-volatile memory structure. At least one has a width of W ₁ in the direction of the bit lines, a plurality of upper control gate and said with a high bottom surface than the top surface of said plurality of charge storage pattern among the plurality of electronic storage pattern a control gate comprising a plurality of lower control gate located under the plurality of upper control gate is formed, together with at least one among the plurality of lower control gate has a width of W ₂ in the direction of the bit lines, method of forming a non-volatile memory structure according to claim 20, characterized in that a W _2> W _1.   Forming the control gate includes forming a blocking insulating film on the plurality of charge storage patterns, forming a control gate film on the blocking insulating film, and on the control gate film. 23. The method of claim 21, further comprising: forming a mask pattern on the substrate, and etching the control gate film using the mask pattern to form the plurality of upper control gates and the plurality of lower control gates. Method for forming a non-volatile memory structure.   Forming the plurality of charge storage patterns includes forming a pad oxide film on the substrate, forming a mask pattern on the pad oxide film, and forming a trench defining an active region. Etching the substrate, filling the trenches to form isolation regions, etc., removing the mask pattern and the pad oxide film to expose the active regions, etc. 22. The method of forming a nonvolatile memory structure according to claim 21, wherein a tunneling insulating film is formed on the active region, and the plurality of charge storage patterns are formed on the tunneling insulating film.   Etching the control gate film includes etching the control gate film until the blocking insulating film is exposed, and exposing a sidewall of the plurality of upper control gates and an upper part of the control gate film. 23. The method of forming a nonvolatile memory structure according to claim 22, wherein the control gate film is etched with an etching gas.   The method of forming a nonvolatile memory structure according to claim 24, wherein the control gate film is polymer-etched with the etching gas and the etching is repeated.   26. The method of forming a nonvolatile memory structure according to claim 25, wherein the etching gas contains carbon.   The plurality of charge storage patterns are a plurality of floating gates, and forming the plurality of floating gates includes forming a gate oxide film, a polysilicon film and a nitride film on a substrate, a nitride film pattern, Patterning the gate oxide film, the polysilicon film and the nitride film to form a floating gate pattern and a gate oxide film pattern including a plurality of floating gates; and forming a trench defining an active region The trench is filled with a field oxide film for etching an exposed portion of a substrate, forming a trench oxide film inside the trench, etc., and forming an isolation region of an element. A method for forming a non-volatile memory structure according to claim 21.   Forming the control gate includes forming an interlayer dielectric film on the plurality of floating gates, forming a control gate film on the interlayer dielectric film, and forming a mask pattern on the control gate film. 28. The nonvolatile memory structure of claim 27, wherein the control gate film is etched using the mask pattern to form the plurality of upper control gates and the plurality of lower control gates. Forming method.   Patterning the polysilicon film to form the floating gate pattern includes doping the polysilicon film with an impurity at a first concentration level, and doping the control gate film with an impurity at a second concentration level. 29. The method of claim 28, further comprising doping, wherein the second concentration level is higher than the first concentration level.   Etching the control gate film using the mask pattern to form the plurality of upper control gates and the plurality of lower control gates etches the control gate films at a plurality of different etching rates. The method of forming a non-volatile memory structure according to claim 28.   The plurality of charge storage patterns are charge trapping films, and the formation of the charge trapping film includes forming a tunneling film, a memory storage film and a blocking film on the substrate, a tunneling film pattern, Patterning the tunneling film, the memory storage film and the blocking film to form a memory storage pattern including a trap film and a blocking film pattern; and exposing the substrate to form a source region and a drain region. 22. The method of forming a nonvolatile memory structure according to claim 21, wherein ions are implanted into the portion. Forming a pad oxide film on the substrate; forming a mask pattern on the pad oxide film; etching the substrate to form a trench or the like defining an active region; Filling the trench or the like to form the mask, removing the mask pattern and the pad oxide film to expose the active region, forming a tunneling insulating film on the exposed active region, Forming a plurality of charge storage patterns on the tunneling insulating film; forming a blocking insulating film on the plurality of charge storage patterns; forming a control gate film on the blocking insulating film; Forming a mask pattern on the control gate film, the plurality of upper control gates and the plurality of lower control gates. Etching the control gate layer using the mask pattern to form the plurality of upper control gates having a lower surface higher than an upper surface of the plurality of charge storage patterns; A lower control gate is positioned below the plurality of upper control gates, and at least one of the plurality of lower control gates has a width of W ₂ in the direction of the bit line, and W ₂ > W _1. A method for forming a non-volatile memory structure.