JP2008042154A - パッケージ基板 - Google Patents
パッケージ基板 Download PDFInfo
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- JP2008042154A JP2008042154A JP2006264172A JP2006264172A JP2008042154A JP 2008042154 A JP2008042154 A JP 2008042154A JP 2006264172 A JP2006264172 A JP 2006264172A JP 2006264172 A JP2006264172 A JP 2006264172A JP 2008042154 A JP2008042154 A JP 2008042154A
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- circuit
- insulating layer
- circuit board
- package substrate
- reinforcing plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/0949—Pad close to a hole, not surrounding the hole
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
強化版を組み合わせることで薄型基板の強度を高めて、製造工程の要件を満たすパッケージ基盤を提供する。
【解決手段】
回路基板210と、強化板240と、少なくとも一つの導電溝250が配設されたパッケージ基板200を提供する。前記強化板は、第一の表面240aが前記回路基板に接する形で配置されて前記回路基板の反りを阻止する。前記強化板は、開口内で露出しており前記回路基板の第一接触に対応する開口を有す。さらに、前記導電溝の一端は前記開口内に位置して前記第一接触に電気接続されており、前記導電溝の他端は前記強化板の第二の表面240bに位置してボンディングパッドを形成している。
【選択図】図2
Description
Claims (11)
- パッケージ基板であって、
回路基板と、
強化板であって、第一の表面が前記回路基板に接する形で配置されて前記回路基板の反りを阻止し、開口を有し、該開口は、そこに露出する前記回路板の第一接触に対応する、強化板と、
前記開口内に位置して前記第一接触に電気接続される一端と、前記強化板の第二の表面に位置してボンディングパッドを形成する他端を有す、少なくとも一つの導電溝とを含む、パッケージ基板。 - 前記回路基板は厚みが60μm未満である絶縁層を有す、請求項1に記載されたパッケージ基板。
- 前記回路基板はさらに上部回路と、下部回路と、メッキ加工された貫通孔を含み、前記上部回路と前記下部回路は前記絶縁層の2つの反対面上に配置され、前記メッキ加工された貫通孔は前記絶縁層の前記二つの反対面を貫通して前記上部回路と前記下部回路とに電気接続されている、請求項2に記載されたパッケージ基板。
- 前記回路基板はさらに、上部絶縁層と、下部絶縁層と、複数の導電ビアとを含み、前記上部絶縁層は前記上部回路を被覆し、前記下部絶縁層は前記下部回路を被覆し、前記複数の導電ビアは前記上部絶縁層内と前記下部絶縁層内にそれぞれ形成されて前記上部回路と前記下部回路とを電気接続する、請求項3に記載されたパッケージ基板。
- 前記第一接触は前記下部絶縁層と前記強化板との間に配置されており、前記複数の導電ビアは複数の前記第一接触をそれぞれ介して前記導電溝と電気接続されている、請求項4に記載されたパッケージ基板。
- 前記回路基板はさらに、前記上部絶縁層の表面に配置され、前記複数の導電ビアを通じて前記上部回路に電気接続された複数の第二接触を含む、請求項4に記載されたパッケージ基板。
- 前記強化板は絶縁膜と金属板とを含み、前記金属板の全表面は前記絶縁膜で被覆されている、請求項1に記載されたパッケージ基板。
- 前記金属板は銅、アルミニウム、またはステンレス鋼からなる、請求項7に記載されたパッケージ基板。
- 前記絶縁膜はエポキシ樹脂あるいはポリイミドからなる、請求項7に記載されたパッケージ基板。
- さらに、前記強化板の前記第二の表面に位置する前記導電溝を被覆し、前記ボンディングパッドを露出するソルダーレジストを含む、請求項1に記載されたパッケージ基板。
- さらに前記ボンディングパッド上に配設された少なくとも一つのはんだ玉、あるいはピンを含む、請求項1に記載されたパッケージ基板。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095129187A TWI308385B (en) | 2006-08-09 | 2006-08-09 | Package substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008042154A true JP2008042154A (ja) | 2008-02-21 |
Family
ID=39049897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006264172A Pending JP2008042154A (ja) | 2006-08-09 | 2006-09-28 | パッケージ基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7772703B2 (ja) |
JP (1) | JP2008042154A (ja) |
TW (1) | TWI308385B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019197876A (ja) * | 2018-05-07 | 2019-11-14 | 恆勁科技股分有限公司Phoenix Pioneer Technology Co.,Ltd. | フリップチップパッケージ基板 |
WO2023148840A1 (ja) * | 2022-02-02 | 2023-08-10 | キオクシア株式会社 | 半導体装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8653662B2 (en) * | 2012-05-02 | 2014-02-18 | International Business Machines Corporation | Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits |
KR101538573B1 (ko) * | 2014-02-05 | 2015-07-21 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 |
CN109564913B (zh) * | 2016-08-08 | 2023-06-06 | 伊文萨思公司 | 薄封装中的翘曲平衡 |
TWI739027B (zh) * | 2018-08-30 | 2021-09-11 | 恆勁科技股份有限公司 | 覆晶封裝基板之核心結構及其製法 |
TWI738069B (zh) * | 2019-09-27 | 2021-09-01 | 恆勁科技股份有限公司 | 覆晶封裝基板及其製法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004031738A (ja) * | 2002-06-27 | 2004-01-29 | Ngk Spark Plug Co Ltd | 配線基板およびその製造方法 |
JP2006073777A (ja) * | 2004-09-02 | 2006-03-16 | Nec Toppan Circuit Solutions Inc | 印刷配線板、その製造方法及び半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61188997A (ja) * | 1985-02-18 | 1986-08-22 | オ−ケ−プリント配線株式会社 | プリント配線基板およびその製造方法 |
JP2000003980A (ja) | 1998-04-17 | 2000-01-07 | Sumitomo Metal Electronics Devices Inc | 半導体搭載用回路基板及びその製造方法 |
US6960824B1 (en) * | 2000-11-15 | 2005-11-01 | Skyworks Solutions, Inc. | Structure and method for fabrication of a leadless chip carrier |
US6744135B2 (en) * | 2001-05-22 | 2004-06-01 | Hitachi, Ltd. | Electronic apparatus |
CN1224305C (zh) * | 2001-10-31 | 2005-10-19 | 新光电气工业株式会社 | 半导体器件用多层电路基板的制造方法 |
TWI227102B (en) * | 2002-03-15 | 2005-01-21 | United Test Ct Inc | Fabrication method for circuit carrier |
TWI229574B (en) * | 2002-11-05 | 2005-03-11 | Siliconware Precision Industries Co Ltd | Warpage-preventing circuit board and method for fabricating the same |
-
2006
- 2006-08-09 TW TW095129187A patent/TWI308385B/zh active
- 2006-09-20 US US11/533,765 patent/US7772703B2/en active Active
- 2006-09-28 JP JP2006264172A patent/JP2008042154A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004031738A (ja) * | 2002-06-27 | 2004-01-29 | Ngk Spark Plug Co Ltd | 配線基板およびその製造方法 |
JP2006073777A (ja) * | 2004-09-02 | 2006-03-16 | Nec Toppan Circuit Solutions Inc | 印刷配線板、その製造方法及び半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019197876A (ja) * | 2018-05-07 | 2019-11-14 | 恆勁科技股分有限公司Phoenix Pioneer Technology Co.,Ltd. | フリップチップパッケージ基板 |
WO2023148840A1 (ja) * | 2022-02-02 | 2023-08-10 | キオクシア株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
TW200810058A (en) | 2008-02-16 |
US20080036058A1 (en) | 2008-02-14 |
US7772703B2 (en) | 2010-08-10 |
TWI308385B (en) | 2009-04-01 |
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