JP2008021916A - Electronic component device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component device and its manufacturing method which can prevent land exfoliation of the conductor land generated at the time of reflow by the side of the printed wiring board, while securing connection with the printed wiring board, even if electronic components has a high-density electrode. <P>SOLUTION: The electronic component device comprises: an insulating substrate; a conductive land formed on this insulating substrate; an electronic components arranged on this conductive land; a non-conductive sheet fixed to the insulating substrate other than the conductive land for covering at least one portion of the periphery of the conductive land, and also for opening other portions of the conductive land; and a connection means for connecting the conductive land and the electronic components electrically, in the portion for opening the conductive land of this non-conductive sheet. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic component device for mounting an electronic component including a component having a high-density electrode such as an area array, and a manufacturing method thereof.

  In recent years, BGA (BALL / GRID / ARRAY) and CSP (CHIP / SCALE / PACKAGE) parts, which are area arrays, have a high pin count and narrow pitch to ensure the reliability of connection between BGA / CSP and printed wiring board. Therefore, a method of filling an underfill (filler) around a solder ball as a connecting portion is taken. When filling the underfill, the surface layer on the printed wiring board side is preferably smooth.

Also, there are many cases where conductor patterns (drawing patterns) and through / non-through vias are installed around the conductor lands (pads) in the area where the BGA that fills the underfill is mounted. Flow is hindered. In addition, the surface layer of the printed wiring board forms an insulating layer with a solder resist material for pad peeling and pattern protection at the time of high temperature reflow using lead-free solder material, and covers the periphery of the conductor land to prevent peeling of the conductor land.

  For example, in order to reduce the land peeling of a circuit board using a lead-free solder material having a relatively high melting point, a through hole in which a lead 3 of an electronic component is inserted in FIG. In the land 2 having the hole 4, the lead 3 and the land 2 are electrically connected using the lead-free solder 6 and the solder resist 5 for protecting the circuit board 1 is formed so as to cover at least a part of the land outer peripheral end 2a. Are disclosed.

  Further, as a means for smoothing the surface of a laminated plate in which a plurality of laminated plates are stacked, a prepreg advanced to the B stage is prepared in FIG. 1 of Japanese Patent Application Laid-Open No. 11-320593 (refer to Patent Document 2). Is sandwiched between molding plates and heated and pressed between hot plates.

Japanese Patent Laid-Open No. 2002-237664 (FIG. 1)

Japanese Patent Laid-Open No. 11-320593 (FIG. 1, paragraph 0002)

  However, in the thing of patent document 1, since a solder resist is used for an insulating layer, in order to respond | correspond to narrow pitches, such as BGA, in order to form the hollow pattern of an insulating layer by printing, the wettability of a solder resist or It is difficult to apply from the viewpoint of printing accuracy, and even if the solder resist is laminated and etched by photoengraving, the film thickness of the solder resist is relatively thick, so there is a problem that a long etching time is required. there were. Also, since the solder resist is a resin, the solid state has a rough surface roughness, so a step due to the pattern thickness such as the conductor land is added, and the surface layer as a printed wiring board is uneven, and filling such as underfill is not possible. There is also a problem that it is difficult.

  In the thing of patent document 2, although it is suitable in order to improve the smoothness of the surface layer of a laminated board, the relationship with the electronic component etc. which are comprised on the upper part is not mentioned.

The present invention has been made in order to solve the above-described problems. Even in an electronic component having a high-density electrode, the connection with the printed wiring board is ensured and the printed wiring board side generated at the time of soldering is secured. An object of the present invention is to provide an electronic component device capable of preventing the land of a conductor land from being separated.

  An electronic component device according to a first aspect of the present invention includes an insulating substrate, a conductive land provided on the insulating substrate, an electronic component provided on the conductive land, and a peripheral edge of the conductive land. A non-conductive sheet that covers at least a part of the portion and opens the other part of the conductive land and is fixed to the insulating substrate other than the conductive land, and the conductive land of the non-conductive sheet And a connection means for electrically connecting the conductive land and the electronic component at a portion where the opening is opened.

  According to a second aspect of the present invention, there is provided an electronic component device comprising: an insulating substrate; first and second conductive lands provided on the insulating substrate; and one and other electrons provided on the insulating substrate. Covering the component and at least a part of the peripheral edge of each of the first and second conductive lands, and opening the other parts of the first and second conductive lands, respectively. A non-conductive sheet fixed to the insulating substrate other than the conductive land, and a portion of the non-conductive sheet that opens the first and second conductive lands, the first conductive land and the one electronic component; And a connecting means for electrically connecting the second conductive land and the lead wire connected to the other electronic component.

  An electronic component device according to a third aspect of the present invention is provided on an insulating substrate, one and other conductive lands provided on one and the other main surface sides of the insulating substrate, and the insulating substrate. A first connecting means for electrically connecting the one and the other conductor lands through a through hole; an electronic component provided on the one conductive land; and a peripheral portion of the one and the other conductive lands A non-conductive sheet that covers at least a portion of the conductive land and opens the other portion of the one conductive land and is fixed to the insulating substrate other than the one and other conductive lands, and the non-conductive sheet And a connecting means for electrically connecting the one conductive land and the electronic component at a portion where the one conductive land is opened.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing an electronic component device comprising: a conductive land forming step of forming a conductive land on a main surface of an insulating substrate; and at least a peripheral edge portion of the conductive land. A non-conductive sheet forming step for forming a non-conductive sheet thereon, a connection member forming step for forming a conductive connection member on the conductive land, and an electronic component arrangement for arranging an electronic component on the connection member And a heat treatment step for connecting the electronic component to the conductive land by the connecting means by heat treatment and fixing the non-conductive sheet to the insulating substrate at the same time after the steps. is there.

According to the electronic component device of the present invention, the non-conductive sheet is mounted between the area array component and the substrate, so that the non-conductive sheet can be formed on the outer peripheral edge of the conductor land without laminating an insulating layer such as solder resist material Therefore, even if a high-melting-point solder material is used as an electrical connection means, there is an effect that it is possible to prevent land peeling that occurs when soldering electronic components.

  In addition, since the non-conductive sheet is fused to the surface layer of the base material, the through-through hole portion (signal line land portion) provided in addition to the component mounting land is sealed with this sheet, and is generated from the through-hole portion. It is possible to contain copper and electrolytic plating material residues, and the quality of the optical component mounting substrate can be improved.

  In addition, since there is no air leakage from the through-hole portion in the board transfer process during automatic component mounting, it is possible to prevent a vacuum chuck failure (substrate transfer failure).

Example 1.
Embodiment 1 of the present invention will be described below with reference to FIG. FIG. 1 is a partial cross-sectional view of an electronic component device mounted with a BGA. In FIG. 1, 1 is an insulating substrate (insulating substrate), 1a is a surface layer substrate, and 1b is an inner layer substrate. 2 is a conductor land (also referred to as a conductive land conductor land pattern) or mounting pad (pad) patterned on the insulating substrate 1, and 3 is a signal line (drawing pattern) for transmitting a signal from the conductor land 2 or the like, 3a is a surface layer pattern, and 3b is an inner layer pattern. Reference numeral 4 denotes a via for connecting the signal lines 3 to each other, 4a is a through via, and 4b is a non-through via. 5 is an insulating layer made of a solder resist material for protecting the signal wire 3 on the surface layer, and 6 is a lead-free (eutectic) or eutectic cream solder material, which is an insulating substrate corresponding to the electrode of the electronic component to be mounted 1 is an electrical connection means (connection means) printed and formed on one conductor land 2.

  Reference numeral 7 denotes a non-conductive prepreg sheet (also referred to as a non-conductive sheet non-conductive sheet) installed on the insulating substrate 1, and 7 a denotes a bent portion of the prepreg sheet 7 with its peripheral edge bent. 8 is a bump (bump electrode) made of a conductor such as a solder material, and 9 is a BGA as an area array, which is usually integrated with the bump electrode 8. Reference numeral 10 denotes an underfill (filler) that is injected into a gap between the prepreg sheet 7 and the BGA 9 on the insulating substrate 1 and is filled in the bump electrode (solder bump) 8 region of the BGA 9.

  The prepreg sheet 7 is obtained by impregnating a plain woven glass cloth with an epoxy resin to be in a semi-cured state (B stage). As will be described later, this prepreg sheet 7 is processed to provide punch holes, cuts are made in the periphery of the sheet, and the cut part is heated to a temperature higher than the transition temperature (Tg) of the sheet and bent to form a bent part. In addition, the processed sheet is mounted between the BGA 9 and the insulating substrate 1, reflowed in a reflow furnace, and the sheet and the insulating substrate 1 are fused. is there. In terms of processing quality, (1) the pot life of the B stage prepreg sheet 7 is about 3 months under storage conditions of 20 ° C. and 50% RH. (2) A part of the resin of the sheet does not flow or adhere to the via 4 or the like on the insulating substrate 1 when fused. (3) The curing time (gel time) is shorter than the welding time of the conductor land 2 and the bump electrode 8 by the solder cream material during reflow. From the above conditions, suitable prepreg materials are, for example, prepreg R-1661 manufactured by Matsushita Electric Works, prepreg GEA-67N manufactured by Hitachi Chemical.

  Next, a processing method of the prepreg sheet 7 mounted in the gap between the insulating substrate 1 and the BGA 9 will be described with reference to FIG. FIG. 2A shows a partial plan view of the prepreg sheet 7. In FIG. 2 (a), 7b is a through hole (processed hole) provided in the prepreg sheet 7, and the hole on the prepreg sheet 7 side with respect to the pad diameter of the conductor land 2 of the insulating substrate 1 shown as reference is φ0.6 mm. The diameter is 0.8 mm. FIG. 2B is a perspective view for explaining the processing order of the prepreg sheet 7 shown in FIG. 2A, and the prepreg sheet 7 is bent to form a bent portion 7a after drilling.

  The prepreg sheet 7 is mounted around the conductor land 2 corresponding to each of the bump electrodes 8 of the BGA 9, but the prepreg sheet 7 is not covered with the prepreg sheet 7 so that the bump electrode 8 of the BGA 9 and the conductor land 2 of the insulating substrate 1 are not hidden. A punch hole (processed hole) 7b is formed in the sheet 7 in advance. The size of the punch hole 7b is about the diameter of the conductor land 2 plus about 0.2 mm. For example, as shown in FIG. 2, when the size of the conductor land 2 is 0.6 mm and the pitch of the bump electrodes 8 of the BGA 9 is 1.0 mm, the hole diameter is 0.8 mm.

  Regarding the thickness of the prepreg sheet 7, since it is mounted on the insulating substrate 1 side between the BGA 9 and the insulating substrate 1 and then filled with the underfill 10, if the thickness of the prepreg sheet 7 is too thick, the BGA 9 and the insulating substrate 1 And the underfill 10 is difficult to be filled. Further, the prepreg sheet 7 is fused (adhered) to the insulating substrate 1 by reflow. However, if the thickness of the prepreg sheet 7 exceeds 0.1 mm, the deflection of the glass cloth in the prepreg increases, so that the adhesion to the insulating substrate 1 is improved. become weak. Therefore, the thickness of the prepreg sheet 7 is 0.1 mm or less, preferably 0.06 mm or less.

  The size of the prepreg sheet 7 is set so that the height of the tray shape when folded is substantially the same as the height of the BGA 9 to be mounted. Therefore, the length of one side of the prepreg sheet 7 is set to a length having a margin of about 3 mm in the sum of the length of one side of the BGA 9 to be mounted and the height including the bump electrode 8 of the BGA 9.

  In folding, a kerf is formed along a fold line (folding position) in a desired peripheral area, an unnecessary area at an end where the fold line intersects is cut off, and then heated locally along the fold line of the prepreg sheet 7. Bend the periphery. The intersecting portions of the bent portions 7a orthogonal to each other are appropriately bonded with a thermosetting resin to form a frame. In this local heating, a temperature of about 300 ° C. is radiated by an infrared heater having a spot diameter of about 100 μm. Alternatively, it may be bent while being heated manually using a simple hot plate (bar). Since the peripheral edge of the prepreg sheet 7 is intended to dam the underfill 10, it is preferable that the bent portion 7a of the prepreg sheet 7 is upright with respect to the plane of the prepreg sheet 7 when the underfill 10 has a low viscosity. This does not apply as long as it has thixotropic viscosity.

  Next, a method for forming a base material (also referred to as a substrate or a printed wiring board) on which BGA 9 is mounted will be described with reference to FIGS. As shown in FIG. 1, a copper foil previously formed on each of an outer layer (surface layer) substrate 1a and an inner layer substrate 1b using a glass cloth base epoxy resin is exposed, developed and etched by photolithography using a desired mask pattern. To do. That is, as shown in FIG. 3, the conductor land 2 corresponding to the position of the bump electrode 8 of the BGA 9 and the signal line (drawer pattern) 3 electrically connected to the conductor land 2 and the lead pattern of the through via 4a and the non-through via 4b. 3a and 3b are formed. Thereafter, the outer layer substrate 1a and the inner layer substrate 1b are laminated, a hole is drilled at a predetermined position, and electroless plating or electrolytic plating is performed using a nickel (Ni) or gold (Au) material. In addition, you may implement a hole process in the pre-processing stage before lamination | stacking.

  Next, the assembly (manufacturing order) of the electronic component device using the printed wiring board will be described with reference to FIGS. As shown in FIG. 4, the pattern of a desired insulating layer 5 is formed by screen printing using a solder resist material so as to surround the conductor land 2 around the conductor land 2 corresponding to the bump electrode 8 of the BGA 9 on the printed wiring board. Form. Alternatively, the insulating layer 5 may be formed by photolithography after full surface printing.

  Next, the cream solder 6 is screen-printed on the conductor land 2. Next, as shown in FIGS. 5 and 6, the prepreg sheet 7 is installed on the conductor land 2 side of the BGA 9 mounting region of the insulating substrate 1. At that time, each conductor land 2 is aligned so as to be completely exposed from the processed hole 7 b of the prepreg sheet 7. Positioning may be performed by human positioning, but a reference hole having the same diameter is provided in advance at the end of the insulating substrate 1 or the prepreg sheet 7 and the positioning is performed using positioning pins. For fixing the insulating substrate 1 and the prepreg sheet 7, an adhesive or the like is applied and temporarily fixed using four corners of the prepreg sheet 7 excluding the peripheral edge.

  Thereafter, the insulating substrate 1 on which the prepreg sheet 7 is temporarily fixed is set in a component mounting apparatus (self-mounting machine) such as a chip mounter, and the BGA 9 is mounted on the surface of the insulating substrate 1 as shown in FIG.

  Next, after self-mounting the surface mount component including the BGA 9, reflow soldering is performed under a normal reflow temperature condition of the surface mount component in a reflow furnace whose set temperature is around 240 ° C., and the electronic component and the conductor land 2 of the insulating substrate 1 Are connected via cream solder 6. At the same time, since the prepreg sheet 7 is also heated at a temperature higher than the transition temperature of the base material, the adhesion between the insulating substrate 1 and the prepreg sheet 7 becomes strong, becomes a completely bonded state, and the prepreg sheet 7 is cured, and is in an A stage (cured) state. It becomes.

  Next, a method for applying the underfill 6 will be described. FIG. 8 is a partial cross-sectional view of the electronic component device on which the BGA 9 is mounted, and is the same as FIG. The underfill 10 is injected into the gap between the prepreg sheet 7 and the BGA 9 from one end of the unbent peripheral edge of the tray-like bent portion 7 a provided outside the BGA 9 mounting region, and also into the through hole 7 b of the prepreg sheet 7. The prepreg sheet 7 is filled and dammed by the bent portion 7a.

  FIG. 9 is a diagram for explaining a method of injecting the underfill 10. In FIG. 9, when filling the underfill 10 into the area of the bump electrode 8 of the BGA 9 from the dispenser 100 in which the underfill 10 is stored in advance, the substrate (printed wiring board) is inclined as shown in FIG. inject. This angle (θ) is preferably 15 to 75 degrees with respect to the horizontal plane. Further, it is preferable to fill the substrate while heating according to the characteristics of the underfill 10. If underheating is insufficient, the fluidity of the underfill 10 is poor. If it is heated too much, the reaction of the underfill 10 proceeds and the curing time is accelerated, and the fillable area is narrowed for large BGA parts, so the ambient temperature is 45 to 55 ° C. It is desirable to manage with the substrate temperature. 1 to 9, the same reference numerals denote the same or corresponding parts.

As the filling of the underfill 10 proceeds, the underfill 10 flows out from the periphery of the BGA 9, but the underfill 10 is blocked by the peripheral edge portion of the prepreg sheet 7 bent in a tray shape provided around the BGA 9. .

As described above, the via 4 and the lead pattern 3 around the conductor land 2 of the BGA 9 are exposed to the plane of the application region of the underfill 10 when the prepreg sheet 7 is not attached, and thus the flow of the underfill 10 is obstructed. However, by mounting the prepreg sheet 7, smoothness over the entire mounting area of the BGA 9 can be obtained, and the underfill 10 can be injected over a wide range.

Further, since the via 4 is covered with the prepreg sheet 7, it is possible to prevent the underfill 10 from flowing out from the via 4 around the conductor land 2 to the back side of the substrate, and to perform masking for closing the via 4. There is also an advantage that is no longer necessary.

Example 2
In the first embodiment, the BGA 9 mounted on the insulating substrate 1 has been described. In the second embodiment, the case where the BGA 9 and electronic components other than the BGA 9 are simultaneously mounted will be described with reference to FIG. FIG. 10 is a mounting schematic diagram of an electronic component device in which the BGA 9 and other electronic components are mounted on the same substrate. In FIG. 10, 70 is a prepreg sheet fused on the base material in the BGA 9 mounting area, 71 is a prepreg sheet fused on the base material in the electronic component mounting area other than the BGA, and 72 is the back surface of the insulating substrate 1 (S Prepreg sheet to be fused on the surface) side substrate, 110 is an input / output connector for an electronic circuit, 120 is a discrete resistor mounted on the substrate, 120a is an electrode (lead electrode) of the resistor 120, 130 is a surface-mounted capacitor, and 130a is an electrode (chip electrode) of the capacitor 130. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

  11 is a partial cross-sectional view of the X-X ′ region of the base material on the BGA 9 mounting region side of the mounting schematic diagram shown in FIG. 10, and 70 b is a through hole (working hole) provided in the prepreg sheet 70. In the figure, the same reference numerals as those in FIGS. 1 and 10 denote the same or corresponding parts.

  FIG. 12 is a partial cross-sectional view of the electronic component device on the electronic component mounting side other than the BGA 9 in the mounting schematic diagram shown in FIG. 10, and the lead electrode 120 a of the resistor 120 penetrates the insulating substrate 1. Installed. The chip electrode 130 a of the capacitor 130 is surface-mounted on the surface layer of the insulating substrate 1. In the figure, the same reference numerals as those in FIGS. 1 and 10 denote the same or corresponding parts.

  The major difference from the first embodiment is that the insulating layer 5 is provided in FIG. 5 of the first embodiment, but the insulating layer 5 is not provided in the second embodiment. Further, unlike the first embodiment, the processing hole 70b is installed so as to cover the outer peripheral end portion of the conductor land 2 of the insulating substrate 1 so that the prepreg sheet 70 and a partial pattern of the conductor land 2 are fused. To do.

  That is, when the lead electrode of the electronic component is inserted through the front and back of the insulating substrate 1 as shown in FIG. 13A, if the lead electrode diameter is 0.5 mm, the hole diameter of the conductor land 2 is 0.7 mm. The outer shape of the conductor land 2 is larger than the hollow hole diameter of 0.85 mm provided in the prepreg sheet. Further, as shown in FIG. 13B, when mounting the chip electrode of the electronic component on the surface of the insulating substrate 1, the prepreg sheet is positioned so that at least a part of the outer peripheral end of the conductor land 2 is covered. Is positioned and placed. At the same time, the prepreg sheet is placed so that the hollow portion of the prepreg sheet is located in a region deviated from the electrical connection means region installed in the conductor land 2 pattern.

  Next, since the prepreg sheets 70, 71, 72 are placed and fused on both surfaces of the insulating substrate 1, a method for fixing the prepreg sheets 71, 72 will be described in detail.

  First, the prepreg sheets 71 and 72 that have been punched are overlaid as shown in the reference diagram of FIG. On the outside of the prepreg sheets 71 and 72, for example, a release film having a thickness of 50 to 75 μm is stacked (tetrafluoroethylene such as Aflex manufactured by Asahi Glass Co., Ltd.) and a thickness of 100 μm as a cushioning material on the upper part. Overlay about 3 sheets of heat-resistant paper.

The alignment between the conductive land 2 of the insulating substrate 1 and the prepreg sheets 71 and 72 is made in advance by providing holes of the same diameter in the layer constituent units of the insulating substrate 1 and the prepreg sheets 71 and 72, and using alignment pins. Alignment is performed in units of layer constitution between the insulating substrate 1 and the prepreg sheets 71 and 72. After alignment, the insulating substrate 1 and the release film on the periphery of the prepreg sheets 71 and 72 and the heat-resistant paper are fixed on both sides via the side surface of the base material using polyimide tape. Next, thermocompression bonding is performed at a temperature of 130 to 150 ° C. and a pressure of 10 kg / cm ² for about 30 minutes, and the insulating substrate 1 and the prepreg sheets 71 and 72 are attached. After pasting, remove the alignment pin and peel off the release film. Next, the cream solder 6 is printed, and the BGA 9 and the electronic components for surface mounting are mounted on the insulating substrate 1 by the self-mounting machine, and reflow similar to that of the first embodiment is performed. Thereafter, the lead electrode of the insertion type electronic component is inserted into the through hole, and flow soldering or manual soldering is performed.

  From the above, by replacing the insulating layer 5 described in the first embodiment with the prepreg sheets 71 and 72 on both surfaces of the insulating substrate 1, not only through the BGA 9 but also through vias 4a in the electronic component installation area other than the BGA 9 Since the through via 4 b is also covered with the prepreg sheets 71 and 72, there is an effect of preventing the underfill 10 from flowing out from the through via 4 a around the conductor land 2 to the S surface side of the insulating substrate 1.

  In the first embodiment, the prepreg sheet 7 provided in the BGA 9 mounting region has the bent portion 7a at the peripheral portion. However, the prepreg sheet 70 in the first embodiment is formed by using the bent portion 7a as a normal flat prepreg sheet. It becomes an alternative to the insulating layer 5 made of the solder resist material described. Further, since the surface of the prepreg sheet 70 has higher smoothness than the surface of the insulating layer 5 made of a solder resist material obtained by solidifying a resin, it can be easily injected even when the underfill 10 is applied to the BGA 9 mounting region.

  In other words, the same arrangement pattern as that of the insulating layer 5 shown in the first embodiment is configured by the prepreg sheet 70, and the holes of the through via 4a and the non-through via 4b that cannot be covered by the insulating layer 5 are used. By covering the (through-hole hole) with a prepreg sheet, the insulation layer 5 used for improving the dielectric strength including short-circuiting and preventing corrosion of signal lines (wiring patterns) or the like, by printing or photoengraving about 30-50 μm The thickness stacking process can be omitted, and in the suction process (vacuum chuck) when the electronic component device is transported by the self-mounting machine, the suction failure due to air leakage from the through via 4a can be improved, and the through via 4a or non-through The effect that the conductive residue generated in the electroless plating or electrolytic plating process in the via 4b is completely enclosed in the insulating substrate 1 and the short circuit failure due to the scattering of the conductive material can be prevented. A.

Example 3
In Example 2, the prepreg sheet 70 and the prepreg sheets 71 and 72 in the area where the BGA 9 and the electronic components other than the BGA 9 are mounted are separated. In Example 3, a prepreg sheet integrally formed over the entire area of the electronic component to be mounted will be described with reference to FIG. FIG. 15 is a plan view of the integrated prepreg sheet, 73 is an integrated prepreg sheet (non-conductive sheet), 73 a is a bent portion of the prepreg sheet 73, and 73 b is an insulating substrate 1 provided on the prepreg sheet 73. Machining hole corresponding to the conductor land 2, 73 c is a surface layer (surface) component soldering lead hole, 73 d is a surface mounting component mounting hole, 73 e is a back surface (S surface) component soldering lead hole, and 73 f is a back surface (S surface). The mounting component mounting hole 73g is a processing hole corresponding to the conductor land 2 for mounting the connector.

  Next, the structure of the processing holes 73b to 73g installed in the prepreg sheet 73 will be described. The processing hole 73 b is a hole corresponding to the bump electrode 8 of the BGA 9 shown in FIG. 1 and covers the outer peripheral end of the conductor land 2. The processing hole 73c covers an outer peripheral end portion of the conductor land 2 when the lead electrode 120a such as the resistor 120 is attached to the conductor land 2 on the surface layer of the insulating substrate 1 by electrical connection means. The processing hole 73d is a rectangular hole when chip components such as a resistor and a capacitor 130 are mounted on the surface layer, and the chip electrode 130a and the like are attached to the conductor land 2 on the surface layer of the insulating substrate 1 by electrical connection means. Covers the outer peripheral edge of the conductor land 2.

  The processing hole 73e covers the outer peripheral end portion of the conductor land 2 when the lead electrode 120a such as the resistor 120 is attached to the conductor land 2 by the electric connection means on the surface of the S surface of the insulating substrate 1. The processing hole 73f is a rectangular hole when chip components such as the resistor 120 and the capacitor 130 are mounted on the surface of the S surface, and the chip electrode 130a and the like are attached to the conductor land 2 on the S surface surface of the insulating substrate 1 by electrical connection means. The processed hole 73 f covers the outer peripheral end of the conductor land 2. The processing hole 73g penetrates a terminal (not shown) of the connector 110 and covers the outer peripheral end of the conductor land 2 that is electrically connected to the terminal of the connector 110. In addition, the processing hole 73h is a component lead insertion hole, and covers the outer peripheral end of the conductor land 2 when the conductor land 2 is provided at the insertion position. Note that all the through holes for connecting the inner layer circuit exposed on the surface layer of the insulating substrate 1 are covered with the prepreg sheet 73.

  In FIG. 15, the bent portion 73a of the prepreg sheet 73 is bent to prevent the underfill 10 from flowing. However, if the underfill 10 has thixotropy, the bent portion 73a may not be formed.

From the above, the prepreg sheet 73 is integrated and fused to the surface layer of the insulating substrate 1 so that it can be used as an alternative to the insulating layer 5 using a solder resist or the like. The number of parts can be reduced.
In Examples 1 to 3, a B-stage prepreg sheet was used as the non-conductive sheet. However, even if a solder resist film or a polyimide film is punched and thermocompression bonded to the insulating substrate 1, there is a corresponding effect.

It is a fragmentary sectional view of the electronic component apparatus which mounted BGA by Example 1 of this invention. It is a figure explaining the processing method of the prepreg sheet | seat of the electronic component apparatus by Example 1 of this invention, Fig.2 (a) is a top view of a prepreg sheet | seat, FIG.2 (b) shows a process order. FIG. 3 is a schematic pattern diagram of conductive lands and signal lines of the electronic component device according to Embodiment 1 of the present invention. It is a fragmentary sectional view explaining the assembly order of the electronic component apparatus by Example 1 of this invention. It is a fragmentary sectional view explaining the assembly order of the electronic component apparatus by Example 1 of this invention. It is a perspective view explaining the mounting method of the nonelectroconductive sheet of the electronic component apparatus by Example 1 of this invention. It is a perspective view explaining the mounting method of BGA of the electronic component apparatus by Example 1 of this invention. It is a fragmentary sectional view explaining the assembly order of the electronic component apparatus by Example 1 of this invention. It is a figure explaining the underfill injection | pouring method of the electronic component apparatus by Example 1 of this invention. It is the mounting schematic diagram of the electronic component apparatus by Example 2 of this invention. It is a fragmentary sectional view by the side of the BGA area | region of the electronic component apparatus by Example 2 of this invention. It is a fragmentary sectional view by the side of the electronic component except the BGA area | region of the electronic component apparatus by Example 2 of this invention. It is a figure explaining the positional relationship of the conductor land of the electronic component apparatus by Example 2 of this invention, and the hollow part of a prepreg sheet, Fig.13 (a) is a case of the mounting component which penetrates front and back, FIG.13 ( b) is a case of a surface mount component. It is a figure explaining the sticking method of the nonelectroconductive sheet by Example 2 of this invention. It is a top view of the non-electricity sheet | seat by Example 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate, 1a Surface layer substrate, 1b Inner layer substrate, 2 Conductor land (mounting pad), 3 Signal line (drawing pattern), 3a Surface layer pattern, 3b Inner layer pattern, 4 Via, 4a Through-via, 4b Non-through via, 5 Insulation Layer, 6 electrical connection means, 7 non-conductive sheet (prepreg sheet), 7a bent portion, 7b processed hole (through hole), 8 bump electrode, 9 BGA (area array), 10 underfill, 70 non-conductive sheet, 71 non-conductive Electrical sheet, 72 Non-conductive sheet, 73a Bending part, 73b-73h Processing hole (through hole), 100 dispenser, 110 connector, 120 resistor, 120a electrode, 130 capacitor, 130a electrode.

Claims (4)

An insulating substrate; a conductive land provided on the insulating substrate; an electronic component provided on the conductive land; and covering at least a part of a peripheral portion of the conductive land; The other part of the conductive land is opened, the non-conductive sheet fixed to the insulating substrate other than the conductive land, and the part of the non-conductive sheet that opens the conductive land and the conductive land and the electron An electronic component device comprising connection means for electrically connecting a component. Insulating substrate, first and second conductive lands provided on the insulating substrate, one and other electronic components provided on the insulating substrate, and the first and second conductive lands Each of the peripheral edges of the first and second conductive lands is covered, and the other portions of the first and second conductive lands are opened and fixed to the insulating substrate other than the first and second conductive lands. The first conductive land and the one electronic component are electrically connected to each other at the portion where the first and second conductive lands of the non-conductive sheet are opened, and the second conductive An electronic component device comprising a connecting means for electrically connecting a conductive land and a lead wire connected to the other electronic component. Insulating substrate, one and other conductive lands provided on one and other main surface sides of the insulating substrate, and the one and other conductor lands via a through hole provided in the insulating substrate A first connecting means for electrically connecting the electronic component, an electronic component provided on the one conductive land, and at least a part of the peripheral edge of the one and the other conductive land, and the one In the conductive land, the other part is opened, and the non-conductive sheet fixed to the insulating substrate other than the one and the other conductive lands, and the one conductive land of the non-conductive sheet are opened. An electronic component device comprising connection means for electrically connecting the one conductive land and the electronic component. A conductive land forming step for forming a conductive land on the main surface of the insulating substrate, and a nonconductive sheet forming step for covering at least a peripheral portion of the conductive land and forming a nonconductive sheet on the insulating substrate. A connecting member forming step of forming a conductive connecting member on the conductive land, an electronic component arranging step of arranging an electronic component on the connecting member, and after these steps, the electronic component is heated by heat treatment. A method of manufacturing an electronic component device, comprising: a heat treatment step of connecting to the conductive land by the connecting means and simultaneously fixing the nonconductive sheet to the insulating substrate.

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