JP2008010465A - Semiconductor memory device - Google Patents

Abstract

Provided is a complementary memory cell capable of suppressing the occurrence of variations in electrical characteristics even when misalignment occurs in the formation process.
A complementary memory cell includes two memory units. Each of the memory units MU includes a memory capacitor in a portion where the active region 3 and the upper electrode 22 overlap in the semiconductor substrate. Of the two memory capacitors included in the complementary memory cell, one upper electrode 22 covers a predetermined first direction side end in the active region 3, and the other upper electrode 22 extends in the first direction in the active region 3. The second direction side end opposite to is covered.
[Selection] Figure 4

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device provided with complementary memory cells constituted by two memory units.

  In a system LSI (Large-Scale Integration) in which a memory for storing data and a logic circuit for performing predetermined arithmetic processing are integrated on the same semiconductor chip, an SRAM (Static Random Access Memory) is generally used as the memory. ing. However, when a large-capacity memory is required, a DRAM (Dynamic Random Access Memory) that requires a smaller memory cell area than the SRAM is mounted together. By doing so, it is possible to suppress an increase in chip area and to reduce costs, and various methods have been devised.

  For example, as shown in Patent Document 1 below, there is a method of configuring a DRAM memory cell using a logic circuit formation process (logic process) as it is. That is, in this method, a DRAM memory transistor (access transistor) having the same structure as a logic transistor is used. In a DRAM memory capacitor (storage node), a part of the active region of the substrate is used as a lower electrode, a film of the same material as the gate oxide film of the logic transistor is used as a dielectric film, and an electrode of the same material as the gate electrode of the logic transistor is used. A planar type capacitor having the upper electrode as the upper electrode is used. According to this method, even when DRAMs are mixedly mounted, no extra process is required.

  Further, the memory device of Patent Document 1 is characterized in that a normal DRAM cell (DRAM cell comprising one memory transistor and one capacitor) is combined into two to store 1-bit data ( (See FIG. 4 of Patent Document 1). That is, two DRAM cells store data complementary to each other, and at the time of reading, data signals complementary to each other are read to a pair of bit lines connected thereto. As a result, the amplitude of the read signal is twice that of a normal DRAM cell, so that data retention characteristics are improved, and noise is canceled by performing complementary operations of the two DRAM cells, enabling high-speed operation. The advantage of becoming is obtained. Such a memory cell composed of two memory cells each storing a complementary signal is called a “complementary memory cell”.

  On the other hand, Patent Documents 2 and 3 show a technique for improving the planar type capacitor of the DRAM cell found in Patent Document 1 by adding some process steps to the logic process. For example, as shown in FIG. 2 of Patent Document 3, a recess (cavity) in which a side wall portion of the active region is exposed is formed on an element isolation film (field insulating film) that defines the active region in the semiconductor substrate. The memory capacitor of the DRAM cell has a three-dimensional structure extending from the upper surface of the active region to the side wall portion thereof. Thereby, the effective area of the memory capacitor is increased, and the capacity can be increased. Note that, in Patent Document 3, as shown in FIGS. 4 and 5, when a recess is formed in the element isolation film, an impurity having a conductivity type different from that of the substrate is implanted to form a lower electrode of the capacitor. A technique for improving the performance of the capacitor by forming a low-resistance impurity diffusion layer in the portion is also proposed.

JP 2003-217280 A Special table 2004-527901 JP 2005-5690 A

  In this specification, for convenience of explanation, each of two memory cells (unit storing 1-bit data) constituting a complementary memory cell is referred to as a “memory unit”.

  As described above, each of the two memory units included in the complementary DRAM cell has the same configuration as a normal DRAM cell composed of one memory transistor and one memory capacitor. As the capacitor, a planar capacitor having an active region of the substrate as a lower electrode is used. Further, since the upper electrode of the memory capacitor is shared by a plurality of memory units, it is usually arranged so as to straddle a plurality of active regions. Therefore, when a misalignment occurs in the alignment between the active region and the upper electrode during the formation process, the area where the active region and the upper electrode overlap changes, and the capacitance value of the memory capacitor changes. In the conventional complementary DRAM, a so-called “folded bit wiring” layout has been taken, so that the misalignment causes a large variation in the capacity of the memory capacitor among the plurality of complementary DRAM cells constituting the cell array. (Details will be described later). This causes a decrease in yield and becomes a problem.

  If the capacity of the memory capacitor is increased, the influence of the variation can be reduced. However, for that purpose, it is necessary to increase the formation area of the memory capacitor, and there is a limit because it hinders high integration of the memory cells. Further, if the tolerance of misalignment in the process of forming the memory capacitor is set to be small, the above problem of variation will be suppressed. However, since the accuracy of the exposure apparatus and inspection apparatus is limited, the tolerance is limited. If this is too small, the photolithography process is frequently re-executed, which undesirably decreases the production efficiency.

  The present invention has been made to solve the above problems, and a semiconductor having a complementary memory cell that can suppress variation in electrical characteristics even when misalignment occurs in the formation process. An object is to provide a storage device.

  The semiconductor memory device according to the present invention is a semiconductor memory device including complementary memory cells each including two memory units, and each of the memory units uses a part of an active region in a semiconductor substrate as a first electrode, A capacitor having a second electrode formed on the first electrode through a dielectric film; and the two capacitors included in the complementary memory cell include a pattern of the active region and a second electrode in the formation process If the misalignment with the pattern occurs in a direction in which the area where the active region and the second electrode overlap in one capacitor is reduced, the misalignment causes the misalignment between the active region and the second capacitor in the other capacitor. The two electrodes are laid out so that the area where they overlap is increased.

  According to the present invention, even when misalignment between the active region and the second electrode of the capacitor occurs, an effect of suppressing the fluctuation of the electrical characteristics of the complementary memory cell can be obtained. Therefore, the yield can be improved. Compared with the prior art, the effect can be obtained without increasing the formation area of the memory capacitor or reducing the allowable value of misalignment, so that high integration and reduction in manufacturing efficiency are not accompanied.

<Embodiment 1>
FIG. 1A is a basic circuit diagram of a general 1-transistor 1-capacitor DRAM cell. The DRAM cell 100 includes a memory transistor 101 that functions as an access transistor that performs data writing, refreshing, reading, and the like, and a memory capacitor 102 that accumulates charges according to data. In this example, the memory transistor 101 is a P-channel MOS transistor. The gate terminal of the MOS transistor 101 is connected to the word line WL, one of the source / drain terminals is connected to the bit line BL, and the other is connected to one terminal of the capacitor 102. The other terminal of the capacitor 102 is connected to a predetermined power source.

  FIG. 1B is a basic circuit diagram of a complementary DRAM cell 200 having the DRAM cell 100 shown in FIG. 1A as a memory unit. As shown in FIG. 1B, one complementary DRAM cell 200 is composed of two DRAM cells (memory units) 100 sharing a word line WL. The two memory units 100 operate so as to read and write complementary data signals. That is, complementary data signals are input / output to / from the pair of bit lines BL and ZBL to which the complementary DRAM cell 200 is connected. According to the complementary DRAM cell 200, the amplitude of the read signal can be doubled that of the normal DRAM cell of FIG. 1A, and noise is canceled by the two memory units 100 performing complementary operations. Therefore, high speed operation becomes possible.

FIG. 2 is a diagram for explaining the configuration of the semiconductor memory device according to the first embodiment of the present invention, and is a layout diagram showing the configuration of a complementary DRAM cell array. Normally, memory units constituting a complementary DRAM cell are repeatedly arranged in a matrix to form a memory cell array (memory block). In the figure, four complementary DRAM cells (ie, eight memory units) and their connections are shown. Two sense amplifiers are representatively shown. For convenience of illustration, the sense amplifiers SA ₁ and SA ₂ (generic name “sense amplifier SA”) and the bit lines BL ₁ , ZBL ₁ , BL ₂ , and ZBL ₂ (generic name “bit line BL”) are schematically illustrated. Yes. The sense amplifier SA may be a “shared sense amplifier” (one in which one sense amplifier is shared in a time division manner by two or more pairs of bit lines) employed in Patent Document 1.

As shown in FIG. 2 in this embodiment, the bit lines BL _1, ZBL ₁ to be connected to the sense amplifier SA _1, respectively extend in opposite directions with the sense amplifier SA ₁ in the middle. Similarly, the bit lines BL _2, ZBL ₂ to be connected to the sense amplifier SA _2, respectively extend in opposite directions with the sense amplifier SA ₂ in the center. That is, the arrangement of the sense amplifiers SA ₁ and SA ₂ is a so-called “open bit line system”. The word lines WL ₁ and WL ₂ are disposed so as to intersect the bit lines BL ₁ and BL ₂ , and the word lines ZWL ₁ and ZWL ₂ are disposed so as to intersect the bit lines ZBL ₁ and ZBL ₂ . The intersections of the bit lines BL ₁ , BL ₂ , ZBL ₁ , ZBL ₂ (generic name “bit line BL”) and the word lines WL ₁ , WL ₂ , ZWL ₁ , ZWL ₂ (generic name “word line WL”), respectively. In addition, eight memory units MU _{1 to} MU ₈ (generic name “memory unit MU”) are formed.

FIG. 3 is a cross-sectional view showing the configuration of the memory unit MU. Since all of the memory units MU _{1 to} MU ₈ basically have the same configuration, only one of them is shown in FIG. FIG. 3 corresponds to a cross section along the bit line BL in the memory unit MU of FIG. 2 and 3, the same elements are denoted by the same reference numerals.

  As shown in FIG. 3, the memory unit MU is formed on an N-type silicon semiconductor substrate 1. An isolation trench 2 is formed on the semiconductor substrate 1, thereby defining an active region 3 in the semiconductor substrate 1. An isolation insulating film 4 is formed in the isolation trench 2.

The memory transistor of the memory unit MU includes a silicon oxide gate oxide film 11 formed on the upper surface of the semiconductor substrate 1 and a polysilicon gate electrode 12 formed on the gate oxide film 11 (corresponding to the word line WL in FIG. 2). In addition, a P ⁻ -type LDD (Lightly Doped Drain) region 13 and a P ⁺ -type source / drain region 14 are formed on both sides of the gate oxide film 11 on the semiconductor substrate 1.

In the memory capacitor of the memory unit MU, a part of the active region 3 is a lower electrode (first electrode), and a P ⁺ type impurity diffusion layer 20 is formed in that part. A polysilicon upper electrode 22 (second electrode) is formed on the surface of an impurity diffusion layer 20 (hereinafter referred to as “lower diffusion layer 20”) serving as a lower electrode through a dielectric layer 21 of silicon oxide (SiO ₂ ). The In the present embodiment, side walls 15 and 25 are formed on the side surfaces of the gate electrode 12 and the upper electrode 22, respectively. The lower diffusion layer 20 is connected to the source / drain region 14 of the memory transistor through the LDD region 13 below the sidewall 25. Thereby, the wiring resistance between the memory capacitor and the memory transistor is reduced.

  The memory transistor and the memory capacitor are covered with a silicon oxide interlayer insulating film 26, and a bit line 28 (corresponding to the bit line BL in FIG. 2) is formed on the interlayer insulating film 26. A bit line contact 27 that electrically connects the bit line 28 and the source / drain region 14 is formed in the interlayer insulating film 26. The bit line 28 is covered with an interlayer insulating film 29. Although omitted here, a silicide layer may be formed on each of the gate electrode 12, the source / drain region 14, and the upper electrode 22 as necessary.

  A feature of the layout of the semiconductor memory device of this embodiment will be described. As shown in FIG. 3, the upper electrode 22 of the memory capacitor is formed so as to cover the end of the active region 3. As can be seen from FIG. 2, two memory units MU are formed in one active region 3 so as to sandwich the bit line contact 27 therebetween. Therefore, the left and right end portions of the active region 3 are respectively covered with the two upper electrodes 22 included in the two memory units MU formed therein.

  In the present embodiment, one memory unit MU having the upper electrode 22 covering the left end (first direction side end) of the active region 3 and the upper side covering the right end (second direction side end). Each complementary DRAM cell is laid out so that one complementary DRAM cell is constituted by a pair with one memory unit MU having the electrode 22.

For example, in the example of FIG. 2, the upper electrodes 22 of the memory units MU ₁ , MU ₃ , MU ₅ , MU ₇ cover the left end of the active region 3, respectively, and the memory units MU ₂ , MU ₄ , MU _6. , MU ₈ upper electrodes 22 respectively cover the right end of the active region 3. Therefore, in this case, the memory units MU ₁ and MU ₄ , the memory units MU ₂ and MU ₃ , the memory units MU ₅ and MU ₈ , and the memory units MU ₆ and MU ₇ are complemented respectively. Type DRAM cell is constructed. In other words, each complementary DRAM cell covers a pair of memory units MU having the upper electrode 22 covering the outer end of the active region 3 or the inner end of the active region 3 with the sense amplifier SA as the center. The memory unit MU having the upper electrode 22 is composed of a pair.

  Hereinafter, the effects of the layout will be described with reference to FIGS. FIG. 4 is a top view when misalignment between the pattern of the active region 3 and the pattern of the upper electrode 22 occurs in the process of forming the semiconductor memory device of FIG. In the example of FIG. 4, the positions of the gate electrode 12 and the upper electrode 22 are shifted to the right with respect to the active region 3 (details will be described later, but the gate electrode 12 and the upper electrode 22 are formed in the same process). Therefore, when the position of the upper electrode 22 is shifted, the position of the gate electrode 12 is similarly shifted).

When such misalignment occurs, the area where the upper electrode 22 and the active region 3 overlap is reduced in the memory units MU ₁ , MU ₃ , MU ₅ , and MU ₇ . Conversely, in the memory units MU ₂ , MU ₄ , MU ₆ , MU ₈ , the area where the upper electrode 22 and the active region 3 overlap increases. That is, a set of the memory units MU ₁ and MU _4, a set of the memory units MU ₂ and MU _3, a set of the memory units MU ₅ and MU ₈ , and a set of the memory units MU ₆ and MU ₇ constituting the complementary DRAM cell. In each, the capacity of one memory capacitor is reduced, but the capacity of the other memory capacitor is increased.

On the other hand, FIG. 5 is a top view showing a layout of a complementary DRAM cell array in a conventional semiconductor memory device. In the conventional complementary DRAM cell, a so-called “folded bit line system” has been adopted in order to suppress the influence of noise generated between the bit lines. That as shown in FIG. 5, the bit lines BL _1, ZBL ₁ to be connected to the sense amplifier SA ₁ extends in the same direction with respect to the sense amplifier SA _1. The word lines WL _{101 to} WL ₁₀₄ are arranged so as to cross the bit lines BL ₁ and ZBL ₁ , and eight memory units MU _{101 to} MU ₁₀₈ are formed at each of the intersections. The configurations of the individual memory units MU _{101 to} MU ₁₀₈ are the same as those in FIG.

In the case of the conventional folded bit line system, one complementary DRAM cell is constituted by a set of memory units MU adjacent in the extending direction of the word line WL. That is, in FIG. 5, they are complemented by a set of memory units MU ₁₀₁ and MU _105, a set of memory units MU ₁₀₂ and MU _106, a set of memory units MU ₁₀₃ and MU ₁₀₇ , and a set of memory units MU ₁₀₄ and MU ₁₀₈ , respectively. Type DRAM cell is constructed. In this conventional layout, each complementary DRAM cell has a pair of memory units MU having an upper electrode 22 covering the left end of the active region 3 or an upper portion covering the right end of the active region 3. The memory unit MU having the electrodes 22 is constituted by a set.

  FIG. 6 is a top view when misalignment between the pattern of the active region 3 and the pattern of the upper electrode 22 occurs in the process of forming the semiconductor memory device of FIG. In the example of FIG. 6, the positions of the gate electrode 12 and the upper electrode 22 are shifted to the right with respect to the active region 3.

When such a shift occurs, in the memory units MU ₁₀₁ , MU ₁₀₃ , MU ₁₀₅ , and MU ₁₀₇ , the overlapping area between the upper electrode 22 and the active region 3 decreases. On the contrary, in the memory units MU ₁₀₂ , MU ₁₀₄ , MU ₁₀₆ , and MU ₁₀₈ , the overlapping area between the upper electrode 22 and the active region 3 increases. That is, the capacity of the two memory capacitors is reduced in the set of memory units MU ₁₀₁ and MU _{105 and} the set of memory units MU ₁₀₃ and MU ₁₀₇ constituting the complementary DRAM cell, and the set of memory units MU ₁₀₂ and MU ₁₀₆ and the memory. In the set of the units MU ₁₀₄ and MU ₁₀₈ , the capacity of the two memory capacitors is increased.

  FIG. 7 is a graph showing changes over time in the potentials of the bit line pair BL and ZBL when reading data in a complementary DRAM cell. Here, data “1” is written in the complementary DRAM cell (“H (High)” is written in the memory capacitor of the memory unit connected to the bit line BL, and the memory connected to the bit line ZBL). It is assumed that “L (Low)” is written in each capacitor of the unit.

Until the time t ₁ when the read operation is started, the bit lines BL and ZBL are both equalized to a predetermined bit line potential (in the example of FIG. 7, it is set to 1/2 of the power supply voltage VDD). When the word line potential rises at time t ₁ , the memory transistors of each memory unit are turned on, and the charges accumulated in the respective memory capacitors are read to the bit lines BL and ZBL until time t ₂ . In this example, data “H” is read out to the bit line BL and data “L” is read out to the bit line ZBL, so that the potential of the bit line BL rises and the potential of the bit line ZBL falls. Curves V _BL0 and V _ZBL0 indicated by solid lines in FIG. 7 indicate the potentials of the bit lines BL and ZBL when there is no misalignment between the active region 3 and the upper electrode 22, respectively. Further, the potential difference ΔV ₀ shown in the figure is a potential difference between the bit lines BL and ZBL after data is read in this case.

Then, an amplification operation by the sense amplifier is performed at times t _{3 to} t ₄ . At this time, if the potential difference between the bit lines BL and ZBL is larger than the limit sensitivity of the normal operation of the sense amplifier, the bit line potential is normally amplified, the potential V _BL0 of the bit line BL becomes the power supply potential VDD, and the bit line ZBL The potential V _ZBL0 becomes the ground potential GND.

On the other hand, the curves V _BL11 and V _ZBL11 shown by the alternate long and _short dash line in FIG. 7 are obtained when the capacitances of the two memory capacitors of the two memory units are increased due to misalignment between the active region 3 and the upper electrode 22. The potentials of the bit lines BL and ZBL are shown (curves V _BL11 and V _ZBL11 after time t ₃ are omitted). This corresponds to the set of memory units MU ₁₀₂ and MU _{106 and} the set of memory units MU ₁₀₄ and MU ₁₀₈ in FIG. A potential difference ΔV ₁₁ shown in FIG. 7 is a potential difference between the bit lines BL and ZBL after data is read in this case.

Since both capacities of the two memory capacitors are increased due to the misalignment, the potential V _BL11 is greatly increased and the potential V _ZBL11 is greatly decreased as compared with the case where there is no misalignment. As a result, the potential difference ΔV ₁₁ becomes larger than ΔV ₀ when there is no misalignment, and the bit line potential is normally amplified at time t ₃ .

Curves V _BL12 and V _ZBL12 shown by broken lines in FIG. 7 indicate the bit lines when the capacitances of the two memory capacitors of the two memory units are reduced due to misalignment between the active region 3 and the upper electrode 22. The potentials of BL and ZBL are shown (curves V _BL12 and V _ZBL12 after time t ₃ are omitted). This corresponds to the set of memory units MU ₁₀₁ and MU _{105 and} the set of memory units MU ₁₀₃ and MU ₁₀₇ in FIG. A potential difference ΔV ₁₂ shown in FIG. 7 is a potential difference between the bit lines BL and ZBL after data is read in this case.

Since both capacities of the two memory capacitors are reduced due to the misalignment, the rising width of the potential V _{BL12 and} the decreasing width of the potential V _ZBL12 are smaller _than when there is no misalignment. As a result, the potential V _ZBL12 becomes smaller than ΔV ₀ when there is no misalignment. If this potential difference ΔV ₁₂ becomes smaller than the limit sensitivity of normal operation of the sense amplifier, the sense amplifier cannot perform normal amplification operation, which causes a malfunction, which causes a problem.

Further, since the electric charge accumulated in the memory capacitor gradually leaks, the potential difference ΔV ₀ shown in FIG. 7 becomes smaller as the time from the writing time to the start of reading becomes longer. If the potential difference ΔV ₀ becomes smaller than the limit sensitivity of the normal operation of the sense amplifier due to the leakage of the charge, the sense amplifier cannot perform a normal amplification operation, and malfunction occurs. The maximum time during which this malfunction does not occur is called the refresh time for that bit. Considering the entire memory cell array including a plurality of memory cells, the refresh time has a distribution corresponding to the variation in the manufacturing process. As for the distribution of the refresh time, for example, the logarithm of the refresh time has a normal distribution.

FIG. 8 is a graph showing the relationship between the refresh time and the cumulative number of failed bits (fail bit number) in a memory cell array composed of a plurality of complementary DRAM cells. In the figure, the horizontal axis is the logarithm of the refresh time, and the vertical axis is the logarithm of the number of fail bits. When the logarithmic distribution of the refresh time is a normal distribution, when it is converted into a characteristic of the number of fail bits and expressed in a graph, as shown by a solid line FBC ₀ in FIG. 8, it linearly starts at a certain time t _ref0. The curve starts to increase and eventually converges gradually to the total number of bits. This time t _ref0 is the refresh time of the first failing bit. If the time t _ref0 is smaller than a predetermined standard value, it is determined as defective.

The refresh time of the complementary DRAM cell depends on the capacity of the memory capacitor (the sum of the capacity of the memory capacitors of the two memory units). For example, when the capacity of the memory capacitor is increased, the refresh characteristic is shifted as indicated by the one-dot chain line FBC _{11 in} FIG. 8, and the refresh time is increased (t _ref11 ). Conversely, when the capacity of the memory capacitor is reduced, the refresh characteristic is shifted as indicated by the broken line FBC _{12 in} FIG. 8, and the refresh time is shortened (t _ref12 ).

Therefore, in the conventional complementary DRAM cell, when a misalignment occurs between the active region 3 and the gate electrode 12 and the upper electrode 22 as shown in FIG. 6, the memory unit MU ₁₀₂ , which increases the capacity of the memory capacitor, The refresh time of the complementary DRAM cells of the set of MU ₁₀₆ and the memory units MU ₁₀₄ and MU ₁₀₈ is increased, and the capacity of the memory capacitor is reduced, and the set of memory units MU ₁₀₁ and MU ₁₀₅ and the memory units MU ₁₀₃ and MU ₁₀₇ are reduced. The refresh time of the set of complementary DRAM cells is shortened. Therefore, the refresh time varies depending on each complementary DRAM cell. Since the refresh time of the entire memory cell array is limited (rate-controlled) to a shorter one, even if the refresh time of a part of the memory cells in the memory cell array is only shorter than the standard value, it is determined as defective. . Therefore, if the variation in refresh time for each complementary DRAM cell increases due to misalignment, the possibility of a decrease in yield increases, which is a problem.

  FIG. 9 is a graph showing temporal changes in the potentials of the bit line pair BL, ZBL at the time of data reading in the complementary DRAM cell according to the present invention, and corresponds to FIG. 7 of the conventional example described above. In this case as well, data “1” is written in the complementary DRAM cell (“H (High)” is written in the memory capacitor of the memory unit connected to the bit line BL, and the memory unit connected to the bit line ZBL). (L (Low) is written in each capacitor).

As described above, in the complementary DRAM cell according to the present embodiment, even if the capacitance of one of the two memory capacitors included in the complementary DRAM cell is reduced due to misalignment, the capacitance of the other memory capacitor is reduced. The layout is large. For example, when the capacity of the memory capacitor of the memory unit connected to the bit line BL becomes small, the capacity of the memory capacitor of the memory unit connected to the bit line ZBL becomes large. Therefore, the potentials of the bit lines BL and ZBL in that case 9 behave as shown by the dotted lines V _BL1 and V _ZBL1 in FIG. That is, compared to the case where there is no misalignment, the increase in the potential V _BL1 is small, but the decrease in the potential V _ZBL1 is large. As a result, the potential difference ΔV ₁ is kept substantially equal to ΔV ₀ when there is no misalignment.

  Even if misalignment occurs, the change in the sum of the capacitance values of the two memory capacitors of the complementary DRAM cell is small, so there is almost no shift in the refresh characteristics as shown in FIG. Variation in the refresh time for each is suppressed.

  As described above, according to the present embodiment, even when misalignment between the active region 3 and the upper electrode 22 occurs, fluctuations in the electrical characteristics of the complementary DRAM cell associated therewith are suppressed, Yield can be improved. Compared with the prior art, the effect can be obtained without increasing the formation area of the memory capacitor or reducing the allowable value of misalignment, so that high integration and reduction in manufacturing efficiency are not accompanied.

  The outline of the manufacturing method of the complementary DRAM cell according to the present embodiment shown in FIG. 3 will be described below. The complementary DRAM cell according to the present embodiment can form a DRAM memory cell by using a logic circuit formation process (logic process).

  10 to 13 are process diagrams of the complementary DRAM cell according to the present embodiment. 10 to 13, the left side is a cross section of a memory cell region where a complementary DRAM cell (cell unit) is formed, and the right side is a cross section of a logic circuit region where a logic circuit is formed.

  First, an isolation trench 2 is formed in the upper part of the semiconductor substrate 1, and an element isolation film 4 is formed in the inside by an HDP (High Density Plasma) oxide film or the like. Thereby, the active region 3 in the semiconductor substrate 1 is defined. Then, a resist pattern 40 having an opening in the pattern of the lower diffusion layer 20 to be the lower electrode is formed. Then, P type ions such as boron ions are implanted using the resist pattern 40 as a mask, thereby forming the lower diffusion layer 20 (FIG. 10).

  After removing the resist pattern 40, the gate oxide film 11 and the gate electrode 12 of the memory transistor, the dielectric layer 21 of the memory capacitor, and the upper electrode 22 are formed by photolithography. That is, the surface of the semiconductor substrate 1 is oxidized to form a silicon oxide film, a polysilicon film is further formed on the entire surface, and these are patterned. Thereby, the gate oxide film 11 and the gate electrode 12 of the memory transistor, the dielectric layer 21 and the upper electrode 22 of the memory capacitor are formed in the memory cell region. At the same time, the gate oxide film 31 and the gate electrode 32 of the logic transistor are formed in the logic circuit region. Then, by implanting P-type ions again, LDD layers 13 and 33 are formed on both sides of the gate electrodes 12 and 32, respectively (FIG. 11).

  Thereafter, a silicon nitride film is deposited on the entire surface and etched back to form sidewalls 15, 25, and 35 on the side surfaces of the gate electrode 12, the upper electrode 22, and the gate electrode 32, respectively. Then, P-type ions are implanted again to form the source / drain region 14 of the memory transistor and the source / drain region 34 of the logic transistor (FIG. 12). At this time, a silicide layer may be formed on the upper surfaces of the gate electrodes 12 and 32, the source / drain regions 14 and 34, and the upper electrode 22 as necessary.

  Thereafter, a silicon oxide film is deposited by an ordinary method to form an interlayer insulating film 26, and a bit line contact 27 and a logic circuit contact 37 are formed therein. At the same time, a word line contact for connecting the gate electrode 12 to the metal word line WL, a contact (cell plate contact) for connecting the upper electrode 22 and the like are also formed. Then, a bit line 28 and a logic circuit wiring 38 are formed on the interlayer insulating film 26 and covered with an interlayer insulating film 29 of silicon oxide, thereby completing a cell unit and a logic transistor (FIG. 13). .

  Through the above steps, the cell unit of the complementary DRAM cell shown in FIG. 3 is formed in parallel with the logic transistor of the logic circuit. That is, in this embodiment, the gate oxide film 11 of the memory transistor, the dielectric layer 21 of the memory capacitor, and the gate oxide film 31 of the logic transistor are formed in the same process (same layer), and further, the gate electrode of the memory transistor 12. The upper electrode 22 of the memory capacitor and the gate electrode 32 of the logic transistor are formed in the same process (same layer). Therefore, the gate oxide film 11 of the memory transistor, the dielectric layer 21 of the memory capacitor, and the gate oxide film 31 of the logic transistor are formed of the same material with substantially the same thickness, and further, the gate electrode 12 of the memory transistor and the upper part of the memory capacitor The electrode 22 and the gate electrode 32 of the logic transistor are formed of the same material with substantially the same film thickness. Therefore, it can contribute to the simplification of the manufacturing process.

<Embodiment 2>
FIG. 14 is a layout diagram showing the configuration of the semiconductor memory device according to the second embodiment. In the present embodiment, a method of arranging memory unit pairs of complementary DRAM cells in which the refresh performance and the like of the entire cell array has the best performance in the semiconductor memory device according to the first embodiment is proposed.

In the example of FIG. 14, the cell array includes m sense amplifiers SA ₁ , SA ₂ ,..., SA _m (generically “sense amplifier SA”) arranged in an open bit line system. That is, the memory mat (memory space) constituting the memory cell array is arranged on the left and right with the sense amplifier SA at the center. In the left memory mat, m bit lines BL ₁ , BL ₂ ,..., BL _m (generically “bit lines BL”) are arranged corresponding to the sense amplifiers SA _{1 to} SA _m , respectively. . Further, in the longitudinal direction, 2n word lines are _{WL 1, WL 2, WL 3} , WL 4, ···, WL 2n-1, WL 2n ( collectively, "the word line WL ') is arranged to intersect their Is done. A memory unit MU is disposed at each intersection of the bit line BL and the word line WL. Here, the memory unit formed at the intersection of the i-th bit line BL _i and the j-th word line WL _j is denoted as a memory unit MU _{i (j)} .

On the other hand, m bit lines ZBL ₁ , ZBL ₂ ,..., ZBL _m (generic name “bit line ZBL”) are arranged in the right memory mat corresponding to each of the sense amplifiers SA _{1 to} SA _m. Is done. A signal complementary to the bit line BL is supplied to the bit line ZBL. Also, 2n word lines ZWL ₁ , ZWL ₂ , ZWL ₃ , ZWL ₄ ,..., ZWL _2n−1 , ZWL _2n (generic name “word line ZWL”) are arranged in the vertical direction intersecting them. Is done. A memory unit MUZ is disposed at each intersection of the bit line BL and the word line WL. Here, the memory unit formed at the intersection of the i-th bit line ZBL _i and the j-th word line ZWL _j is denoted as a memory unit MUZ _{i (j)} .

  Although shown in a simplified manner in FIG. 14, each memory unit MU shown in FIG. 14 has the same configuration as that shown in FIGS.

  Also in the present embodiment, as in the first embodiment, each complementary DRAM cell basically has a memory unit MU having an upper electrode 22 covering the outer end portion of the active region 3 with the sense amplifier SA as the center. Or a pair of memory units MU having the upper electrode 22 covering the inner end of the active region 3. In the present embodiment, in each of the plurality of complementary DRAM cells, when one of the two memory units is far from the sense amplifier SA, the other is disposed closer to the sense amplifier SA. Is laid out.

That is, when attention is paid to the plurality of complementary DRAM cells MU _{1 (j)} connected to the sense amplifier SA ₁ in FIG. 14, the memory unit MU formed outside the active region 3 farthest from the sense amplifier SA ₁ in the left memory mat. Complementary DRAM cells in combination with _{1 (1)} constitute the memory unit MUZ _{1 (} outside the active region 3 arranged closest to the sense amplifier SA ₁ in the right memory mat. ₂₎ . In the left memory mat, the memory unit MU _{1 (2)} formed inside the active region 3 farthest from the sense amplifier SA ₁ is paired closest to the sense amplifier SA ₁ in the right memory mat. The memory unit MUZ _{1 (1)} is formed inside the active region 3 provided.

Further, the second memory mat MU _{1 (3)} formed outside the active region 3 farthest from the sense amplifier SA ₁ in the left memory mat is paired with the second sense amplifier SA in the right memory mat. _The memory unit MUZ _{1 (4)} is formed outside the active region 3 disposed near ₁ . Further, the second memory mat MU _{1 (4)} formed inside the active region 3 farthest from the sense amplifier SA ₁ in the left memory mat is paired with the second sense amplifier SA in the right memory mat. _The memory unit MUZ _{1 (3)} is formed inside the active region 3 disposed near ₁ .

Similarly, a pair of memory units MU _{1 (5)} and MUZ _{1 (6),} a pair of memory units MU _{1 (6)} and MUZ _{1 (5)} ,..., A memory unit MU _{1 (2n-1)} , MUZ pair 1 _(2n), by combining such MUZ _{1 (2n-1)} pairs of the memory unit MU 1 _(2n), is formed respectively complementary memory cell. For each complementary DRAM cell connected to the sense amplifiers SA _{2 to} SA _m , a combination of the memory units MU and MUZ constituting the complementary DRAM cell is selected by the same method. Therefore, in each complementary DRAM cell, the sum of the distance between the sense amplifier SA and one memory unit MU and the distance between the sense amplifier SA and the other memory unit MUZ, that is, the sum of the bit line lengths connecting them is It is almost constant for all complementary DRAM cells.

According to the present embodiment, for example, in a complementary DRAM cell, even if a memory unit MU connected to the bit line BL is far from the sense amplifier SA and a read delay occurs due to the resistance of the bit line BL, Since the memory unit MUZ connected to the line ZBL is near the sense amplifier SA, such a delay does not occur on the bit line ZBL side. Therefore, the speed at which the potential difference between the bit lines BL and ZBL (ΔV ₀ in FIG. 9) increases is faster than when both memory units MU and MUZ are arranged farther from the sense amplifier SA, for example. As a result, the entire memory cell array can be read at a higher speed than before.

<Embodiment 3>
In the first and second embodiments, the configuration of the complementary DRAM cell is laid out using the open bit line method. In general, however, the open bit line method is more capacitively coupled between bit lines than the folded bit line method. It is known that it is susceptible to noise caused by it.

In the third embodiment, therefore, a low dielectric constant film (low-k) having a dielectric constant lower than that of silicon oxide (SiO ₂ ) is used as an interlayer insulating film for insulating the bit lines BL from the first and second embodiments. Membrane). That is, for example, in FIG. 3, a low-k film is used for the interlayer insulating film 29 covering the bit line 28. Examples of the low-k film include an SiOF film, an organic SOG (Spin On Glass) film, an HSQ (Hydrogensilsesquioxane), and a CVD organic silicon oxide film.

  According to the present embodiment, the interlayer insulating film that insulates between the bit lines has a low dielectric constant, and the weak point of the open bit line system that is easily affected by noise between the bit lines is improved. Therefore, the reliability of the semiconductor memory device is improved as compared with the first and second embodiments.

  In the present embodiment, not only the interlayer insulating film 29 but also an interlayer insulating film 26 in which the bit line contact 27 is formed, an interlayer insulating film (not shown) higher than the interlayer insulating film 29, etc. A low-k membrane may be used.

<Embodiment 4>
In the above embodiment, the memory capacitor is a planar capacitor, but in Embodiment 4, a three-dimensional capacitor as shown in Patent Documents 2 and 3 is applied.

  15 and 16 are cross-sectional views of the memory unit of the complementary DRAM cell according to the fourth embodiment. FIG. 17 is a top view thereof, and FIGS. 15 and 16 correspond to cross sections taken along lines AA and BB in FIG. 17, respectively. That is, FIG. 15 is a cross section on the active region 3 of the memory unit, and FIG. 16 is a cross section of the isolation region between the memory units adjacent in the extending direction of the word line WL (gate electrode 12).

  As shown in FIGS. 15 to 17, in the memory unit of the fourth embodiment, a recess 50 exposing the side surface of the active region 3 is formed on the element isolation film 4 below the upper electrode 22. The side surface of the active region 3 (inner wall of the isolation trench 2) is exposed in the recess 50, and the memory capacitor has a three-dimensional structure extending from the active region 3 to the inner wall of the isolation trench 2. That is, as shown in FIG. 15, the lower diffusion layer 20 and the dielectric layer 21 are formed so as to extend from the active region 3 to the inner wall of the isolation trench 2, and a part of the upper electrode 22 is in the recess 50. It is formed to enter. As a result, not only the upper surface of the active region 3 but also the side surfaces of the active region 3 contribute to the effective area of the memory capacitor, and the capacitance can be increased.

  Next, a process for forming a complementary DRAM cell (memory unit) according to the present embodiment will be described. First, as in the first embodiment, the isolation trench 2 is formed in the semiconductor substrate 1, and the element isolation film 4 is formed therein. Then, a resist pattern 40 serving as a mask is formed at the time of ion implantation for forming the lower diffusion layer 20. In the first embodiment, ion implantation for forming the lower diffusion layer 20 is performed following the formation of the resist pattern 40. However, in this embodiment, the etching using the resist pattern 40 as a mask is performed in the present embodiment. Thus, the recess 50 is formed by removing the upper part of the element isolation film 4. Thereafter, ion implantation for forming the lower diffusion layer 20 is performed. At this time, the lower diffusion layer 20 is also formed on the inner wall of the isolation trench 2 exposed in the recess 50. 18 and 19 are cross-sectional views taken along lines AA and BB immediately after the ion implantation, respectively.

  The subsequent steps are the same as those described in the first embodiment with reference to FIGS. That is, the gate oxide film 11, the gate electrode 12, the dielectric layer 21, and the upper electrode 22 are formed by photolithography. At this time, the gate oxide film 11 is also formed on the inner wall of the isolation trench 2, and a part of the gate oxide film 11 is formed to be embedded in the isolation trench 2.

  Thereafter, an LDD region 13 is formed by ion implantation. Then, after forming the sidewalls 15 on the side surfaces of the dielectric layer 21 and the upper electrode 22, the source / drain regions 14 are formed by ion implantation again. Then, by sequentially forming the interlayer insulating film 26, the bit line contact 27, the bit line 28, and the interlayer insulating film 29, the memory unit according to the present embodiment shown in FIGS. 15 to 17 is formed.

  As described above, the memory unit manufacturing method according to the present embodiment is the same as that shown in the embodiment, except for the etching process for forming the recess 50. That is, although illustration is omitted here, a logic transistor can be formed in parallel with the above manufacturing process.

  Also in the present embodiment, as in the first embodiment, when the capacity of one of the two memory units constituting the complementary DRAM cell is reduced due to misalignment, The set is such that the capacity of the memory capacitor increases. Thereby, the same effect as in the first embodiment can be obtained.

  In particular, in the memory unit of the present embodiment, since the side surface 51 of the active region 3 also contributes to the effective area of the memory capacitor, the capacitance varies greatly due to misalignment, and the electrical characteristics vary between the memory units. Easy to grow. Therefore, the present invention that can suppress the variation is effective.

  The present invention can also solve the problems peculiar to the complementary DRAM cell comprising the memory units having the configurations shown in FIGS. This will be described below.

As shown in FIGS. 15 to 17, the width W _{R of the} recess 50 is formed wider than the interval between the active regions 3 (the width of the isolation trench 2) in the cross section along the line AA. Thereby, the side surface (indicated by reference numeral 51 in FIG. 17) of the active region 3 in the extending direction of the gate electrode 12 is also exposed in the recess 50. Thereby, the side surface 51 also contributes to the effective area of the memory capacitor.

Although the capacity of the memory capacitor can be increased as the width W _{R of the} recess 50 is increased, the width W _R needs to be smaller than the width W _P of the upper electrode 22 including the sidewall 25. Otherwise, in the cross section of FIG. 16, the portion embedded in the recess 50 of the upper electrode 22 is exposed on the separation region between adjacent memory units, and the memory units are short-circuited through that portion. This is because. Therefore, normally, the width of the upper electrode 22 is formed wider than the width W _{R of the} recess 50 in consideration of misalignment between the pattern of the recess 50 (opening pattern of the resist pattern 40) and the pattern of the upper electrode 22.

Here, as can be seen from the manufacturing process described above, both the etching mask for forming the recess 50 and the ion implantation mask for forming the lower diffusion layer 20 are the same resist pattern 40. That is, when the width of the upper electrode 22 is made wider than the width W _{R of the} recess 50, the width of the upper electrode 22 is wider than the width of the lower diffusion layer 20, and the lower portions of the upper electrode 22 are below the lower ends. It seems that the diffusion layer 20 is not formed. However, since the width of the lower diffusion layer 20 is expanded from the profile (shown by a dotted line in FIG. 15) immediately after the formation due to the diffusion of impurities by heat treatment after the formation, it is not usually a problem.

However, when a misalignment between the pattern of the recess 50 (opening pattern of the resist pattern 40) and the pattern of the upper electrode 22 occurs, even after the diffusion of impurities, the bottom of the end of the upper electrode 22 as shown in FIG. There is a possibility that a portion (indicated by E in FIG. 20) where the lower diffusion layer 20 is not formed is generated. In this case, since the LDD region 13 and the lower diffusion layer 20 under the sidewall 25 of the upper electrode 22 are separated, the wiring resistance between the memory transistor and the memory capacitor at the time of charge writing and reading is increased. End up. In the memory unit having the configuration of FIG. 15 as described above, this problem is likely to occur because the width of the upper electrode 22 needs to be wider than the width W _{R of the} recess 50.

  However, also in this embodiment, if the memory unit of the complementary DRAM cell is laid out in the same manner as in the first embodiment, as a result, when one wiring resistance increases, the other wiring resistance decreases. The above problems are reduced.

FIG. 3 is a circuit diagram of a general DRAM cell and a complementary DRAM cell. 2 is a top view showing a layout of a complementary DRAM cell array according to the first embodiment. FIG. 2 is a cross-sectional view of a memory unit constituting the complementary DRAM cell array according to the first embodiment. FIG. FIG. 6 is a diagram for explaining an effect of the first embodiment. It is a top view which shows the layout of the conventional complementary DRAM cell array. It is a figure for demonstrating the problem of the conventional complementary DRAM cell. It is a figure for demonstrating the problem of the conventional complementary DRAM cell. It is a figure for demonstrating the problem of the conventional complementary DRAM cell. FIG. 6 is a diagram for explaining an effect of the first embodiment. FIG. 6 is a process diagram showing a method of manufacturing a complementary DRAM cell according to the first embodiment. FIG. 6 is a process diagram showing a method of manufacturing a complementary DRAM cell according to the first embodiment. FIG. 6 is a process diagram showing a method of manufacturing a complementary DRAM cell according to the first embodiment. FIG. 6 is a process diagram showing a method of manufacturing a complementary DRAM cell according to the first embodiment. FIG. 6 is a top view showing a layout of a complementary DRAM cell array according to a second embodiment. FIG. 6 is a cross-sectional view of a memory unit constituting a complementary DRAM cell array according to a fourth embodiment. FIG. 6 is a cross-sectional view of a memory unit constituting a complementary DRAM cell array according to a fourth embodiment. FIG. 10 is a top view of a memory unit constituting a complementary DRAM cell array according to a fourth embodiment. FIG. 10 is a process diagram illustrating a method for manufacturing a complementary DRAM cell according to a fourth embodiment. FIG. 10 is a process diagram illustrating a method for manufacturing a complementary DRAM cell according to a fourth embodiment. It is a figure for demonstrating the effect of Embodiment 4. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Isolation trench, 3 Active area | region, 4 Element isolation film | membrane, 11 Gate oxide film, 12 Gate electrode, 13 LDD area | region, 14 Source / drain area | region, 20 Lower diffused layer, 21 Dielectric layer, 22 Upper electrode, 40 resist patterns, 50 recesses.

Claims (12)

A semiconductor memory device comprising complementary memory cells comprising two memory units,
Each of the memory units is
A capacitor having a second electrode formed on a part of an active region in a semiconductor substrate as a first electrode and a dielectric film on the first electrode,
The two capacitors included in the complementary memory cell are:
If the misalignment between the pattern of the active region and the pattern of the second electrode in the formation process occurs in a direction in which the area where the active region and the second electrode overlap in one of the capacitors is reduced, that position The semiconductor memory device is laid out so that an area where the active region and the second electrode overlap in the other capacitor increases due to misalignment. The semiconductor memory device according to claim 1,
The second electrode of one of the two capacitors included in the complementary memory cell covers a first direction side end of the active region, and the other second electrode is the second electrode of the active region. A semiconductor memory device characterized by covering a second direction side end opposite to the one direction side end. The semiconductor memory device according to claim 1,
A sense amplifier for amplifying the output of the complementary memory cell;
The sense amplifier is
A semiconductor memory device, wherein the semiconductor memory device is disposed between two memory units constituting the complementary memory cell. The semiconductor memory device according to claim 3,
Each of the two capacitors included in the complementary memory cell includes:
The semiconductor memory device, wherein the second electrode covers an outer end portion of the active region with the sense amplifier as a center. The semiconductor memory device according to claim 3,
Each of the two capacitors included in the complementary memory cell includes:
The semiconductor memory device, wherein the second electrode covers an inner end portion of the active region with the sense amplifier as a center. A semiconductor memory device according to any one of claims 3 to 5,
A plurality of the complementary memory cells;
In the plurality of complementary memory cells,
A semiconductor memory device, wherein one of two memory units is disposed farther from the sense amplifier and the other is disposed closer to the sense amplifier. The semiconductor memory device according to claim 3,
A plurality of complementary memory cells;
The plurality of complementary memory cells are
The second electrode of the capacitor is composed of two memory units covering the outer end of the active region with the sense amplifier as a center;
A semiconductor memory device comprising: the second electrode of the capacitor including two memory units covering an inner end portion of the active region with the sense amplifier as a center. The semiconductor memory device according to claim 7,
In the plurality of complementary memory cells,
A semiconductor memory device, wherein one of two memory units is disposed farther from the sense amplifier and the other is disposed closer to the sense amplifier. The semiconductor memory device according to claim 1, wherein:
The active region is
It is defined by a trench formed in the semiconductor substrate,
The capacitor of the memory unit extends from the active region to the inner wall of the trench. A semiconductor memory device according to any one of claims 1 to 9, wherein
The memory unit is
A memory transistor connected to the capacitor;
The gate insulating film and the gate electrode of the memory transistor are
A semiconductor memory device, wherein each of the capacitors is formed of the same layer as the dielectric film and the second electrode of the capacitor. The semiconductor memory device according to claim 10,
It further includes a logic circuit that performs predetermined arithmetic processing,
The memory transistor is
A semiconductor memory device, which is formed of the same layer as a logic transistor included in the logic circuit. 12. A semiconductor memory device according to claim 1, wherein
A plurality of bit lines connected to each of the memory units;
The interlayer insulating film that insulates between the plurality of bit lines,
A semiconductor memory device characterized by being formed of a low dielectric constant film having a dielectric constant lower than that of silicon oxide (SiO ₂ ).

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