JP2007328864A - Buffered ferroelectric capacitor latch circuit - Google Patents

Abstract

The conventional main ferroelectric memory reads data destructively and requires rewriting, or memory cells are arranged in a matrix and control is performed without destroying data. . Therefore, the control circuit is complicated and the cycle time for reading data is long, so that it is not easy to work in a general IC.
A ferroelectric capacitor having a ferroelectric thin film, a latch circuit made of two inverter circuits composed of MOSFETs, and a resistance means are combined to automatically set a signal potential at power-off when the power is turned on. It was set as the structure to restore.
[Selection] Figure 1

Description

  The present invention relates to a configuration of a latch circuit including a field effect transistor, a ferroelectric capacitor, and resistance means when a nonvolatile circuit is incorporated in a semiconductor integrated circuit.

  In recent years, the importance of electrically writable and erasable nonvolatile memories in the memory field has increased. Further, it is often required to incorporate a nonvolatile circuit that can be written to and erased from a part of the integrated circuit.

  There are various types of nonvolatile memories, but ferroelectric memories are attracting attention from the viewpoints of high speed, low voltage characteristics, low power consumption, and the like. There are various specific configurations of the ferroelectric memory as shown in the following examples.

  An example of a ferroelectric memory is a ferroelectric capacitor that defines two states depending on the remanent polarization state inside the ferroelectric film, and two types of voltages having different polarities at the voltage exceeding the coercive electric field of the ferroelectric thin film at the time of writing. The internal polarization state of 1 or 0 is created by the application method, and after the storage state due to remanent polarization, the charge is taken out by applying a voltage higher than the coercive electric field of the ferroelectric thin film at the time of reading. There is a method for detecting the internal storage state. FIG. 22, FIG. 24, FIG. 25, and FIG. 26 show this method simply.

  FIG. 22 is a sectional view showing the structure of a ferroelectric capacitor. In FIG. 22, 2240 is a ferroelectric thin film made of an inorganic ferroelectric material, and 2241 and 2242 are electrodes made of metal. A ferroelectric capacitor shown by a broken line 2249 is constituted by a structure in which the ferroelectric thin film 2240 is sandwiched between the metal electrodes 2241 and 2242.

  FIG. 24 shows the polarization charge-applied voltage characteristics of the ferroelectric capacitor shown in FIG. In FIG. 24, a curve passing through characteristic points 2401, 2402, 2403, 2404, 2405, and 2406 is a voltage V applied between the first terminal 2241 and the second terminal 2242 of the ferroelectric capacitor in FIG. The characteristic of the polarization charge Q is represented. A characteristic point 2401 in FIG. 24 shows a state in which a positive voltage V higher than that of the first terminal 2241 is applied to the second terminal 2242 in FIG. 22, and a characteristic point 2404 in FIG. 24 corresponds to the second terminal 2241 in FIG. A state in which a voltage V higher than 2242 is applied is shown. In the characteristic point 2401 and the characteristic point 2404 in FIG. 24, the internal polarization is positive / negative and reverse. When the potential difference between the first terminal and the second terminal of the ferroelectric capacitor that was in the state of the characteristic point 2401 is opened with 0, the internal polarization is stored as remanent polarization, and the state shown in the characteristic point 2402 is obtained. When the potential difference between the first terminal and the second terminal of the ferroelectric capacitor that was in the state of the characteristic point 2404 is opened with 0, the internal polarization is stored as remanent polarization and the state shown in the characteristic point 2405 is obtained. Therefore, the internal polarization charge of the ferroelectric capacitor and the applied voltage have hysteresis characteristics, and at the same time, the terminals at both ends of the ferroelectric capacitor are opened, and even if the voltage is set to 0, the residual polarization varies depending on the previous state. Have. It can be seen that this state corresponds to the characteristic point 2402 and the characteristic point 2405, and that nonvolatile data can be stored in the form of remanent polarization.

  In FIG. 24, the polarization charge at the characteristic point 2404 remains as residual polarization even when the power is turned off as described above, but the polarization charge at this time is not limited to this. The same polarization remains for a while even when the voltage is applied in the opposite direction. It disappears when the characteristic point 2406 is reached. The voltage at this time is called a coercive voltage.

  The states of the internal polarization of the ferroelectric capacitors corresponding to the characteristic points 2401 to 2406 in FIG. 24 are schematically shown in FIGS. 25 (A) to (F), respectively. However, the applied voltage V in FIG. 24 is positive or negative with reference to the electrode of the upper capacitor in FIG. In FIG. 25, a ferroelectric capacitor surrounded by a circle inside two electrode plates and indicated by + and − represents a polarization charge, and a symbol indicated by + and − outside the electrode plate is simply It represents an electric charge. As can be seen from FIGS. 24 and 25, even when the voltage applied to the ferroelectric thin film becomes zero, the remanent polarization inside the ferroelectric thin film remains different depending on the previous state and history. In other words, in both the states of (B) and (E) of FIG. 25, the applied voltage is 0, but the polarity of the internal remanent polarization is completely reversed.

Also, as shown in FIG. 24, when a voltage V (ΔV _B ) is applied between the terminals from the state where the terminals at both ends of the ferroelectric capacitor are opened, the characteristic point 2404 is moved. At this time, if the previous state is the characteristic point 2402, the charge of ΔQ1 shown in FIG. 24 is taken out, and if it is the state of the characteristic point 2405, the charge of ΔQ0 is taken out. Since it is apparent from FIG. 24 that ΔQ1 >> ΔQ0, the difference in the previous state stored as the remanent polarization can be discriminated through an appropriate detection circuit and can be used as data 1 or 0.

  Note that the symbol shown in FIG. 23A or 23B is used as a symbol in the circuit diagram of the ferroelectric capacitor having the above structure and characteristics. Here, FIG. 23A is basically used when used on a circuit in which a ferroelectric capacitor exhibits hysteresis characteristics. FIG. 23B is basically used when the ferroelectric capacitor is used on a circuit that does not exhibit hysteresis characteristics. In such a case, although it has the same structure as a ferroelectric capacitor, it does not exhibit hysteresis and simply functions and functions as an electrostatic capacitor having a large relative dielectric constant. Sometimes.

  FIG. 26 shows an example of a circuit configuration that actually performs the above ferroelectric capacitor. FIG. 26 is a circuit diagram showing the structure of a unit memory cell of a ferroelectric memory device that stores 1-bit nonvolatile data by using one transistor and one ferroelectric capacitor. In FIG. 26, reference numeral 2611 denotes a ferroelectric capacitor, and 2612 denotes an N-type insulated gate field effect transistor (hereinafter sometimes abbreviated as MOSFET. Note that MOSFET is a metal-oxide-semiconductor-field-effect-transistor). Reference numeral 2613 denotes a word line, which is connected to the gate electrode of the MOSFET 2612. Reference numeral 2614 denotes a bit line which is connected to an electrode serving as a source or drain of the MOSFET 2612. Reference numeral 2615 denotes a plate line connected to one end of the ferroelectric capacitor 2611. The other end of the ferroelectric capacitor 2611 is connected to the drain or source electrode of the MOSFET 2612. By the above circuit, the potential applied to the ferroelectric capacitor 2611 is supplied to the bit line 2614 and the plate line 2615, and the MOSFET 2612 is turned on (ON) and turned off (OFF) by the word line 2613. Read operation is performed. This method is a method generally called destructive reading because it takes out charges when reading data, that is, destroys the data.

Next, FIG. 27, FIG. 28, and FIG. 29 show three conventional examples of so-called nondestructive read ferroelectric memories that do not destroy data when data is read.
FIG. 27 is a circuit diagram of a non-destructive read ferroelectric memory disclosed in Patent Document 2. In FIG. In FIG. 27, an inverter circuit composed of a P-type MOSFET 2711 and an N-type MOSFET 2713 and an inverter circuit composed of a P-type MOSFET 2712 and an N-type MOSFET 2714 are connected to each other to form a latch circuit. The output of each inverter circuit and the plate line 2722 Ferroelectric capacitors 2701 and 2702 are provided between them. In addition, a non-destructive and non-destructive readout ferroelectric memory is provided by providing access MOSFETs 2715 and 2716, word lines 2721 and data lines 2723 and 2724, and combining a so-called static random access memory and a ferroelectric capacitor. It is embodied.

  FIG. 28 is a circuit diagram of a non-destructive read ferroelectric memory disclosed in Patent Document 3. In FIG. In FIG. 28, the gate electrodes and drain electrodes of N-type MOSFETs 2813 and 2814 are connected to each other, and a ferroelectric substance is provided between the drain electrodes of the N-type MOSFETs 2813 and 2814 and the control plate line 2822 as a load. Capacitors 2801 and 2802 are provided. Further, a non-destructive read ferroelectric memory is realized by providing access MOSFETs 2815 and 2816, word lines 2821 and data lines 2823 and 2824, and combining them.

FIG. 29 is a circuit diagram of a non-destructive read ferroelectric memory disclosed in Non-Patent Document 1. In FIG. 29, the input terminals and output terminals of the inverter circuits 2921 and 2922 with control signals are connected to each other to form a latch circuit, and the ferroelectric capacitors 2901 and 2902 are connected to the output terminals of the inverter circuits 2921 and 2922 with control signals, respectively. Is provided. Further, by controlling the transmission gates 2924 and 2925 and the control signals ENB and CL in FIG. 29, a non-destructive read ferroelectric memory is realized.
The above-described non-destructive readout circuit methods shown in FIGS. 27, 28, and 29 all require a special sequence and timing to control the plate line connected to one side of the ferroelectric capacitor. It is.

JP-A-11-39882 JP 2001-283484 A JP 2003-59259 A “Nikkei Electronics January 14, 2002 issue” published by Nikkei BP, p. 26-27

  However, the conventional ferroelectric memory has the following problems. The method of destructively reading data by the method described with reference to FIGS. 22, 24, 25, and 26 or the method disclosed in Patent Document 1 requires rewriting of lost data after reading. Therefore, since a write operation is performed after data is read, a control circuit with an excessively large number of elements and a time that cannot be ignored are required, which affects the access time and cycle time and shortens the lifetime of the device. .

  In addition, the method shown in FIGS. 27, 28, and 29 of nondestructive reading, or the method shown in Patent Document 2, 3 or Non-Patent Document 1, includes control of each control signal including control of a plate line as a memory operation. Because the operation procedure is required, when embedding a non-volatile memory as a so-called embedded type in an integrated circuit, it is necessary to design it with the memory control in mind, giving restrictions to the overall control of the integrated circuit, and dedicated memory It is difficult for general logic-based designers to have knowledge of handling.

  In addition, since the conventional circuit example of the non-destructive reading is premised on a configuration as a dedicated memory, a relatively small-capacity readable / writable non-volatile memory is provided in the integrated circuit, although it is good for a large-scale memory. In the case of the built-in circuit, the size of the peripheral circuit and the control circuit occupy a large area, which is not suitable for efficiently mounting a small-capacity nonvolatile memory.

  Accordingly, the present invention solves such problems, and the object of the present invention is a readable / writable non-volatile circuit, and a special control method when data is read or written. Providing a ferroelectric memory and its circuit that can be handled in the same way as a normal insulated gate field-effect transistor circuit without requiring a procedure, and occupies a small area, and is suitable for being easily embedded in an integrated circuit. It is to be.

In order to solve the above-described problems and achieve the object of the present invention, each invention is configured as follows.
In other words, the first invention includes first and second ferroelectric capacitors, and first and second inverter circuits that use the first power supply terminal and the second power supply terminal as power supplies, and the first inverter The input terminal and the output terminal of the circuit and the second inverter circuit are connected to each other to form a latch circuit, and the first ferroelectric capacitor is connected between the output terminal and the input terminal of the first inverter circuit; The second ferroelectric capacitor is connected between the output terminal and the input terminal of the second inverter circuit to form a ferroelectric capacitor latch circuit, and a buffer circuit including a first and second resistance means is provided for the strong circuit. The dielectric capacitor latch circuit is connected to the output terminals of the first and second inverter circuits.

  According to a second invention, in the first invention, the ferroelectric capacitor latch circuit includes a first and second ferroelectric capacitors, first, second, third and fourth capacitors, A first power source terminal and a first power source terminal and a second power source terminal as a power source, and a latch circuit in which the input terminal and the output terminal of the first inverter circuit and the second inverter circuit are connected to each other. The first ferroelectric capacitor is connected between the output terminal of the first inverter circuit and the input terminal, and the second ferroelectric capacitor is input to the output terminal of the second inverter circuit. The first capacitor is connected between the output terminal of the first inverter circuit and the second power supply terminal, and the second capacitor is connected between the output terminal of the second inverter circuit and the second power supply. Connected between terminals The third capacitor is connected between the output terminal of the first inverter circuit and the first power supply terminal, and the fourth capacitor is connected between the output terminal of the second inverter circuit and the first power supply terminal. Is.

  According to a third aspect of the invention, in addition to the second aspect of the invention, the ferroelectric capacitor latch circuit further includes a first capacitor circuit between the output terminal of the first inverter circuit and the input terminal of the second inverter circuit. The second resistance means is interposed between the output terminal of the second inverter circuit and the input terminal of the first inverter circuit via the resistance means.

  According to a fourth aspect of the present invention, in addition to the third aspect, the ferroelectric capacitor latch circuit has a third configuration between one end of the first ferroelectric capacitor and the output terminal of the first inverter circuit. The fourth resistance means is interposed between one end of the second ferroelectric capacitor and the output terminal of the second inverter circuit through the resistance means.

  According to a fifth invention, in the second, third, or fourth invention, a part or all of the first, second, third, and fourth capacitors of the ferroelectric capacitor latch circuit are the first, It is formed with the same structure as the second ferroelectric capacitor.

  According to a sixth aspect of the present invention, in any one of the first to fourth aspects, the first and second inverter circuits of the ferroelectric capacitor latch circuit include a first conductivity type insulated gate field effect transistor and a second Of the first conductivity type insulated gate field effect transistor, the source electrode of the first conductivity type insulated gate field effect transistor is connected to a first power supply terminal, and the second conductivity type insulated gate field effect transistor. The source electrode of the type transistor is connected to the second power supply terminal, and the drain electrode and the gate electrode of the two insulated gate field effect transistors are connected to each other.

  According to a seventh invention, in the third or fourth invention, polysilicon is used for a part or all of the resistance means of the ferroelectric capacitor latch circuit.

  According to an eighth invention, in the third or fourth invention, an insulated gate field effect transistor is used for a part or all of the resistance means of the ferroelectric capacitor latch circuit.

  According to a ninth invention, in any one of the first to fourth inventions, the ferroelectric thin film constituting the ferroelectric capacitor of the ferroelectric capacitor latch circuit is made of an inorganic ferroelectric substance.

  According to a tenth aspect of the present invention, in any one of the first to fourth aspects, the ferroelectric thin film constituting the ferroelectric capacitor of the ferroelectric capacitor latch circuit is made of an organic ferroelectric.

  In an eleventh aspect based on the first aspect, part or all of the resistance means in the buffer circuit uses polysilicon.

  In a twelfth aspect according to the first aspect, a part or all of the resistance means in the buffer circuit uses an insulated gate field effect transistor.

  As described above, according to the present invention configured as described above, the latch circuit constituted by two inverter circuits has two stable states, and in either of the stable states, the ferroelectric capacitor has its stability. The polarization is caused by the potential in the state, and the residual polarization is memorized even when the power is turned off, and even after the power is turned on again, the bias of the charge due to the residual polarization of the ferroelectric capacitor causes the data retention state of the latch circuit when the power is turned off. The configuration is such that it returns quickly and eliminates the influence of the external connection state immediately after the power is turned on again by the buffer circuit.

  The inverter circuit in the ferroelectric latch circuit is composed of P-type and N-type insulated gate field effect transistors.

  Further, a resistance means is interposed between the inverter circuit and the ferroelectric capacitor in the ferroelectric capacitor latch circuit. Further, a resistance means is interposed between the output terminals and the input terminals of the two inverters constituting the latch circuit.

  Further, part or all of the resistance means in the ferroelectric capacitor latch circuit and the buffer circuit is formed of polysilicon.

  Further, a part or all of the resistance means in the ferroelectric capacitor latch circuit and the buffer circuit is constituted by an insulated gate field effect transistor.

  The ferroelectric thin film of the ferroelectric capacitor is configured to use an inorganic ferroelectric or an organic ferroelectric.

  Therefore, according to the above configuration, the data retention state at the time of power-off is reliably restored after the power is turned on again by the bias of charge due to the residual polarization of the ferroelectric capacitor reflecting the data of the latch circuit at the time of power-off. There is an effect.

  In addition, the configuration of the latch circuit itself serves as both a data write circuit and a data output circuit, eliminating the need for an extra control circuit and read / write procedure, resulting in high-speed and fewer circuit elements, and a small capacity non-volatile There is an effect that it is possible to provide a circuit that is very suitable for the LSI with built-in memory from the viewpoint of cost and occupied area.

  In addition, the use of the buffer circuit eliminates the influence of the external circuit connection state on the ferroelectric capacitor latch circuit when the power is turned on again, so the ferroelectric capacitor latch circuit can be easily connected to other circuits. As a result, the electrical symmetry can be secured, and stable operation can be expected.

  Moreover, there is an effect that the operation is stabilized by appropriately using the resistance means.

  In addition, since the inverter circuit is formed of an insulated gate field effect transistor, there is an effect that an integrated circuit with stable characteristics and manufacturing processes can be provided at low cost.

  Further, by appropriately using an inorganic ferroelectric material or an organic ferroelectric material, there is an effect that the application range is widened, manufacturing is easy, and stability is increased. As a result, the quality reliability is increased and the manufacturing cost is reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1 of the buffer type ferroelectric capacitor latch circuit of the present invention)
FIG. 1 is a circuit diagram showing a first example of a buffered ferroelectric capacitor latch circuit according to the present invention. In FIG. 1, a ferroelectric capacitor latch circuit is surrounded by a broken line 101, and a broken line 111 and a broken line 112 are buffer circuits. The specific configuration of the ferroelectric capacitor latch circuit 101 of FIG. 1 is the same as that of FIG. 2, and details will be described later. Further, although the buffer circuits 111 and 112 in FIG. 1 are configured by the resistance means 121 and 122, since the buffer circuit has various circuit configurations, details will be described later.

  The basic function of FIG. 1 is that when the ferroelectric capacitor latch circuit 101 stores the signal potential at the time of power-off in a ferroelectric capacitor, which is a nonvolatile memory element, and the power is turned on again. Is to quickly return to the signal potential when the power is shut off. The buffer circuits 111 and 112 block the influence of the external circuit when the power is turned on, so that the operation of the ferroelectric capacitor latch circuit is performed reliably.

  Now, in the buffer type ferroelectric capacitor latch circuit of the present invention, the ferroelectric capacitor latch circuit 101 is a circuit that forms the basis of the function and is not generally known. The latch circuit will be described first.

(Ferroelectric capacitor latch circuit)
Here, the configuration and operation of the ferroelectric capacitor latch circuit will be described first. In addition, since the ferroelectric capacitor latch circuit can be configured in various ways, examples will be described below in order.
(Embodiment 1 of a ferroelectric capacitor latch circuit)
FIG. 2 is a circuit diagram showing a first example of a ferroelectric capacitor latch circuit.
In FIG. 2, 11 and 12 are ferroelectric capacitors. 13 is an N-type insulated gate field effect transistor (MOSFET), and 15 is a P-type MOSFET. The source electrode of the N-type MOSFET 13 is connected to the negative power supply terminal having the potential of V _SS , the source electrode of the P-type MOSFET 15 is connected to the positive power supply terminal having the potential of V _DD , and the N-type MOSFET 13 and the P-type MOSFET 15 The gate electrodes are connected to each other and the drain electrodes are also connected to each other, and the inverter circuit 135 is configured by the N-type MOSFET 13 and the P-type MOSFET 15.

Reference numeral 14 denotes an N-type MOSFET, and reference numeral 16 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 14 is connected to a negative power supply terminal having a potential of V _SS , the source electrode of the P-type MOSFET 16 is connected to a positive power supply terminal having a potential of V _DD , and the N-type MOSFET 14 and the P-type MOSFET 16 The gate electrodes are connected to each other, and the drain electrodes are also connected to each other. The N-type MOSFET 14 and the P-type MOSFET 16 constitute an inverter circuit 146.

  The output of the inverter circuit 135 is connected to the input of the inverter circuit 146 through resistance means 197 formed of polysilicon. The output of the inverter circuit 146 is connected to the input of the inverter circuit 135 through the resistance means 198 formed of the polysilicon. As described above, the inverter circuit 135 and the inverter circuit 146 constitute a latch circuit.

The output of the inverter circuit 135 is connected to the input / output terminal 17 via the resistance means 195. The ferroelectric capacitor 11 has one end connected to the input / output terminal 17 and the other end connected to the input of the inverter circuit 135. One end of the capacitor 191 is connected to the input / output terminal 17 and the other end is connected to the positive power supply terminal V _DD . One end of the capacitor 193 is connected to the input / output terminal 17 and the other end is connected to the negative power supply terminal V _SS .

The output of the inverter circuit 146 is connected to the input / output terminal 18 through the resistance means 196. One end of the ferroelectric capacitor 12 is connected to the input / output terminal 18, and the other end is connected to the input of the inverter circuit 146. One end of the capacitor 192 is connected to the input / output terminal 18, and the other end is connected to the positive power supply terminal V _DD . One end of the capacitor 194 is connected to the input / output terminal 18 and the other end is connected to the negative power supply terminal V _SS .

  In the above, ferroelectric capacitors 11 and 12, N-type MOSFETs 13 and 14, P-type MOSFETs 15 and 16, capacitors 191 and 192, capacitors 193 and 194, resistance means 195 and 196, and resistance means 197 and 198 have the same shape, respectively. Yes, the same characteristics. In addition, it is desirable that the layout pattern in which the above elements are arranged and connected is also the same or symmetrical.

Since the inverter circuit 135 and the inverter circuit 146 constitute a latch circuit as described above, the latch circuit has two stable states. That is, the input / output terminal 17 is −V _SS corresponding to the low potential, the input / output terminal 18 is + V _DD corresponding to the high potential, and the input / output terminal 17 is + V _DD corresponding to the high potential. The input / output terminal 18 is in the second state of −V _SS corresponding to a low potential.

FIG. 3 is a circuit diagram that expresses FIG. 2 in a functionally easy-to-understand manner. FIG. 4 shows a stable state when power is supplied in the circuit diagram of FIG. FIG. 4 (41A) shows the first state, and (42A) shows the second state. That is, in the first state, the input / output terminal 17 is −V _SS corresponding to a low potential, and the input / output terminal 18 is + V _DD corresponding to a high potential. In the second state, the input / output terminal 17 is + V _DD corresponding to a high potential, and the input / output terminal 18 is −V _SS corresponding to a low potential. Now, the ferroelectric capacitors 11 and 12 shown in FIGS. 2 and 3 are polarized inside due to the potential state in this state. The states of polarization at this time are shown in FIG. 4 (41A) showing the first state and (42A) showing the second state, and the polarization state inside the ferroelectric capacitor in each state is expressed. In other words, the ferroelectric capacitors 11 and 12 have a positive polarity on the capacitor side on the input / output terminal 17 side and a capacitor on the input / output terminal 18 side when the input / output terminal 17 is −V _SS and the input / output terminal 18 is + V _DD. On the electrode side, negative polarity polarization occurs inside the ferroelectric thin film. When the input / output terminal 17 is + V _DD and the input / output terminal 18 is −V _SS , the ferroelectric capacitors 11 and 12 have a negative polarity on the input / output terminal 17 side and a negative polarity on the input / output terminal 18 side. The electrode side of the capacitor causes positive polarity polarization inside the ferroelectric thin film.

Next, a case where the power is turned off will be described. In the polarization described above, the polarization charge amount decreases when the power is turned off in FIG. 2, but the residual polarizations at the characteristic points 2402 and 2405 in FIG. 24 remain and are stored. FIG. 4 (41B) and (42B) show the state of internal polarization when the power supply is cut off, that is, when the input / output terminals 17 and 18 are both at zero ground potential. In the circuit diagram of FIG. 2, −V _SS which is a negative power source is set as a ground potential. Now, after turning off the power, the potential of each circuit settles to the ground potential after a while. However, as described above, the internal polarization of the ferroelectric capacitor is stored as remanent polarization.

Next, the case where the power is turned on again will be described. The capacitors 191 and 192 in FIG. 2 have a charge of 0 when the power is turned off. Since one end of the capacitor is connected to the positive power supply terminal + V _DD , the input / output terminals 17 and 18 try to follow the potential on the positive power supply terminal + V _DD side when the power is turned on again. That is, the electrodes of the capacitors on the input / output terminals 17 and 18 side of the ferroelectric capacitors 11 and 12 try to follow the potential on the positive power supply terminal + V _DD side. On the other hand, the capacitors 193 and 194 have zero electric charge when the power supply is cut off, and one end of the capacitor is connected to the negative power supply terminal -V _SS , so that when the power supply is turned on again, The terminal opposite to the input / output terminal 12 tries to follow the potential on the negative power supply terminal −V _SS side.

In practice, if the capacitances of the ferroelectric capacitors 11 and 12 are C _f , the capacitances of the capacitors 191 and 192 are C ₁ , and the capacitances of the capacitors 193 and 194 are C ₂ , the ferroelectric capacitor 11 And the potential V ₁ of the input / output terminals 17 and 18 which are one ends of the terminals 12 and 12 are
V ₁ = V _DD · C ₁ (C _f + C ₂ ) / (C ₂ C _f + C ₁ C ₂ + C ₁ C _f )
The potential V _{2 at} the other end of the ferroelectric capacitors 11 and 12 is
V ₂ = V _DD · (C ₁ C _f ) / (C ₂ C _f + C ₁ C ₂ + C ₁ C _f )
It becomes. Therefore, C _f, C _1, the potential of V _1, V ₂ at power-on by either choose how the value of C ₂ will vary, as an extreme example, C _f << C ₁ and,, C _f « In the case of C ₂ , V ₁ ≈V _DD and V ₂ ≈0. That is, the ferroelectric capacitors 11 and 12 can be applied with a potential close to + V _DD at one end and −V _SS (0 potential) at the other end when the power is turned on. Therefore, a voltage close to the voltage between the power supplies + V _DD is applied to both ends of the ferroelectric capacitor electrode.

  This corresponds to the fact that the voltage V is applied to the ferroelectric capacitor at the characteristic point 2402 or 2405 where the voltage between the electrodes is 0 in the diagram of FIG. At this time, if the residual polarization corresponds to the characteristic point 2405, the amount of change in charge is small, and if it is 2402, the amount of change in charge is large. Here, a small amount of fluctuation in charge means that there is little fluctuation in the potential of the electrode at the other end of the electrode to which a potential is applied, and a large amount of fluctuation in charge means that the other end of the electrode to which a potential is applied. This means that the potential fluctuation of the electrode is large.

Therefore, when the power is turned on again, the input / output terminals 17 and 18 are operated as if + V _DD is applied due to the action of the capacitors 191 and 192. At this time, the internal polarization of the ferroelectric capacitor 11 or 12 is applied. In the electrode on the output terminal 17 or 18 side, the negative remanent polarization, that is, the one in which a positive charge is induced outside the electrode corresponds to the characteristic point 2405 in FIG. There are few. Also, the characteristic point 2402 in FIG. 24 indicates that the internal polarization of the ferroelectric capacitor 11 or 12 induces a positive remanent polarization, that is, a negative charge outside the electrode, on the input / output terminal 17 or 18 side electrode. The charge transfer is large and the potential fluctuation at the other end is also large.

Therefore, for example, when the power is turned on again in the state where there is residual polarization as shown in FIG. 4 (41B), + V _DD is applied to the electrode on the input / output terminal 17 side of the ferroelectric capacitor 11 by the action of the capacitor 191. At this time, the electrode on the input / output terminal 17 side of the ferroelectric capacitor 11 induces a positive remanent polarization, that is, a negative charge outside the electrode in the state of (41B). Therefore, the amount of charge transfer is relatively large and the potential fluctuation is large. Therefore, the other end of the ferroelectric capacitor 11 greatly fluctuates from 0 potential to the positive potential side, and a large positive potential is applied to the input terminal of the inverter circuit 135.

On the other hand, due to the action of the capacitor 192, similarly, the electrode on the input / output terminal 18 side of the ferroelectric capacitor 12 acts as if + V _DD is applied. At this time, the input of the ferroelectric capacitor 12 is activated. In the state of (41B), the electrode on the output terminal 18 side has a negative remanent polarization, that is, a state in which a positive charge is induced outside the electrode, so that the amount of moving charge is relatively small and the potential fluctuation is small. Therefore, the other end of the ferroelectric capacitor 12 hardly fluctuates from 0 potential, and a potential close to 0 potential is applied to the input terminal of the inverter circuit 146. Thus, a relatively large positive potential is applied to the input terminal of the inverter circuit 135, and a potential that is relatively close to 0 potential is applied to the input terminal of the inverter circuit 146. As a result, the latch circuit composed of the inverter circuits 135 and 146 settles to a stable state in which the input / output terminal 17 becomes −V _SS (0 potential) and the input / output terminal 18 becomes + V _DD . This is the state (41A) before the power is turned off. That is, it means that the state before power-off is restored after power-on again.

Actually, C _f , C _1, and C ₂ are values that cannot be ignored. Therefore, V ₁ has a potential lower than + V _DD , V ₂ has a potential higher than 0, and the ferroelectric capacitors 11 and 12 24, only a voltage lower than + V _DD is applied, but it is clear from FIGS. 24 and 25 that there is a difference in charge amount due to the difference in remanent polarization, and the symmetrically configured latch circuit is in its original state. It is biased enough to select.

When the power is turned on again in the second state (42B) in FIG. 4 where there is residual polarization, the capacitor 191 causes the electrode on the input / output terminal 17 side of the ferroelectric capacitor 11 to be applied to the electrode. Although it operates as if it is operated with a potential close to + V _DD , the electrode on the input / output terminal 17 side of the ferroelectric capacitor 11 is negatively remanent in the state of (41B), that is, outside the electrode. In this state, a positive charge is induced, so that the potential fluctuation is small. Therefore, the other end of the ferroelectric capacitor 11 hardly fluctuates from 0 potential, and a potential close to 0 potential is applied to the input terminal of the inverter circuit 135.

On the other hand, due to the action of the capacitor 192, the electrode on the input / output terminal 18 side of the ferroelectric capacitor 12 acts as if a potential close to + V _DD is applied, but at this time, the ferroelectric capacitor Since the 12 electrodes on the input / output terminal 18 side are in the state of (42B), a positive remanent polarization, that is, a state in which a negative charge is induced outside the electrode, the potential fluctuation is large. Therefore, the other end of the ferroelectric capacitor 12 greatly fluctuates from 0 potential to the positive potential side, and a large positive potential is applied to the input terminal of the inverter circuit 146. Thus, a potential that is relatively close to 0 potential is applied to the input terminal of the inverter circuit 135, and a relatively large positive potential is applied to the input terminal of the inverter circuit 146. As a result, the latch circuit composed of the inverter circuits 135 and 146 settles to a stable state in which the input / output terminal 17 becomes + V _DD and the input / output terminal 18 becomes −V _SS (0 potential). This is the state (42A) before the power is turned off. That is, it means that the state before power-off is restored after power-on again.

  As described above, in any of the two stable states, the state is restored to the state before the power is turned off after the power is turned on again due to the residual polarization of the ferroelectric capacitor. FIG. 4 shows the potential and polarization state of the circuit at the time of stabilization before turning off the power, and the state of the potential and polarization of the circuit at the time of turning off the power. The relationship of returning to the state before cutting is schematically expressed.

  It should be noted that resistance means 195, 196, 197, and 198 are provided in FIG. 2 so that the above operation proceeds as intended and promptly. In other words, after the power is turned on again, in a transient short time when the latch circuit goes to the state before the power is turned off, the charge read from the ferroelectric capacitor is prevented from being dissipated to other than the input terminal of the inverter circuit, This prevents unnecessary charges and potentials from entering from other paths.

Further, the structures of the ferroelectric capacitors 11 and 12 in FIGS. 2 and 3 have the structure shown in FIG. In FIG. 22, the ferroelectric thin film 2240 is suitably PZTN, PZT, or SBT. Among these, PZTN is more desirable because it has a large residual polarization and hysteresis characteristics with good squareness. PZT is a generic term for Pb (Zr, Ti) O ₃ , PZTN is a generic term for a part of Ti in PZT replaced with Nb, and SBT is SrBi ₂ Ta ₂ O ₉ or it. It is a generic name for near compositions. Further, platinum (Pt) is generally used for the metal electrodes 2241 and 2242 in FIG.

(Embodiment 2 of a ferroelectric capacitor latch circuit)
FIG. 5 is a circuit diagram showing a second embodiment of the ferroelectric capacitor latch circuit.
In FIG. 5, 11 and 12 are ferroelectric capacitors. 13 is an N-type insulated gate field effect transistor (MOSFET), and 15 is a P-type MOSFET. The source electrode of the N-type MOSFET 13 is connected to the negative power supply terminal having the potential of V _SS , the source electrode of the P-type MOSFET 15 is connected to the positive power supply terminal having the potential of V _DD , and the N-type MOSFET 13 and the P-type MOSFET 15 The gate electrodes are connected to each other and the drain electrodes are also connected to each other, and the inverter circuit 135 is configured by the N-type MOSFET 13 and the P-type MOSFET 15.

Reference numeral 14 denotes an N-type MOSFET, and reference numeral 16 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 14 is connected to a negative power supply terminal having a potential of V _SS , the source electrode of the P-type MOSFET 16 is connected to a positive power supply terminal having a potential of V _DD , and the N-type MOSFET 14 and the P-type MOSFET 16 The gate electrodes are connected to each other, and the drain electrodes are also connected to each other. The N-type MOSFET 14 and the P-type MOSFET 16 constitute an inverter circuit 146.

  The output of the inverter circuit 135 is connected to the input of the inverter circuit 146. The output of the inverter circuit 146 is connected to the input of the inverter circuit 135. As described above, the inverter circuit 135 and the inverter circuit 146 constitute a latch circuit.

The output of the inverter circuit 135 is connected to the input / output terminal 17. The ferroelectric capacitor 11 has one end connected to the input / output terminal 17 and the other end connected to the input of the inverter circuit 135. One end of the capacitor 191 is connected to the input / output terminal 17 and the other end is connected to the positive power supply terminal V _DD . One end of the capacitor 193 is connected to the second terminal of the ferroelectric capacitor 11, the other end is connected to a power supply terminal V _SS of the negative electrode.

The output of the inverter circuit 146 is connected to the input / output terminal 18. One end of the ferroelectric capacitor 12 is connected to the input / output terminal 18, and the other end is connected to the input of the inverter circuit 146. One end of the capacitor 192 is connected to the input / output terminal 18, and the other end is connected to the positive power supply terminal V _DD . One end of the capacitor 194 is connected to the second terminal of the ferroelectric capacitor 12, the other end is connected to a power supply terminal V _SS of the negative electrode.

  In the above, the ferroelectric capacitors 11 and 12, the N-type MOSFETs 13 and 14, the P-type MOSFETs 15 and 16, the capacitors 191 and 192, and the capacitors 193 and 194 have the same shape and the same characteristics. In addition, it is desirable that the layout pattern in which the above elements are arranged and connected is also the same or symmetrical.

  The configuration of FIG. 5 is a configuration in which the resistance means 195, 196, 197, and 198 in the circuit of FIG. 2 are omitted, and the other configurations are the same as the circuit of FIG. In FIG. 4, the output impedance of the inverter circuit 135 is increased by changing the channel lengths of the N-type MOSFET 13 and the P-type MOSFET 15, and the function of the resistance means 195 of FIG. Yes. Similarly, the function of the resistance means 196 in FIG. Further, the resistor means 197 and 198 in FIG. 2 are substituted with polysilicon used for the gate electrodes of the MOSFETs 13, 14, 15 and 16 in FIG. 4 to have substantial functions. Therefore, in FIG. 5, the resistance means 195, 196, 197, and 198 of FIG. 1 are not on the circuit diagram, but the function of the resistance means is substituted, so that a ferroelectric capacitor latch circuit similar to the circuit of FIG. Has function. In the case of FIG. 5, there is an effect that an area occupied by the layout pattern can be reduced.

(Embodiment 3 of a ferroelectric capacitor latch circuit)
FIG. 6 is a circuit diagram showing a third embodiment of the ferroelectric capacitor latch circuit.
In FIG. 6, reference numerals 11 and 12 denote ferroelectric capacitors. Reference numeral 13 denotes an N-type MOSFET, and reference numeral 15 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 13 is connected to the negative power supply terminal having the potential of V _SS , the source electrode of the P-type MOSFET 15 is connected to the positive power supply terminal having the potential of V _DD , and the N-type MOSFET 13 and the P-type MOSFET 15 The gate electrodes are connected to each other and the drain electrodes are also connected to each other, and the inverter circuit 135 is configured by the N-type MOSFET 13 and the P-type MOSFET 15.

Reference numeral 14 denotes an N-type MOSFET, and reference numeral 16 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 14 is connected to a negative power supply terminal having a potential of V _SS , the source electrode of the P-type MOSFET 16 is connected to a positive power supply terminal having a potential of V _DD , and the N-type MOSFET 14 and the P-type MOSFET 16 The gate electrodes are connected to each other, and the drain electrodes are also connected to each other. The N-type MOSFET 14 and the P-type MOSFET 16 constitute an inverter circuit 146.

  The output of the inverter circuit 135 is connected to the input of the inverter circuit 146 through the resistance means 197. The output of the inverter circuit 146 is connected to the input of the inverter circuit 135 through the resistance means 198. As described above, the inverter circuit 135 and the inverter circuit 146 constitute a latch circuit.

The output of the inverter circuit 135 is connected to the input / output terminal 17 via the resistance means 195. The ferroelectric capacitor 11 has one end connected to the input / output terminal 17 and the other end connected to the input of the inverter circuit 135. One end of the high dielectric capacitor 591 is connected to the input / output terminal 17, and the other end is connected to the positive power supply terminal V _DD . One end of the high dielectric capacitor 593 is connected to the second terminal of the ferroelectric capacitor 11, the other end is connected to a power supply terminal V _SS of the negative electrode.

The output of the inverter circuit 146 is connected to the input / output terminal 18 through the resistance means 196. One end of the ferroelectric capacitor 12 is connected to the input / output terminal 18, and the other end is connected to the input of the inverter circuit 146. One end of the high dielectric capacitor 592 is connected to the input / output terminal 18, and the other end is connected to the positive power supply terminal V _DD . One end of the high dielectric capacitor 594 is connected to the second terminal of the ferroelectric capacitor 12, the other end is connected to a power supply terminal V _SS of the negative electrode.

Note that the ferroelectric capacitors 11 and 12 are represented by the symbols in FIG. 23A, and the high-dielectric capacitors 691, 692, 693, and 694 are represented by the symbols in FIG. The ferroelectric capacitors 11 and 12 and the high-dielectric capacitors 691, 692, 693, and 694 have the same structure as shown in FIG. However, there may be a difference in whether a high dielectric capacitor having a high relative dielectric constant is obtained. Here the high dielectric capacitor 691,692,693,694 is is identical to the ferroelectric capacitor in structure, one end of the capacitor is connected to a power supply terminal V _SS power supply terminal V _DD or the negative electrode of the positive electrode Therefore, the polarity of the potential between the terminals is not reversed, and therefore, it is a usage that does not show hysteresis characteristics. Therefore, the symbol in FIG. 23B is used.

Compared with the circuit configuration of FIG. 2, the circuit configuration of FIG. 6 is obtained by replacing the capacitors 191, 192, 193, and 194 in FIG. 2 with high dielectric capacitors 691, 692, 693, and 694, respectively, in FIG. Other than that, FIG. 2 and FIG. 6 have the same configuration. In FIG. 2, capacitors 191, 192, 193, and 194 preferably have large capacitance values that can be compared with the ferroelectric capacitors 11 and 12. In this case, when a nitride material containing silicon dioxide (SiO ₂ ) or nitrogen generally used as a capacitor is sandwiched between metal electrodes, the relative permittivity of the substance is compared with the relative permittivity of the ferroelectric. It is very small and requires a large area. Therefore, in FIG. 6, a high dielectric capacitor having a large relative dielectric constant is used to reduce the occupied area. As described above, the high dielectric capacitors 691, 692, 693 and 694 in FIG. 6 are actually formed in the same structure as the ferroelectric capacitors 11 and 12. The circuit of FIG. 6 has an effect that the occupied area becomes small because the capacitors 191, 192, 193, 194 of the circuit of FIG. 1 become the high dielectric capacitors 691, 692, 693, 694 in FIG.

(Embodiment 4 of a ferroelectric capacitor latch circuit)
FIG. 8 is a circuit diagram showing a fourth embodiment of the ferroelectric capacitor latch circuit.
In FIG. 8, 11 and 12 are ferroelectric capacitors. 13 is an N-type insulated gate field effect transistor (MOSFET), and 15 is a P-type MOSFET. The source electrode of the N-type MOSFET 13 is connected to the negative power supply terminal having the potential of V _SS , the source electrode of the P-type MOSFET 15 is connected to the positive power supply terminal having the potential of V _DD , and the N-type MOSFET 13 and the P-type MOSFET 15 The gate electrodes are connected to each other and the drain electrodes are also connected to each other, and the inverter circuit 135 is configured by the N-type MOSFET 13 and the P-type MOSFET 15.

Reference numeral 14 denotes an N-type MOSFET, and reference numeral 16 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 14 is connected to a negative power supply terminal having a potential of V _SS , the source electrode of the P-type MOSFET 16 is connected to a positive power supply terminal having a potential of V _DD , and the N-type MOSFET 14 and the P-type MOSFET 16 The gate electrodes are connected to each other, and the drain electrodes are also connected to each other. The N-type MOSFET 14 and the P-type MOSFET 16 constitute an inverter circuit 146.

  The output of the inverter circuit 135 is connected to the input of the inverter circuit 146 via a transmission gate resistance means 897 composed of a P-type MOSFET 854 and an N-type MOSFET 853. The output of the inverter circuit 146 is connected to the input of the inverter circuit 135 via a transmission gate resistance means 898 composed of a P-type MOSFET 852 and an N-type MOSFET 851. As described above, the inverter circuit 135 and the inverter circuit 146 constitute a latch circuit.

The output of the inverter circuit 135 is connected to the input / output terminal 17 via the resistance means 195. The ferroelectric capacitor 11 has one end connected to the input / output terminal 17 and the other end connected to the input of the inverter circuit 135. One end of the capacitor 191 is connected to the input / output terminal 17 and the other end is connected to the positive power supply terminal V _DD . One end of the capacitor 193 is connected to the second terminal of the ferroelectric capacitor 11, the other end is connected to a power supply terminal V _SS of the negative electrode.

The output of the inverter circuit 146 is connected to the input / output terminal 18 through the resistance means 196. One end of the ferroelectric capacitor 12 is connected to the input / output terminal 18, and the other end is connected to the input of the inverter circuit 146. One end of the capacitor 192 is connected to the input / output terminal 18, and the other end is connected to the positive power supply terminal V _DD . One end of the capacitor 194 is connected to the second terminal of the ferroelectric capacitor 12, the other end is connected to a power supply terminal V _SS of the negative electrode.

As described above, the resistance means 195, 196, 197, and 198 are used in FIG. 2, but in FIG. 8, transmission gates 897 and 898 using P-type MOSFET and N-type MOSFET are used for the resistance means 197 and 198. Note that the gate electrodes of the P-type MOSFETs 852 and 854 are connected to V _SS, and the gate electrodes of the N-type MOSFETs 851 and 853 are connected to V _DD . The other structure is the same in FIG. 2 and FIG.

FIG. 7 shows a circuit configuration of a general transmission gate. In FIG. 7, 751 is an N-type MOSFET, and 752 is a P-type MOSFET. The source or drain electrodes of the N-type MOSFET 751 and the P-type MOSFET 752 are connected to each other, one end being a terminal 753 and the other end being a terminal 754. The gate electrode of the N-type MOSFET 751 is connected to V _DD, and the gate electrode of the P-type MOSFET 752 is connected to V _SS and both are turned on. The P-type MOSFET 752 easily transmits a high-potential side signal potential, and the N-type MOSFET 751 easily transmits a low-potential signal potential. Accordingly, since the N-type MOSFET 751 and the P-type MOSFET 752 are connected in parallel, the low-potential side signal and the high-potential side signal are transmitted.

  In FIG. 8, transmission gates 897 and 898 using MOSFETs are used as resistance means as described above. In the case of the resistance means using MOSFET, it is easy to maintain the magnitude relationship with the impedance of the inverter circuit by MOSFETs 13, 15, 14 and 16, and it is easy to construct a resistance means with an appropriate impedance, and it is easy to make high resistance, so a small occupation There is an effect that it can be formed with an area.

(Embodiment 5 of a ferroelectric capacitor latch circuit)
FIG. 9 is a circuit diagram showing a fifth embodiment of the ferroelectric capacitor latch circuit.
In FIG. 9, 11 and 12 are ferroelectric capacitors. Reference numeral 13 denotes an N-type MOSFET, and reference numeral 15 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 13 is connected to the negative power supply terminal having the potential of V _SS , the source electrode of the P-type MOSFET 15 is connected to the positive power supply terminal having the potential of V _DD , and the N-type MOSFET 13 and the P-type MOSFET 15 The gate electrodes are connected to each other and the drain electrodes are also connected to each other, and the inverter circuit 135 is configured by the N-type MOSFET 13 and the P-type MOSFET 15.

Reference numeral 14 denotes an N-type MOSFET, and reference numeral 16 denotes a P-type MOSFET. The source electrode of the N-type MOSFET 14 is connected to a negative power supply terminal having a potential of V _SS , the source electrode of the P-type MOSFET 16 is connected to a positive power supply terminal having a potential of V _DD , and the N-type MOSFET 14 and the P-type MOSFET 16 The gate electrodes are connected to each other, and the drain electrodes are also connected to each other. The N-type MOSFET 14 and the P-type MOSFET 16 constitute an inverter circuit 146.

  The output of the inverter circuit 135 is connected to the input of the inverter circuit 146 via a transmission gate resistance means 897 composed of a P-type MOSFET 854 and an N-type MOSFET 853. The output of the inverter circuit 146 is connected to the input of the inverter circuit 135 via a transmission gate resistance means 898 composed of a P-type MOSFET 852 and an N-type MOSFET 851. As described above, the inverter circuit 135 and the inverter circuit 146 constitute a latch circuit.

The output of the inverter circuit 135 is connected to the input / output terminal 17. The ferroelectric capacitor 11 has one end connected to the input / output terminal 17 and the other end connected to the input of the inverter circuit 135. One end of the high dielectric capacitor 691 is connected to the input / output terminal 17, and the other end is connected to the positive power supply terminal V _DD . One end of the high dielectric capacitor 693 is connected to the second terminal of the ferroelectric capacitor 11, the other end is connected to a power supply terminal V _SS of the negative electrode.

The output of the inverter circuit 146 is connected to the input / output terminal 18. One end of the ferroelectric capacitor 12 is connected to the input / output terminal 18, and the other end is connected to the input of the inverter circuit 146. One end of the high dielectric capacitor 692 is connected to the input / output terminal 18, and the other end is connected to the positive power supply terminal V _DD . One end of the high dielectric capacitor 694 is connected to the second terminal of the ferroelectric capacitor 12, the other end is connected to a power supply terminal V _SS of the negative electrode.

  9 has the basic configuration excluding the resistance means 195 and 196 in FIG. 2, the point that high dielectric capacitors 691, 692, 693, and 694 are used as the capacitor in FIG. 6, and the resistance means 897 in FIG. 898 is a combination of the features of using a transmission gate of MOSFET in 898. Therefore, the basic operation and function as the ferroelectric capacitor latch circuit are the same as those in the first, second, third, and fourth embodiments. By taking advantage of each feature, the occupation area is reduced while ensuring stable operation, and a practical configuration is achieved.

  In FIG. 9, there is nothing equivalent to the resistance means 195 and 196 in FIG. 2, but if there are resistance means 897 and 898 by the transmission gate in FIG. 8, the resistance means 195 and 196 can be effectively omitted. Is possible.

  In FIG. 9, high dielectric capacitors 691, 692, 693, 694 are formed with the same structure as the ferroelectric capacitors 11, 12.

(Application examples and improvements of ferroelectric capacitor latch circuits)
Now, an application example in which the ferroelectric capacitor latch circuit described together with the above-described embodiment is used in an actual circuit and points to be further improved will be described below.
First, FIGS. 2, 5, 6, 8, and 9 are given as first, second, third, fourth, and fifth embodiments of the ferroelectric capacitor latch circuit. Is defined and expressed by the circuit symbol of the symbol shown in FIG. Next, an application example using this circuit symbol will be described.

  FIG. 18 shows an example of application in which the above-described ferroelectric capacitor latch circuit is used in an actual circuit. In FIG. 18, reference numeral 1822 denotes an input terminal including a pad for inputting a signal from the outside of the integrated circuit. Reference numeral 1821 denotes a buffer circuit using an inverter circuit, which receives a signal from the pad 1822 and outputs a signal from the output terminal to the inside of the integrated circuit. Reference numeral 1810 denotes the ferroelectric capacitor latch circuit described above, and one input / output terminal is connected to the input terminal of the inverter circuit 1821 and the pad 1822. The impedance when the input / output terminal of the ferroelectric capacitor latch circuit functions as an output terminal is set sufficiently higher than the impedance of the signal source outside the integrated circuit.

  When a control signal is applied to the pad 1822 from the outside of the integrated circuit, a high potential (High) signal or a low potential (Low) signal is supplied. At this time, since the impedance of the signal source of the control signal applied from the outside is sufficiently low, the control signal can be sent to the input terminal of the inverter circuit 1821 without being obstructed by the ferroelectric capacitor latch circuit 1810. The ferroelectric capacitor latch circuit 1810 latches and stores the data information of this control signal. If the input terminal of the inverter circuit 1821 does not always have a high potential (High) or low potential (Low) signal potential, the operation becomes unstable or a through current flows. Therefore, in the absence of the ferroelectric capacitor latch circuit 1810, the control signal must be continuously applied from the outside of the integrated circuit. Here, as shown in FIG. 18, the ferroelectric capacitor latch circuit 1810 is electrically connected to the input terminal 1822 which is a pad, so that the signal stored in the ferroelectric capacitor latch circuit 1810 is input to the inverter circuit 1821. Since it is added to the terminal, there is an effect that it is not necessary to continuously give a signal from outside the integrated circuit. Then, paying attention to the balance between the positive and negative electrostatic capacitances parasitic on the input / output terminal of the ferroelectric capacitor latch circuit 1810, the power is turned off, and then the previous state is maintained even when the power is turned on again. It is a nonvolatile latch circuit that stores and supplies signals.

  The ferroelectric capacitor latch circuit 1810 shown in FIG. 18 uses the signal wiring connected to only one of the two input / output terminals when viewed from the ferroelectric capacitor latch circuit 1810. When restoring data, there is a possibility that the parasitic capacitance may be biased as a factor other than the remanent polarization. Therefore, in order to prevent malfunction, it is desirable to provide a balance by providing a dummy wiring at the input / output terminal at the other end of the input / output terminal to which the signal wiring is connected.

  However, the input terminal 1822 which is a pad may be connected to a circuit outside the integrated circuit, and it has an uncertain element as to what electrical state and condition it is connected to. Therefore, in the ferroelectric capacitor latch circuit 1810 as described above, the technique of “providing a balance by providing a dummy wiring at the other input / output terminal of the input / output terminal to which the signal wiring is connected” is not necessarily a universal technique. is not.

Therefore, the buffered ferroelectric capacitor latch circuit of the present invention which is further improved will be described below.
(About the buffer type ferroelectric capacitor latch circuit of the present invention)
In the following, embodiments of the buffered ferroelectric capacitor latch circuit of the present invention will be described in part with reference to the drawings, although they partially overlap with those described above.

(Embodiment 1 of the buffer type ferroelectric capacitor latch circuit of the present invention)
FIG. 1 is a circuit diagram showing a first embodiment of a buffered ferroelectric capacitor latch circuit according to the present invention. In FIG. 1, a ferroelectric capacitor latch circuit is surrounded by a broken line 101, and a broken line 111 and a broken line 112 are buffer circuits.

  The specific configuration of the ferroelectric capacitor latch circuit 101 of FIG. 1 is the same as that of FIG. 2, has the configuration and functions described in the first embodiment of the ferroelectric capacitor latch circuit, and operates as described above. An internal circuit surrounded by a broken line 111 and a broken line 112 is a buffer circuit. In FIG. 1, resistance means 121 and 122 made of polysilicon form resistance means.

  One end of the buffer circuit 111 is connected to the terminal 17 of the ferroelectric capacitor latch circuit 101, and the other end is a terminal 117 as a buffer type ferroelectric capacitor latch circuit. One end of the buffer circuit 112 is connected to the terminal 18 of the ferroelectric capacitor latch circuit 101, and the other end is a terminal 118 as a buffer type ferroelectric capacitor latch circuit.

  At this time, since the buffer circuits 111 and 112 are provided at both ends when viewed from the ferroelectric capacitor latch circuit 101, the influence of the external circuit is eliminated in the transition period when the power is turned on, and during this time, the connection with the external circuit is eliminated. Whatever the relationship, symmetry as a ferroelectric capacitor latch circuit is ensured, and the intended normal operation is achieved.

  That is, the buffer circuit 111 formed of the resistor 121 and the buffer circuit 112 formed of the resistor 122 alleviate the influence from the outside when the power is turned on, and the ferroelectric capacitor latch circuit 101 is powered by the unique function and operation described above. The signal state at the time of disconnection is restored.

  Therefore, the buffer circuit always uses 111 and 112 as a pair, and ensures circuit symmetry when viewed from the ferroelectric capacitor latch circuit 101.

  In normal operation, the signal state of the ferroelectric capacitor latch circuit 101 is output through the terminals 117 and 118, or the signal state of the ferroelectric capacitor latch circuit 101 is output according to an external signal through the terminals 117 and 118. Rewrite the internal state. Therefore, the impedance ratio between the resistor 121 and the resistor 195 or the impedance ratio between the resistor 122 and the resistor 196 is selected to a value that does not hinder the operation. Since the operations of the ferroelectric capacitors 11 and 12 and the capacitors 191, 192, 193, and 194 are different between when the power is turned on and when the power is steady, an appropriate impedance ratio between the resistors 121 and 122 and the resistors 195 and 196 described above is set. It is possible to select a value that does not hinder the operation.

  At this time, regardless of the various states and conditions of the connection state with the external circuit, “the signal potential when the power is turned off is stored in the non-volatile memory element, and the signal potential when the power is turned off automatically and quickly when the power is turned on again. "I will return."

(Embodiment 2 of the buffer type ferroelectric capacitor latch circuit of the present invention)
FIG. 12 is a circuit diagram showing a second embodiment of the buffer type ferroelectric capacitor latch circuit of the present invention. In FIG. 12, a ferroelectric capacitor latch circuit is surrounded by a broken line 1201, and a buffer circuit is surrounded by a broken line 111 and a broken line 112.

Here, the ferroelectric capacitor latch circuit 1201 has the configuration of FIG. 9 shown in the fifth embodiment.
The buffer circuit 111 is composed of transmission gate resistance means including a P-type MOSFET 1262 and an N-type MOSFET 1261. The buffer circuit 112 is constituted by transmission gate resistance means including a P-type MOSFET 1264 and an N-type MOSFET 1263.

  One end of the buffer circuit 111 is connected to the terminal 17 of the ferroelectric capacitor latch circuit 1201, and one end of the buffer circuit 112 is connected to the terminal 18 of the ferroelectric capacitor latch circuit 1201. A capacitor latch circuit is configured. With the above configuration, the operation of the ferroelectric capacitor latch circuit 1201 is prevented from being disturbed by an external circuit by the buffer circuits 111 and 112, and stable characteristics are ensured.

  At this time, a transmission gate made of a MOSFET is used as a resistance means of the buffer circuit. When the transmission gate by MOSFET is used as the resistance means, it is easy to set the impedance ratio between the MOSFET of the inverter circuit and the transmission gates 198 and 197 of the MOSFET as the resistance means in the ferroelectric capacitor latch circuit 1201 of FIG. Is easy and stable.

(Buffer circuit)
The buffer circuit in the buffer type ferroelectric capacitor latch circuit of the present invention is not limited to FIG. 1 and FIG. Next, another example of the buffer circuit is shown.
(Third example of buffer circuit)
FIG. 14 shows a third example of the buffer circuit. In FIG. 14, a portion surrounded by a broken line 1421 is a transmission gate resistance means including a P-type MOSFET 1462 and an N-type MOSFET 1461. Also, the inside surrounded by a broken line 1422 is a transmission gate resistance means composed of a P-type MOSFET 1464 and an N-type MOSFET 1463. One end of the transmission gate resistance means 1421 is a terminal 117, the other end is connected to one end of the transmission gate resistance means 1422, and the other end of the resistance means 1422 is a terminal 17. 1423 The first terminal a capacitor connected to the connection line of said resistance means 1421 and the resistor unit 1422, a second terminal of the capacitor 1423 is connected to the negative power supply terminal V _SS. The terminals 117 and 17 are two terminals as a buffer circuit. In FIG. 14, two transmission gates 1421 and 1422 and a capacitor 1423 are provided between them, and the influence of the external circuit when the power is turned on can be eliminated by the amount of the capacitor 1423 provided.
When used in a buffer type ferroelectric capacitor latch circuit, two buffer circuits shown in FIG. 14 are used in the same configuration and used as a pair of resistance means.

(Fourth example of buffer circuit)
FIG. 15 shows a fourth example of the buffer circuit. In FIG. 15, a high dielectric capacitor 1523 is characteristic, but has substantially the same configuration as FIG. 14 is different from FIG. 14 in that a high dielectric (ferroelectric) capacitor 1523 is used in FIG. 15 in contrast to a paraelectric capacitor 1423 in FIG. This is because a ferroelectric substance generally has a high relative dielectric constant, so that if a ferroelectric capacitor is used, it can be formed with a small occupied area on a plane to ensure the same capacitance value. . In addition, since the ferroelectric capacitor is already used in the ferroelectric capacitor latch circuit, a new manufacturing process is not required and no cost increase factor occurs.

(Fifth example of buffer circuit)
FIG. 16 shows a fifth example of the buffer circuit. In FIG. 16, polysilicon is used as the resistance means 1661 and 1662 instead of the resistance means 1421 and 1422 of the transmission gate of FIG. When polysilicon is used as the resistance means in the ferroelectric capacitor latch circuit as shown in FIGS. 2, 6, and 8, it is better to design using the polysilicon as the resistance means as the buffer circuit. It is easy to offset, and variations in the manufacturing process are easily offset.

(Sixth example of buffer circuit)
FIG. 17 shows a sixth example of the buffer circuit. 17 is characterized in that a capacitor 1724 is provided, and the other configuration is the same as that of FIG. In contrast to the fifth embodiment of FIG. 16, in the sixth embodiment of FIG. 17, the capacitors 1723 and 1724 are connected to the signal line with respect to the power sources on both the positive and negative sides, so that more symmetry is maintained and the characteristics are maintained. Has the effect of improving.

(Application of buffer type ferroelectric capacitor latch circuit of the present invention)
Next, how to use and application method of the buffer type ferroelectric capacitor latch circuit of the present invention will be described. Here, an equivalent circuit of the buffer type ferroelectric capacitor latch circuit to which the buffer circuit described above is added is defined and expressed by the circuit symbol of the symbol shown in FIG. Further, it is distinguished from FIG. 10 which is a symbol of a simple type ferroelectric capacitor latch circuit.

(Application Example 1 of Buffer Type Ferroelectric Capacitor Latch Circuit of the Present Invention)
FIG. 19 shows a first application example of the buffered ferroelectric capacitor latch circuit of the present invention.
In FIG. 19, a buffer type ferroelectric capacitor latch circuit 1910 is used instead of the ferroelectric capacitor latch circuit 1810 in FIG. Since the buffer type ferroelectric capacitor latch circuit 1910 uses a buffer circuit, the influence of the parasitic capacitance in the input gate portion of the pad 1822 and the inverter circuit 1821 has little influence on the transition period when the power is turned on. The ferroelectric capacitor latch circuit in the buffer type ferroelectric capacitor latch circuit 1910 accurately restores the potential when the power is cut off. That is, a stable characteristic can be obtained without affecting the state of the external circuit such as the pad 1822 and the circuit can be highly versatile. As a further supplement, the other terminal other than the terminal used for connection to the pad input terminal 1822 out of the two terminals of the buffered ferroelectric capacitor latch circuit may be left floating. That is, no special measures such as connection to dummy wiring are required. This is because the symmetry on the circuit seems to be almost secured from the built-in ferroelectric latch circuit due to the effect of the buffer circuit as described above.

(Application 2 of the buffer type ferroelectric capacitor latch circuit of the present invention)
FIG. 21 shows a second application example of the buffer type ferroelectric capacitor latch circuit of the present invention.
In FIG. 21, 2143 and 2144 are NAND circuits (non-logical product circuits) composed of MOSFETs. A first input gate of the NAND circuit 2143 is connected to an output terminal of the NAND circuit 2144, and a second input gate of the NAND circuit 2144 is connected to an output terminal of the NAND circuit 2143. In other words, a latch circuit is configured by drawing the input terminals and output terminals of the two NAND paths 2143 and 2144 from each other. Note that another signal is input to the second input gate of the NAND circuit 2143 and the first input gate of the NAND circuit 2144. Now, the latch circuit by the two NAND paths 2143 and 2144 stores the previous state and plays a role in affecting the next operation. However, only the latch circuit of the NAND paths 2143 and 2144 turns off the power. Then, the data indicating the state disappears, and when the power is turned on again, it is necessary to set the state again in order to perform a desired operation. However, as shown in FIG. 21, the input / output terminal of the buffer type ferroelectric capacitor latch circuit 2141 according to the present invention is connected to the output terminal of the NAND circuit 2143, and the input / output terminal of the buffer type ferroelectric transistor latch circuit 2142 is connected. When connected to the output terminal of the NAND circuit 2144, the state of the latch circuits of the NAND paths 2143 and 2144 is stored, and even after the power is turned off once and turned on again, the latch circuits of the NAND paths 2143 and 2144 Since the state can be reproduced, there is no need to reset the state after the power is turned on again, and there is an effect that the operation becomes possible immediately after the power is turned on again. In FIG. 21, since the buffered ferroelectric capacitor latch circuits 2141 and 2142 are used, normal operation is performed without considering the symmetry of the layout including the NAND paths 2143 and 2144.

(Embodiment 3 of the buffer type ferroelectric capacitor latch circuit of the present invention)
FIG. 13 is a circuit diagram showing a third embodiment of the buffer type ferroelectric capacitor latch circuit of the present invention.
13 is the same as the circuit configuration of FIG. 12 of the second embodiment of the buffer type ferroelectric capacitor latch circuit of the present invention except for the inverter circuit 1311. In FIG. FIG. 13 is different from FIG. 13 in that an inverter circuit 1311 is provided, a terminal 117 is connected to an input gate of the inverter circuit 1311, and an output of the inverter circuit 1311 is connected to a terminal 118. This is an application example of the buffered ferroelectric capacitor latch circuit according to the first embodiment and the second embodiment. In FIGS. 19 and 21, the terminal on one side of the buffered ferroelectric capacitor latch circuit is apparently in a floating state. There may be. However, it is not actually in an electrically floating state by the resistance means of the type ferroelectric capacitor latch circuit and the buffer circuit. It's just an appearance.
On the other hand, in FIG. 13, the inverter circuit 13 avoids the floating state of the terminals from the outside.

(Application Example 3 of Buffer Type Ferroelectric Capacitor Latch Circuit of the Present Invention)
An example using a buffered ferroelectric capacitor latch circuit having a configuration as shown in FIG. 13 is shown in FIG. In FIG. 20, if expressed as a buffered ferroelectric capacitor latch circuit 2010 configured as shown in FIG. 13, the other terminal of the buffered ferroelectric capacitor latch circuit 2010 to which the pad 2022 is connected is also buffered ferroelectric. The potential is further forcibly applied by the inverter circuit in the body capacitor latch circuit 2010. The other end of the buffer type ferroelectric capacitor latch circuit shown in FIGS. 1 and 12 is also applied with a potential through the resistance means of the buffer circuit, so that it does not enter a so-called electrically floating state. In this case, since the final state of the buffered ferroelectric capacitor latch circuit 2010 is determined quickly, there is an effect that if the focus is on only the transient state when the power is turned on, the responsiveness becomes faster. Therefore, in applications where the operation time from power-on to normal operation is expected to be fast, the circuit system as shown in FIG. 13 may be good.

(Other embodiments)
The present invention is not limited to the above embodiment. Here are some examples:
Examples of the buffer type ferroelectric capacitor latch circuit of the present invention are shown in FIGS. 1, 12, and 13, but are not limited thereto. Examples of ferroelectric capacitor latch circuits are shown in FIG. 2, FIG. 5, FIG. 6, FIG. 8, and FIG. 9, and examples of buffer circuits are the circuit examples in FIG. FIG. 17 is shown. As the buffer type ferroelectric capacitor latch circuit of the present invention, a combination of the above-described ferroelectric capacitor latch circuit and the buffer circuit is an effective circuit other than those shown in FIGS.

  In the embodiments of the buffered ferroelectric capacitor latch circuit and the ferroelectric capacitor latch circuit of FIGS. 1, 2, 5, 6, 8, 9, 12, and 13, the P-type MOSFET Although a configuration example of an inverter circuit using an N-type MOSFET has been shown, an inverter circuit other than a MOSFET may be used because the function of the inverter circuit is sufficient. In addition, various other configurations are possible even with a MOSFET.

  Further, in the circuit examples of FIGS. 1, 2, 6, 8, 16, and 17, the example in which the resistance means is formed of polysilicon has been described. However, other than P diffusion, N diffusion, non-doped polysilicon, etc. You may form with the element of.

  In FIGS. 19, 20, and 21, examples of application of the buffered ferroelectric capacitor latch circuit of the present invention to an integrated circuit are given. However, as shown in FIGS. Instead, the same floating prevention may be used for the data bus line.

  Further, for the purpose of storing data, not only the latch circuit of FIG. 21, but also the ferroelectric of the present invention is provided at each position of a signal of a circuit necessary for promptly operating from the previous state after the integrated circuit is turned on again. It is effective to connect a capacitor latch circuit.

  Further, the ferroelectric capacitor latch circuits of the present invention may be arranged in a matrix to efficiently control a memory cell array having a relatively large memory capacity.

Further, in FIG. 22, although PZTN is taken as a preferred example of the inorganic ferroelectric thin film, it is not necessarily related to PZTN. For example, PZT or SBT already mentioned as a ferroelectric may be used. Furthermore, Additional _{BLT (Bi 4X La X Ti 3} O 12), there is a _{(Ba, Sr) TiO 3,} Bi 4 Ti 3 O 12, BaBiNb 2 O 9 , etc.. Moreover, it is innumerable if the composition ratio changes. Alternatively, a material obtained by laminating materials having different compositions in the upper layer portion and the lower layer portion of the ferroelectric thin film may be used.

Also, the metal film can be made of a material other than platinum (Pt) described above as the material of the electrode of the metal film, and Ta, Ti or a Pt / Ti alloy may be used. Alternatively, an oxide conductive film such as RuO ₂ , IrO ₂ , SrRuO ₃ , or RhO ₂ can be used in some cases.

  In the above description, the ferroelectric material used for the ferroelectric capacitor is an inorganic ferroelectric substance such as PZTN, PZT, or SBT. However, in the semiconductor manufacturing line, the inorganic component may cause contamination in the MOS manufacturing process, and the crystallization temperature is often too high to affect the components of the MOSIC. In this case, there is a method of using an organic ferroelectric material for the ferroelectric thin film 2240 in FIG. 22 instead of an inorganic ferroelectric material. Since the organic ferroelectric is formed at a lower temperature than the inorganic ferroelectric, it has less influence on the metal wiring process and the like. As the organic ferroelectric material, PVDF (poly (vinylidene fluoride)), P (VDF / TrFE) (poly (vinylidene fluoride-trifluorethylene)), or odd nylon such as nylon 7 or nylon 11 is suitable.

  Further, when an organic ferroelectric is used as the ferroelectric thin film, the crystal axis of the electrode material can be restricted, so that a wider electrode material can be selected.

  The material to be selected is selected not only in electrical characteristics but also in comprehensive consideration of quality reliability, ease of manufacture, manufacturing cost, and the like.

1 is a circuit diagram showing a first embodiment of a buffered ferroelectric capacitor latch circuit according to the present invention; FIG. 1 is a circuit diagram showing a first embodiment of a ferroelectric capacitor latch circuit used in the present invention; FIG. 1 is a circuit diagram illustrating a first embodiment of a ferroelectric capacitor latch circuit used in the present invention in terms of functions. FIG. The schematic diagram showing each electric potential and polarization state at the time of power supply in the circuit of the 1st example of a ferroelectric capacitor latch circuit used in the present invention at the time of power supply off. The circuit diagram which shows the 2nd Example of the ferroelectric capacitor | condenser latch circuit used in this invention. The circuit diagram which shows the 3rd Example of the ferroelectric capacitor | condenser latch circuit used in this invention. The circuit diagram which shows the circuit structure of the transmission gate used in this invention. The circuit diagram which shows the 4th Example of the ferroelectric capacitor | condenser latch circuit used in this invention. The circuit diagram which shows the 5th Example of the ferroelectric capacitor | condenser latch circuit used in this invention. The circuit diagram which expressed the ferroelectric capacitor latch circuit used in this invention as a symbol. The circuit diagram which expressed the buffer type ferroelectric capacitor latch circuit of the present invention as a symbol. The circuit diagram which shows the 2nd Example of the buffer type ferroelectric capacitor latch circuit of this invention. The circuit diagram which shows the 3rd Example of the buffer type ferroelectric capacitor latch circuit of this invention. The circuit diagram which shows the 3rd Example of the buffer circuit used in this invention. The circuit diagram which shows the 4th Example of the buffer circuit used in this invention. The circuit diagram which shows the 5th Example of the buffer circuit used in this invention. The circuit diagram which shows the 6th Example of the buffer circuit used in this invention. The circuit diagram which shows the 1st application example which applied the ferroelectric capacitor latch circuit used in this invention to the integrated circuit. The circuit diagram which shows the 1st application example which applied the buffer type ferroelectric capacitor latch circuit of this invention to the integrated circuit. The circuit diagram which shows the 3rd application example which applied the buffer type ferroelectric capacitor latch circuit of this invention to the integrated circuit. The circuit diagram which shows the 2nd application example which applied the buffer type ferroelectric capacitor latch circuit of this invention to the integrated circuit. Sectional drawing which shows the structural example of the ferroelectric capacitor used for this invention and the conventional ferroelectric memory device. The circuit diagram which expressed the ferroelectric capacitor or high-dielectric capacitor used for this invention and the conventional ferroelectric memory device as a symbol. The characteristic view which shows the typical hysteresis characteristic of the applied voltage and polarization charge of the ferroelectric thin film of the ferroelectric capacitor used for this invention and the conventional ferroelectric memory device. The schematic diagram which shows the state of the applied voltage and polarization charge of the ferroelectric thin film of the ferroelectric capacitor used for this invention and the conventional ferroelectric memory device. The circuit diagram which shows the 1st example of the structure of the memory cell used for the conventional ferroelectric memory device. The circuit diagram which shows the 2nd example of the structure of the memory cell used for the conventional ferroelectric memory device. The circuit diagram which shows the 3rd example of the structure of the memory cell used for the conventional ferroelectric memory device. The circuit diagram which shows the 4th example of the structure of the memory cell used for the conventional ferroelectric memory device.

Explanation of symbols

11, 12, 2611, 2701, 2702, 2801, 2802, 2901, 2902 ... ferroelectric capacitors, 13, 14, 751, 851, 853, 1261, 1263, 1461, 1463, 2612, 2713, 2714, 2715, 2716 , 2813, 2814... N-type MOSFET, 15, 16, 752, 852, 854, 1262, 1264, 1462, 1464, 2711, 2712, 2815, 2816... P-type MOSFET, 17, 18, 117, 118. , 101, 1201, 1810 ... ferroelectric capacitor latch circuit, 111, 112 ... buffer circuit, 135, 146, 1821, 2923 ... inverter circuit, 191, 192, 193, 194, 1423, 1623, 1723, 1724 ... capacitor, 121 122,195,196,197,198,1661,1662 ... resistor means, 691,692,693,694,1523 ... high dielectric capacitor, 753,754 ... terminal, 897,898,1421,1422,2924,2925 ... Transmission gate, 1822 ... Pad input terminal, 1910, 2010, 2141, 1422 ... Buffer type ferroelectric capacitor latch circuit, 2143, 2144 ... NAND circuit, 2240 ... Ferroelectric thin film, 2241, 2242 ... Capacitor electrode, 2401, 4022 , 2403, 2404, 2405, 2406 ... characteristic points, 2613, 2721, 2821 ... word lines, 2614, 2723, 2724, 2823, 2824 ... bit lines, 2615, 2722, 2822 ... plate lines, 2921, 2922 ... Signal with an inverter circuit.

Claims (12)

The first inverter circuit includes at least a first power terminal and a second power terminal serving as a power source, first and second ferroelectric capacitors, and first and second inverter circuits, and an output of the first inverter circuit. The terminal is connected to the input terminal of the second inverter circuit, the output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit, and the first ferroelectric capacitor has a first terminal. The terminal and the second terminal are connected to the output terminal and the input terminal of the first inverter circuit, and the first terminal and the second terminal of the second ferroelectric capacitor are the output terminal and the input of the second inverter circuit. A ferroelectric capacitor latch circuit configured to be connected to the terminal;
A, a buffer circuit having at least the resistance means of the second, and
The resistor means of the buffer circuit is connected to the output terminal of the first inverter circuit of the ferroelectric capacitor latch circuit, and the resistor means is connected to the output terminal of the second inverter circuit of the ferroelectric capacitor latch circuit. A buffer-type ferroelectric capacitor latch circuit characterized by that. In claim 1,
The ferroelectric capacitor latch circuit comprises:
A first power supply terminal and a second power supply terminal serving as a power source;
A first ferroelectric capacitor and a second ferroelectric capacitor;
First, second, third and fourth capacitors;
A first inverter circuit and a second inverter circuit that use the first power supply terminal and the second power supply terminal as power supplies,
The output terminal of the first inverter circuit is connected to the input terminal of the second inverter circuit, and the output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit,
A first terminal and a second terminal of the first ferroelectric capacitor are respectively connected to an output terminal and an input terminal of the first inverter circuit;
A first terminal and a second terminal of the second ferroelectric capacitor are respectively connected to an output terminal and an input terminal of the second inverter circuit;
The first terminal and the second terminal of the first capacitor are connected to the output terminal of the first inverter circuit and the second power supply terminal, respectively.
The first terminal and the second terminal of the second capacitor are connected to the output terminal of the second inverter circuit and the second power supply terminal, respectively.
A first terminal and a second terminal of the third capacitor are respectively connected to a second terminal of the first ferroelectric capacitor and the first power supply terminal;
A buffer type ferroelectric capacitor latch, wherein the first terminal and the second terminal of the fourth capacitor are connected to the second terminal of the second ferroelectric capacitor and the first power supply terminal, respectively. circuit. In claim 1,
The ferroelectric capacitor latch circuit comprises:
A first power supply terminal and a second power supply terminal serving as a power source;
A first ferroelectric capacitor and a second ferroelectric capacitor;
First, second, third, and fourth capacitors;
First and second resistance means;
A first inverter circuit and a second inverter circuit that use the first power supply terminal and the second power supply terminal as power supplies,
The output terminal of the first inverter circuit is connected to the input terminal of the second inverter circuit via the first resistance means,
The output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit via the second resistance means,
A first terminal and a second terminal of the first ferroelectric capacitor are respectively connected to an output terminal and an input terminal of the first inverter circuit;
A first terminal and a second terminal of the second ferroelectric capacitor are respectively connected to an output terminal and an input terminal of the second inverter circuit;
The first terminal and the second terminal of the first capacitor are connected to the first terminal and the second power supply terminal of the first ferroelectric capacitor, respectively.
A first terminal and a second terminal of the second capacitor are respectively connected to the first terminal and the second power supply terminal of the second ferroelectric capacitor;
A first terminal and a second terminal of the third capacitor are respectively connected to a second terminal of the first ferroelectric capacitor and the first power supply terminal;
A buffer type ferroelectric capacitor latch, wherein the first terminal and the second terminal of the fourth capacitor are connected to the second terminal of the second ferroelectric capacitor and the first power supply terminal, respectively. circuit. In claim 1,
The ferroelectric capacitor latch circuit comprises:
A first power supply terminal and a second power supply terminal serving as a power source;
A first ferroelectric capacitor and a second ferroelectric capacitor;
First, second, third, and fourth capacitors;
First, second, third and fourth resistance means;
A first inverter circuit and a second inverter circuit that use the first power supply terminal and the second power supply terminal as power supplies,
The output terminal of the first inverter circuit is connected to the input terminal of the second inverter circuit via the first resistance means,
The output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit via the second resistance means,
The first terminal of the first ferroelectric capacitor is connected to the output terminal of the first inverter circuit through the third resistor means, and the second terminal is connected to the input terminal of the first inverter circuit, respectively. Connected,
The first terminal of the second ferroelectric capacitor is connected to the output terminal of the second inverter circuit via the fourth resistor means, and the second terminal is connected to the input terminal of the second inverter circuit, respectively. Connected,
The first terminal and the second terminal of the first capacitor are connected to the first terminal and the second power supply terminal of the first ferroelectric capacitor, respectively.
A first terminal and a second terminal of the second capacitor are respectively connected to the first terminal and the second power supply terminal of the second ferroelectric capacitor;
A first terminal and a second terminal of the third capacitor are respectively connected to a second terminal of the first ferroelectric capacitor and the first power supply terminal;
A buffer type ferroelectric capacitor latch, wherein the first terminal and the second terminal of the fourth capacitor are connected to the second terminal of the second ferroelectric capacitor and the first power supply terminal, respectively. circuit. In Claim 2 or Claim 3 or Claim 4,
Part or all of the first, second, third, and fourth capacitors in the ferroelectric capacitor latch circuit are formed in the same structure as the first and second ferroelectric capacitors. A buffer type ferroelectric capacitor latch circuit characterized by the above. In any one of Claims 1-4,
The first inverter circuit or the second inverter circuit in the ferroelectric capacitor latch circuit includes a first conductivity type insulated gate field effect transistor and a second conductivity type insulated gate field effect transistor. And
A source electrode of the first conductivity type insulated gate field effect transistor is connected to a first power supply terminal; a source electrode of the second conductivity type insulated gate field effect transistor is connected to a second power supply terminal; A buffer type ferroelectric capacitor latch circuit characterized in that the drain electrode and gate electrode of the two insulated gate field effect transistors of the first conductivity type and the second conductivity type are connected to each other. . In claim 3 or claim 4,
A buffer type ferroelectric capacitor latch circuit, wherein a part or all of the resistance means in the ferroelectric capacitor latch circuit is made of polysilicon. In claim 3 or claim 4,
A buffer type ferroelectric capacitor latch circuit characterized in that an insulating gate field effect transistor is used for a part or all of the resistance means in the ferroelectric capacitor latch circuit. In any one of Claims 1-4,
A buffer type ferroelectric capacitor latch circuit, wherein a ferroelectric thin film of the ferroelectric capacitor in the ferroelectric capacitor latch circuit is made of an inorganic ferroelectric substance. In any one of Claims 1-4,
A ferroelectric capacitor latch circuit, wherein a ferroelectric thin film of the ferroelectric capacitor in the ferroelectric capacitor latch circuit is made of an organic ferroelectric. In claim 1,
A buffer type ferroelectric capacitor latch circuit characterized in that a part or all of the first and second resistance means in the buffer circuit are made of polysilicon. In claim 1,
A buffer type ferroelectric capacitor latch circuit characterized in that an insulating gate field effect transistor is used for a part or all of the resistance means of the former and the former in the buffer circuit.

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