JP2007328085A - Liquid crystal device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal device and electronic equipment of a FFS system which can suppress occurrence of flickers or burn-in of liquid crystal. <P>SOLUTION: The liquid crystal device 1 has an element substrate 55 which is provided with a plurality of scan lines Y, a plurality of data lines X, and a plurality of pixel electrodes 55. A 2nd insulating film is formed as an under-layer of the pixel electrodes 55, and a common electrode 56 is formed as an under-layer of the 2nd insulating film. This liquid crystal device 1 is provided with a scan line driving circuit 11 which sequentially supplies a selected voltage to the plurality of scan lines, and a data line driving circuit 21 which alternately supplies an image signal of the positive polarity and an image signal of the negative polarity to the plurality of data lines X when scan lines are selected, and writes in image voltages on the basis of the image signals to the pixel electrodes 55 relating to the selected scan lines Y, and the image voltage on the basis of either the positive polarity or the negative polarity is written to each pixel electrode 55 for two or more horizontal scanning periods in one frame period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal device and an electronic apparatus.

  Conventionally, there is a liquid crystal device adopting an FFS (Fringe Field Switching) method as a display method (see, for example, Patent Document 1). The FFS mode liquid crystal device has the following configuration, for example.

  The FFS liquid crystal device includes an element substrate, a counter substrate disposed opposite to the element substrate, and a liquid crystal provided between the element substrate and the counter substrate.

  The element substrate includes a plurality of scanning lines provided at predetermined intervals, and a plurality of data lines that intersect the plurality of scanning lines and are provided at predetermined intervals.

Pixels are provided at intersections between the scanning lines and the data lines. The pixel includes a pixel capacitor including a pixel electrode and a common electrode, and a thin film transistor (hereinafter referred to as a TFT (Thin Film Transistor)) as a switching element. A plurality of pixels are arranged in a matrix to form a display area. Here, as a display device, the row direction may be either vertical or horizontal.
A scanning line is connected to the gate of the TFT, a data line is connected to the source of the TFT, and a pixel electrode is connected to the drain of the TFT.

  In this element substrate, an insulating film is formed under the pixel electrode, and a common electrode is formed under the insulating film. In some cases, an insulating film is formed over the pixel electrode, and a common electrode is formed over the insulating film.

The above FFS mode liquid crystal operates as follows.
That is, by sequentially supplying the selection voltage to the scanning line, all the TFTs related to the certain scanning line are turned on, and all the pixels related to the scanning line are selected. Then, an image signal is supplied to the data line in synchronization with the selection of these pixels. Then, an image signal is supplied to all the selected pixels via the on-state TFTs, and an image voltage based on the image signal is written to the pixel electrode.

When an image voltage is written to the pixel electrode, a potential difference is generated between the pixel electrode and the common electrode, and an electric field substantially horizontal to the element substrate is generated by the potential difference. This electric field changes the alignment of the liquid crystal, and the light transmitted through the liquid crystal changes, so that gradation display is performed.
JP 2002-14374 A

  By the way, an electric field is generated from a place having a high potential toward a place having a low potential. For this reason, in the pixel electrode and the common electrode, when the potential of the other electrode is always higher than the potential of one electrode or the potential of the other electrode is always lower, the direction of the generated electric field is always one direction. Therefore, the orientation of the liquid crystal is biased, and flicker or liquid crystal burn-in may occur. Therefore, in the liquid crystal device, for example, positive writing in which an image voltage having a higher potential than the common electrode (hereinafter referred to as positive polarity) is written to the pixel electrode, and a lower potential than the common electrode (hereinafter referred to as negative polarity). 1-frame inversion driving method is employed, in which negative-polarity writing, in which an image voltage of an image voltage is written to a pixel electrode, is alternately performed every frame period.

FIG. 7 is a timing chart of an FFS liquid crystal device according to a conventional example.
Here, for example, the FFS liquid crystal device according to the above-described conventional example has 320 rows of scanning lines and 240 columns of data lines. In FIG. 7, PIX (p, q) is the p-th scanning line (p is an integer satisfying 1 ≦ p ≦ 320) among the 320 scanning lines and the q-th data line of 240 columns. This is the voltage of the pixel electrode provided in the pixel provided corresponding to the intersection of the data line in the column (q is an integer satisfying 1 ≦ q ≦ 240). VY (p) is the voltage of the p-th scanning line among the 320 scanning lines. Further, VCOM is a voltage of the common electrode, and is an intermediate voltage between the voltage Vg (+) and the voltage Vg (−). Actually, the voltage VCOM of the common electrode is slightly deviated from an intermediate voltage between the voltage Vg (+) and the voltage Vg (−) due to the influence of the parasitic capacitance of the TFT, but here, The explanation will be made ignoring the influence of the parasitic capacitance and the like.
In FIG. 7, an image signal for displaying the same gradation is supplied to the q-th data line over a plurality of frames. In FIG. 7, the scales of the vertical axes of the pixel electrode voltage PIN (p, q) and the scanning line voltage VY (p) are appropriately changed.

First, in one horizontal scanning period from time t41 to t42, positive writing is performed on pixels provided corresponding to the intersection of the p-th scanning line and the q-th data line.
That is, the voltage VDD is supplied to the p-th scanning line as a selection voltage, all the TFTs related to the p-th scanning line are turned on, and all the pixels related to the p-th scanning line are selected. In synchronization with the selection of these pixels, the voltage Vg (+) is supplied as a positive image signal to the q-th data line. Then, a positive image signal is supplied to the pixel provided corresponding to the intersection of the p-th scanning line and the q-th data line via the on-state TFT, and this positive-polarity image signal is supplied to the positive-polarity image signal. The positive image voltage Vg (+) based thereon is written into the pixel electrode.
As described above, the voltage PIX (p, q) of the pixel electrode included in the pixel provided corresponding to the intersection of the p-th scanning line and the q-th data line is Vg (+).

  Next, at time t <b> 42, the voltage VSS is supplied to the p-th scanning line as a non-selection voltage, all the TFTs related to the p-th scanning line are turned off, and the pixels related to the p-th scanning line are turned on. Deselect all. Then, the voltage PIX (p, q) of the pixel electrode included in the pixel provided corresponding to the intersection of the scanning line in the p-th row and the data line in the q-th column decreases to V5 at time t43. .

Next, during one horizontal scanning period from time t44 to t45, negative polarity writing is performed on pixels provided corresponding to the intersection of the p-th scanning line and the q-th data line.
That is, the voltage VDD is supplied to the p-th scanning line as a selection voltage, all the TFTs related to the p-th scanning line are turned on, and all the pixels related to the p-th scanning line are selected. In synchronism with the selection of these pixels, the voltage Vg (−) is supplied as a negative image signal to the q-th data line. Then, a negative image signal is supplied to the pixel provided corresponding to the intersection of the p-th scanning line and the q-th data line via the on-state TFT. The negative image voltage Vg (−) based thereon is written into the pixel electrode.
As described above, the voltage PIX (p, q) of the pixel electrode included in the pixel provided corresponding to the intersection of the p-th scanning line and the q-th data line is Vg (−).

Next, at time t45, the voltage VSS is supplied as a non-selection voltage to the p-th scanning line, all the TFTs related to the p-th scanning line are turned off, and the pixels related to the p-th scanning line are turned on. Deselect all. Then, the voltage PIX (p, q) of the pixel electrode included in the pixel provided corresponding to the intersection of the scanning line in the pth row and the data line in the qth column rises to V6 at time t46. .
Here, the potential difference between the voltage Vg (−) and the voltage V6 and the potential difference between the voltage Vg (+) and the voltage V5 are so large that they cannot be ignored.

  As described above, in the FFS type liquid crystal device according to the conventional example, the voltage of the pixel electrode that fluctuates is different after positive polarity writing and after negative polarity writing. Therefore, even if an image signal for displaying the same gradation is supplied to the q-th data line over a plurality of frames, the positive polarity writing and the negative polarity writing are performed. However, the potential difference between the pixel electrode constituting the pixel capacitor and the common electrode is different, and flicker and liquid crystal burn-in may occur.

  It is an object of the present invention to provide an FFS liquid crystal device and an electronic apparatus that can suppress the occurrence of flicker and liquid crystal burn-in.

  As a result of intensive studies to achieve the above-described object, the inventors of the present invention have made the voltage difference between the voltage Vg (−) and the voltage V6 and the voltage Vg (+) by increasing the writing time with the same polarity. It has been found that the potential difference between the voltage V5 and the voltage V5 becomes smaller and the difference between the two becomes smaller. That is, when an image voltage based on an image signal having the same polarity is written to a pixel electrode during a plurality of horizontal scanning periods in one frame period, the voltage that decreases after the writing of the image voltage is reduced in the pixel electrode. It came to complete.

  A liquid crystal device according to the present invention includes a first substrate having a plurality of pixel electrodes provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and a second substrate disposed opposite to the first substrate. A liquid crystal device comprising a liquid crystal provided between the first substrate and the second substrate, wherein an insulating film is formed on the first substrate below the pixel electrode, A common electrode is formed under the insulating film, and a scanning line driving circuit for selecting the scanning line by sequentially supplying a selection voltage to the plurality of scanning lines, and the common when the scanning line is selected. A positive image signal that is a potential higher than the potential of the electrode and a negative image signal that is a potential lower than the potential of the common electrode are periodically and alternately supplied to the plurality of data lines, Based on the image signal to the pixel electrode associated with the selected scanning line A data line driving circuit for writing an image voltage, and each pixel electrode has a plurality of horizontal scanning periods in one frame period, and each pixel electrode has an image signal having the same polarity, either positive or negative. An image voltage based on the above is written.

According to the present invention, the pixel electrode, the insulating film under the pixel electrode, and the common electrode under the insulating film are formed on the first substrate of the liquid crystal device. This is a liquid crystal device.
In this FFS type liquid crystal device, an image voltage based on either a positive or negative image signal is written to each pixel electrode for each of a plurality of horizontal scanning periods in one frame period. Therefore, in each pixel electrode, the voltage that decreases after the image voltage is written is small, so that it is common to the pixel electrode that constitutes the pixel capacitance after the positive polarity writing and after the negative polarity writing. It is possible to suppress the occurrence of flicker and liquid crystal image sticking by suppressing the difference in potential from the electrode.

  In the liquid crystal device according to the aspect of the invention, the data line driving circuit alternately supplies the positive-polarity image signal and the negative-polarity image signal to the data line every horizontal scanning period. In addition to the period in which the scanning line is selected for each of the scanning lines, the drive circuit selects the scanning line in the period in which at least one scanning line before a multiple of 2 is selected. It is preferable to supply a voltage.

  According to the present invention, the polarity of the image signal is inverted every horizontal scanning period, and at least one scan before a multiple of 2 in addition to the period in which each scanning line is selected for each scanning line. The selection voltage was also supplied during the period when the line was selected. That is, an image voltage based on either a positive or negative image signal is written in each pixel electrode for each of a plurality of horizontal scanning periods in one frame period. Therefore, in each pixel electrode, the voltage that decreases after the image voltage is written is small, so that it is common to the pixel electrode that constitutes the pixel capacitance after the positive polarity writing and after the negative polarity writing. It is possible to suppress the occurrence of flicker and liquid crystal image sticking by suppressing the difference in potential from the electrode.

  In the liquid crystal device according to the aspect of the invention, the data line driving circuit alternately supplies the positive image signal and the negative image signal to the data line every frame period, thereby driving the scanning line. It is preferable that the circuit supplies the selection voltage to each scanning line over a plurality of continuous horizontal scanning periods.

  According to the present invention, the polarity of the image signal is inverted every frame period, and each scanning line is selected over a plurality of continuous horizontal scanning periods. That is, an image voltage based on either a positive or negative image signal is written into each pixel electrode for each of a plurality of consecutive horizontal scanning periods in one frame period. Therefore, in each pixel electrode, the voltage that decreases after the image voltage is written is small, so that it is common to the pixel electrode that constitutes the pixel capacitance after the positive polarity writing and after the negative polarity writing. It is possible to suppress the occurrence of flicker and liquid crystal image sticking by suppressing the difference in potential from the electrode.

An electronic apparatus according to the present invention includes the above-described liquid crystal device.
According to the present invention, there are effects similar to those described above.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of embodiments and modifications, the same constituent elements are denoted by the same reference numerals, and the description thereof is omitted or simplified.
<First Embodiment>
FIG. 1 is a block diagram of an FFS liquid crystal device according to the first embodiment of the present invention.
The FFS type liquid crystal device 1 includes a liquid crystal panel AA. The liquid crystal panel AA includes a display area A having a plurality of pixels 50, and a scanning line driving circuit 11 and a data line driving circuit 21 that are provided around the display area A and drive the pixels 50.

  The liquid crystal panel AA includes an element substrate 60 (see FIG. 3) as a first substrate, a counter substrate 70 (see FIG. 3) as a second substrate disposed opposite to the element substrate 60, and the element substrate 60 and the counter substrate. 70, and a liquid crystal provided between the two.

  The element substrate 60 includes 320 rows of scanning lines Y1 to Y320 and 240 columns of data lines X1 to X240 provided so as to intersect the scanning lines Y1 to Y320, and each scanning line Y and each data line. Pixels 50 are provided at the intersections of X. A common line 30 is provided substantially parallel to the scanning line Y. In the present embodiment, 320 scanning lines Y and 240 columns of data lines X are provided. However, the present invention is not limited to this.

  The pixel 50 includes a TFT 51, a pixel electrode 55, a common electrode 56 facing the pixel electrode 55, and a storage capacitor 53 having one end connected to the pixel electrode 55 and the other end connected to the common line 30. The pixel electrode 55 and the common electrode 56 constitute a pixel capacitor having a liquid crystal layer as a dielectric. The common electrode 56 is connected to the common line 30.

  The scanning line Y is connected to the gate of the TFT 51, the data line X is connected to the source of the TFT 51, and the pixel electrode 55 and the storage capacitor 53 are connected to the drain of the TFT 51. Therefore, the TFT 51 is turned on when a selection voltage is applied from the scanning line Y, and the data line X, the pixel electrode 55, and the storage capacitor 53 are brought into conduction.

  FIG. 2 is an enlarged plan view of the pixel 50 constituting the FFS type liquid crystal device 1. FIG. 3 is a cross-sectional view of the pixel 50 of the FFS liquid crystal device 1 taken along the line AA.

  As shown in FIG. 3, the liquid crystal panel AA is provided between an element substrate 60 having a plurality of pixel electrodes 55, a counter substrate 70 disposed opposite to the element substrate 60, and the element substrate 60 and the counter substrate 70. Liquid crystal.

As shown in FIG. 2, in the element substrate 60, each pixel 50 is surrounded by a common line 30 made of two adjacent transparent conductive materials and a data line X made of two adjacent conductive materials. It has become an area. That is, each pixel 50 is partitioned by the common line 30 and the data line X.
In the present embodiment, the TFT 51 is an inverted stagger type amorphous silicon TFT, and a region 50C where the TFT 51 is formed (surrounded by a broken line in FIG. 2) near the intersection of the scanning line Y and the data line X. Part) is provided.

First, the element substrate 60 will be described.
The element substrate 60 has a glass substrate 68, and on the glass substrate 68, in order to prevent changes in the characteristics of the TFT 51 due to surface roughness or contamination of the glass substrate 68, a base insulating film (illustrated) is formed over the entire surface. (Omitted) is formed.

A scanning line Y made of a conductive material is formed on the base insulating film.
The scanning line Y is provided along the boundary between adjacent pixels 50, and constitutes the gate electrode 511 of the TFT 51 in the vicinity of the intersection with the data line X.

  A gate insulating film 62 is formed over the entire surface of the pixel 50 on the scanning line Y, the gate electrode 511, and the base insulating film.

  In the region 50C where the TFT 51 is formed on the gate insulating film 62, a semiconductor layer (not shown) made of amorphous silicon and an ohmic contact layer (not shown) made of N + amorphous silicon are stacked facing the gate electrode 511. Has been. A source electrode 512 and a drain electrode 513 are stacked on the ohmic contact layer, thereby forming an amorphous silicon TFT.

The source electrode 512 is formed of the same conductive material as the data line X. That is, the source electrode 512 extends from the data line X. The data line X is provided so as to intersect the scanning line Y and the common line 30.
As described above, the gate insulating film 62 is formed on the scanning line Y, and the data line X is formed on the gate insulating film 62. For this reason, the data line X is insulated from the scanning line Y by the gate insulating film 62.

  A first insulating film 63 is formed over the entire surface of the pixel 50 on the data line X, the source electrode 512, the drain electrode 513, and the gate insulating film 62.

A common line 30 made of a conductive material is formed on the first insulating film 63.
The common line 30 is provided along the scanning line Y, and a common electrode 56 extends from the common line 30.

  A second insulating film 64 is formed on the common line 30, the common electrode 56, and the first insulating film 63 over the entire surface of the pixel 50.

A pixel electrode 55 made of a transparent conductive material such as ITO (Indium Tin Oxide) is formed on the second insulating film 64 in a region facing the common electrode 56. The pixel electrode 55 is connected to the drain electrode 513 through a contact hole (not shown) formed in the first insulating film 63 and the second insulating film 64 described above.
In the pixel electrode 55, a plurality of slits 55A for generating a fringe field (electric field E) are provided at predetermined intervals between the pixel electrode 55 and the common electrode 56. That is, the liquid crystal of the liquid crystal device 1 operates in the FFS mode.

  On the pixel electrode 55 and the second insulating film 64, an alignment film (not shown) made of an organic film such as a polyimide film is formed. The above structure is not intended to limit the liquid crystal panel structure operating in the FFS mode. For example, the second insulating film 64 is formed on the common electrode 56, and the pixel is formed on the second insulating film 64. The structure in which the electrode 55 is formed may be sufficient.

Next, the counter substrate 70 will be described.
The counter substrate 70 has a glass substrate 74, and a light shielding film 71 as a black matrix is formed on the glass substrate 74 at a position facing the scanning line Y and the common line 30. A color filter 72 is formed in a region on the glass substrate 74 excluding the region where the light shielding film 71 is formed.

  An alignment film (not shown) is formed on the black matrix 71 and the color filter 72.

  Returning to FIG. 1, the scanning line driving circuit 11 supplies a selection voltage for turning on the TFT 51 to each scanning line Y in a predetermined order. For example, when a selection voltage is supplied to a certain scanning line Y, all the TFTs 51 connected to the scanning line Y are turned on, and all the pixels 50 related to the scanning line Y are selected.

  The data line driving circuit 21 supplies an image signal to each data line X, and writes the image voltage based on the image signal to the pixel electrode 55 through the TFT 51 in the ON state.

The above FFS type liquid crystal device 1 operates as follows.
That is, by sequentially supplying a selection voltage from the scanning line driving circuit 11 to the scanning lines Y1 to Y320 in 320 rows, all the TFTs 51 related to the scanning lines Y are sequentially turned on, and all the scanning lines Y are related to each other. Pixels 50 are selected sequentially. In synchronization with the selection of the pixels 50, an image signal is supplied from the data line driving circuit 21 to the data line X. Then, an image signal is supplied to all the pixels 50 selected by the scanning line driving circuit 11 from the data line driving circuit 21 via the data line X and the on-state TFT 51, and an image voltage based on this image signal is applied to the pixel electrode. 55 is written.

  When an image voltage is written to the pixel electrode 55, a potential difference is generated between the pixel electrode 55 and the common electrode 56, and a substantially horizontal electric field E is generated on the element substrate 60 due to the potential difference. The electric field E changes the alignment of the liquid crystal, and the light transmitted through the liquid crystal changes, so that gradation display is performed.

  FIG. 4 is a timing chart of the FFS mode liquid crystal device 1.

  Here, the scanning line driving circuit 11 supplies a selection voltage to each scanning line Y twice in one frame period.

The data line driving circuit 21 inverts the polarity of the image signal supplied to the data line X every horizontal scanning period with reference to the voltage of the common electrode 56. Specifically, for example, when an odd row is selected, a positive image signal is supplied to the data line X, and when an even row is selected, a negative image signal is supplied to the data line X. In the next frame, the polarities of the image signals are reversed and supplied to the data line X.
In FIG. 4, an image signal for displaying the same gradation is supplied to the data line X over a plurality of frames.

  In FIG. 4, PIX (i, j) is the i-th scanning line Yi (i is an integer satisfying 1 ≦ i ≦ 320) among the 320 scanning lines Y1 to Y320 and 240 columns of data. This is the voltage of the pixel electrode 55 provided in the pixel 50 provided corresponding to the intersection with the data line Xj of the j-th column (j is an integer satisfying 1 ≦ j ≦ 240) among the lines X1 to X240. VY (i) is the voltage of the scanning line Yi. VCOM is a voltage of the common electrode 56 and is an intermediate voltage between the voltage Vg (+) and the voltage Vg (−).

  First, the voltage PIX (i, j) of the pixel electrode 55 provided in the pixel 50 provided corresponding to the intersection of the i-th scanning line Yi and the j-th data line Xj will be described.

First, in one frame period, it corresponds to the intersection of the scanning line Yi and the data line Xj twice, one horizontal scanning period from time t1 to t2 and one horizontal scanning period from time t3 to t4. Thus, positive polarity writing is performed on the pixel 50 provided.
That is, in one horizontal scanning period from time t1 to time t2 and one horizontal scanning period from time t3 to time t4, the voltage VDD is supplied as the selection voltage to the scanning line Yi, and all the TFTs 51 related to the scanning line Yi are turned on. All the pixels 50 related to the scanning line Yi are selected. In addition, in synchronization with the selection of the pixels 50 related to the scanning lines Yi, the voltage Vg (+) is supplied to the data lines Xj as positive image signals. Then, a positive image signal is supplied to the pixel 50 provided corresponding to the intersection of the scanning line Yi and the data line Xj via the on-state TFT 51, and a positive image based on this positive image signal is supplied. The voltage Vg (+) is written to the pixel electrode 55.
As described above, writing is performed for a total of two horizontal scanning periods including one horizontal scanning period from time t1 to time t2 and one horizontal scanning period from time t3 to time t4.
Note that one horizontal scanning period from time t1 to time t2 is at least one scanning line before the i-th scanning line Yi by a multiple of 2 (i-2) -th scanning line Y (i-2). ) Is a selected period.

  After time t4, the TFT 51 is turned off, so that the voltage PIX (i, j) of the pixel electrode 55 gradually decreases and reaches, for example, V1 and settles.

Next, two horizontal scan periods from time t9 to t10 and one horizontal scan period from time t11 to t12 are provided corresponding to the intersection of the scan line Yi and the data line Xj. Negative polarity writing is performed on the pixel 50.
That is, in one horizontal scanning period from time t9 to t10 and one horizontal scanning period from time t11 to t12, the voltage VDD is supplied as the selection voltage to the scanning line Yi, and all the TFTs 51 related to the scanning line Yi are turned on. All the pixels 50 related to the scanning line Yi are selected. Further, in synchronization with the selection of the pixels 50 related to these scanning lines Yi, the voltage Vg (−) is supplied to the data lines Xj as negative image signals. Then, a negative image signal is supplied to the pixel 50 provided corresponding to the intersection of the scanning line Yi and the data line Xj via the on-state TFT 51, and a negative image based on the negative image signal is supplied. The voltage Vg (−) is written into the pixel electrode 55.
As described above, writing is performed for a total of two horizontal scanning periods including one horizontal scanning period from time t9 to t10 and one horizontal scanning period from time t11 to t12.
Note that one horizontal scanning period from time t9 to time t10 is at least one scanning line before the i-th scanning line Yi by a multiple of 2 (i-2) -th scanning line Y (i-2). ) Is a selected period.

  After time t12, the TFT 51 is turned off, so that the voltage PIX (i, j) of the pixel electrode 55 gradually increases, for example, reaches V2 and settles.

Further, in the pixel 50 provided corresponding to the intersection of the scanning line Y (i + 1) in the (i + 1) th row and the data line Xj in the jth column, the above-mentioned ith scanning line Yi and the jth column. The operation is similar to that of the pixel 50 provided corresponding to the intersection with the data line Xj.
That is, negative writing is performed in a total of two horizontal scanning periods including one horizontal scanning period from time t2 to t3 and one horizontal scanning period from time t4 to t5. Further, positive writing is performed in a total of two horizontal scanning periods of one horizontal scanning period from time t10 to t11 and one horizontal scanning period from time t12 to t13.
Note that one horizontal scanning period from time t2 to time t3 and one horizontal scanning period from time t10 to time t11 are at least one scan before a multiple of 2 of the (i + 1) th scanning line Y (i + 1). This is a period during which the scanning line Y (i-1) in the (i-1) th row, which is a line, is selected.

Further, in the pixel 50 provided corresponding to the intersection of the scanning line Y (i + 2) in the (i + 2) th row and the data line Xj in the jth column, the i-th scanning line Yi and the jth column are described above. The operation is similar to that of the pixel 50 provided corresponding to the intersection with the data line Xj.
That is, positive writing is performed in a total of two horizontal scanning periods, one horizontal scanning period from time t3 to t4 and one horizontal scanning period from time t5 to t6. Further, negative writing is performed in a total of two horizontal scanning periods including one horizontal scanning period from time t11 to t12 and one horizontal scanning period from time t13 to t14.
Note that one horizontal scanning period from time t3 to t4 and one horizontal scanning period from time t11 to t12 are at least one scan before the (i + 2) th scanning line Y (i + 2) multiples of two. This is a period during which the i-th scanning line Yi is selected.

Further, in the pixel 50 provided corresponding to the intersection of the scanning line Y (i + 3) in the (i + 3) th row and the data line Xj in the jth column, the above-mentioned ith scanning line Yi and the jth column. The operation is similar to that of the pixel 50 provided corresponding to the intersection with the data line Xj.
That is, negative writing is performed in a total of two horizontal scanning periods, one horizontal scanning period from time t4 to t5 and one horizontal scanning period from time t6 to t7. In addition, positive writing is performed in a total of two horizontal scanning periods including one horizontal scanning period from time t12 to time t13 and one horizontal scanning period from time t14 to time t15.
Note that one horizontal scanning period from time t4 to time t5 and one horizontal scanning period from time t12 to time t13 are at least one scan before a multiple of 2 of the scanning line Y (i + 3) of the (i + 3) th row. This is a period during which the scanning line Y (i + 1) in the (i + 1) th row is selected.

As described above, for the pixel electrodes 55 in each row, the writing period is set to two horizontal scanning periods in the positive polarity writing and the negative polarity writing. For this reason, as described above, the voltage fluctuation during positive polarity writing (Vg (+) − V1) and the voltage fluctuation during negative polarity writing (V2−Vg (−)) are written respectively. The period becomes smaller than in the case of one horizontal scanning period, and the difference between them, that is, the residual DC component of the pixel voltage becomes smaller. Therefore, occurrence of flicker and liquid crystal image sticking can be suppressed.
In the present embodiment, in the positive polarity writing and the negative polarity writing, the writing periods are each set to two horizontal scanning periods. By making the writing period longer, the residual DC component becomes smaller. However, if the writing period is excessively long, the optical response of the liquid crystal can be felt with the eyes. Therefore, the writing period is appropriately set in consideration of the response speed of the liquid crystal.

Second Embodiment
FIG. 5 is a timing chart of the FFS mode liquid crystal device 1 according to the second embodiment of the present invention.

  Here, the scanning line driving circuit 11 supplies a selection voltage to each scanning line Y over four horizontal scanning periods that are continuous in one frame period.

Further, the data line driving circuit 21 inverts the polarity of the image signal supplied to the data line X every frame period with the voltage of the common electrode 56 as a reference. Specifically, for example, a positive image signal is supplied to the data line X in one frame period, and a negative image signal is supplied to the data line X in the next one frame period.
In FIG. 5, an image signal for displaying the same gradation is supplied to the data line X over a plurality of frames.

  In FIG. 5, PIX (m, n) is the m-th scanning line Ym of 320 scanning lines Y1 to Y320 (m is an integer satisfying 1 ≦ m ≦ 320) and 240 columns of data. This is the voltage of the pixel electrode 55 provided in the pixel 50 provided corresponding to the intersection with the data line Xn of the nth column (n is an integer satisfying 1 ≦ n ≦ 240) among the lines X1 to X240. VY (m) is the voltage of the scanning line Ym. VCOM is a voltage of the common electrode 56 and is an intermediate voltage between the voltage Vg (+) and the voltage Vg (−).

  First, the voltage PIX (m, n) of the pixel electrode 55 provided in the pixel 50 provided corresponding to the intersection of the m-th scanning line Ym and the n-th data line Xn will be described.

First, in one frame period, positive writing is performed on the pixel 50 provided corresponding to the intersection of the scanning line Ym and the data line Xn in the four horizontal scanning periods from time t21 to t23.
That is, in the four horizontal scanning periods from time t21 to t23, the voltage VDD is supplied to the scanning line Ym as the selection voltage, all the TFTs 51 related to the scanning line Ym are turned on, and all the pixels 50 related to the scanning line Ym are selected. To do. In addition, a positive image signal is supplied to the data line Xn in synchronization with the selection of the pixel 50 related to the scanning line Ym. Then, a positive image signal is supplied to the pixel 50 provided corresponding to the intersection of the scanning line Ym and the data line Xn via the on-state TFT 51, and a positive image based on this positive image signal is supplied. The voltage Vg (+) is written to the pixel electrode 55.
As described above, positive writing is performed over four horizontal scanning periods from time t21 to t23.

  Then, after time t23, the TFT 51 is turned off, so the voltage PIX (m, n) of the pixel electrode 55 gradually decreases, for example, reaches V3 and settles.

Next, negative writing is performed on the pixels 50 provided corresponding to the intersections of the scanning lines Ym and the data lines Xn during four horizontal scanning periods from time t26 to t28.
That is, in the four horizontal scanning periods from time t26 to t28, the voltage VDD is supplied as the selection voltage to the scanning line Ym, all the TFTs 51 related to the scanning line Ym are turned on, and all the pixels 50 related to the scanning line Ym are selected. To do. Further, in synchronization with the selection of the pixels 50 related to these scanning lines Ym, a negative image signal is supplied to the data lines Xn. Then, a negative-polarity image signal is supplied to the pixel 50 provided corresponding to the intersection of the scanning line Ym and the data line Xn via the on-state TFT 51, and a negative-polarity image based on this negative-polarity image signal. The voltage Vg (−) is written into the pixel electrode 55.
As described above, the negative polarity writing is performed over the four horizontal scanning periods from the time t26 to the time t28.

  Then, after time t28, the TFT 51 is turned off, so that the voltage PIX (m, n) of the pixel electrode 55 gradually increases, for example, reaches V4 and settles.

  Further, regarding the voltage PIX (i + 1, j) of the pixel electrode 55 provided in the pixel 50 provided corresponding to the intersection of the scanning line Y (m + 1) in the (m + 1) th row and the data line Xn in the nth column, Compared to the voltage PIX (m, n) of the pixel electrode 55 described above, the operation is delayed by one horizontal scanning period. Therefore, the description is omitted.

As described above, regarding the pixel electrodes 55 in each row, the writing period is set to 4 horizontal scanning periods in the positive polarity writing and the negative polarity writing. For this reason, as described above, the voltage fluctuation during positive polarity writing (Vg (+) − V3) and the voltage fluctuation during negative polarity writing (V4−Vg (−)) are written respectively. The period becomes smaller than in the case of one horizontal scanning period, and the difference between them, that is, the residual DC component of the pixel voltage becomes smaller. Therefore, occurrence of flicker and liquid crystal image sticking can be suppressed.
In the present embodiment, in the positive polarity writing and the negative polarity writing, the writing period is set to 4 horizontal scanning periods. However, the writing period is not limited to this, and may be set to 10 horizontal scanning periods, for example. By making the writing period longer, the residual DC component becomes smaller. However, if the writing period is made too long, the optical response of the liquid crystal can be felt with the eyes, so the writing period is set appropriately in consideration of the response speed of the liquid crystal and the like.

<Modification>
Note that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within a scope in which the object of the present invention can be achieved are included in the present invention.
For example, in each of the embodiments described above, the TFT 51 is configured by an amorphous silicon TFT, but is not limited thereto, and may be configured by, for example, a high temperature or low temperature polysilicon TFT. Further, it may be a non-linear resistance element.

<Application example>
Next, an electronic apparatus to which the FFS mode liquid crystal device 1 according to the above-described embodiment is applied will be described.
FIG. 6 is a perspective view illustrating a configuration of a mobile phone to which the FFS liquid crystal device 1 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the FFS liquid crystal device 1. By operating the scroll button 3002, the screen displayed on the FFS liquid crystal device 1 is scrolled.

  Note that electronic devices to which the FFS liquid crystal device 1 is applied include, in addition to those shown in FIG. 6, a personal computer, a portable information terminal, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, Examples include car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices equipped with touch panels. And the liquid crystal device mentioned above is applicable as a display part of these various electronic devices.

1 is a block diagram of an FFS liquid crystal device according to a first embodiment of the present invention. FIG. 3 is an enlarged plan view of pixels that constitute the liquid crystal device. It is sectional drawing of the pixel of the said liquid crystal device. 3 is a timing chart of the liquid crystal device. 6 is a timing chart of the FFS mode liquid crystal device according to the second embodiment of the present invention. It is a perspective view showing a configuration of a mobile phone to which the above-described FFS mode liquid crystal device is applied. It is a timing chart of the liquid crystal device of the FFS system which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 11 ... Scanning line drive circuit, 21 ... Data line drive circuit, 30 ... Common line, 50 ... Pixel, 51 ... TFT, 55 ... Pixel electrode, 56 ... Common electrode, 60 ... Element substrate (first substrate) , 64 ... 2nd insulating film (insulating film), 70 ... Counter substrate (second substrate), 3000 ... Mobile phone (electronic device), X ... Data line, Y ... Scanning line.

Claims (4)

A first substrate having a plurality of pixel electrodes provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines; a second substrate disposed opposite to the first substrate; the first substrate; A liquid crystal device provided with a liquid crystal provided between the second substrate,
In the first substrate, an insulating film is formed under the pixel electrode, and a common electrode is formed under the insulating film.
A scanning line driving circuit for selecting the scanning lines by sequentially supplying a selection voltage to the plurality of scanning lines;
When the scanning line is selected, a positive polarity image signal that is higher than the potential of the common electrode and a negative polarity image signal that is lower than the potential of the common electrode are periodically generated. A data line driving circuit that alternately supplies the plurality of data lines and writes an image voltage based on the image signal to the pixel electrode associated with the selected scanning line, and
An image voltage based on an image signal having the same polarity of positive polarity or negative polarity is written to each pixel electrode in each pixel electrode for each of a plurality of horizontal scanning periods in one frame period. . The liquid crystal device according to claim 1,
The data line drive circuit alternately supplies the positive image signal and the negative image signal to the data line every horizontal scanning period,
The scanning line driving circuit includes:
For each of the scanning lines, in addition to a period in which the scanning line is selected, the selection voltage is supplied to the scanning line also in a period in which at least one scanning line before a multiple of 2 is selected. A liquid crystal device characterized by that. The liquid crystal device according to claim 1,
The data line driving circuit alternately supplies the positive image signal and the negative image signal to the data line every frame period,
The liquid crystal device, wherein the scanning line driving circuit supplies the selection voltage to each scanning line over a plurality of continuous horizontal scanning periods. An electronic apparatus comprising the liquid crystal device according to claim 1.

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