JP2007325072A - Synchronization device and synchronization method - Google Patents

Abstract

A synchronization device and a synchronization method capable of highly accurate synchronization are provided.
A first PLL means 200 that synchronizes with a first synchronization signal (specific signal) and a second PLL means 300 that synchronizes with a second synchronization signal (20 Hz synchronization signal). In the slave station side PLL circuit 150 synchronized with the two synchronization signals, the second PLL means 300 establishes synchronization using the output signal of the first PLL means 200 as the synchronization quantization unit of the second PLL means 300. Thus, it is configured to establish synchronization with two different synchronization signals.
[Selection] Figure 40

Description

  The present invention relates to a synchronization device and a synchronization method for synchronizing a high-precision clock signal in a transmission device that transmits data.

  When speeding up data transmission, high-accuracy clock synchronization between transmission apparatuses that perform data transmission is an indispensable technique. When a multi-mode / multiple modems coexist on the same transmission medium (for example, a power line), such as a power line carrier modem, it is possible to synchronize with the frequency of power flowing through the power line (that is, power supply frequency). At the same time, it is desirable to synchronize to the high precision clock signal of the master modem. In the conventional transmission apparatus, macro synchronization is mainly performed only for the power supply frequency, and microscopically, a high-speed pull-in is performed instantaneously by transmitting and receiving a training signal.

Japanese Patent No. 3747415 Japanese Patent Laid-Open No. 05-207001 JP 05-260100 A JP 05-260109 A Japanese Patent Laid-Open No. 08-116347 Japanese Patent Laid-Open No. 10-224271

  However, in such a conventional method, since the pull-in depends on short-time information such as a training signal, there is a problem that synchronization accuracy is low and high-accuracy high-speed transmission cannot be performed.

  The present invention has been made in view of such a problem, and an object thereof is to provide a synchronization device and a synchronization method capable of highly accurate synchronization.

  In order to solve the above-described problem, the synchronization device according to the first aspect of the present invention (for example, the slave station side PLL circuit 150 in the embodiment) includes a first PLL means synchronized with a first synchronization signal, a second PLL A second PLL means that synchronizes with the synchronizing signal, and synchronizes with these two synchronizing signals. The second PLL means outputs the output signal of the first PLL means to the second PLL means. By establishing synchronization as a synchronization quantization unit, it is configured to establish synchronization with two different synchronization signals.

  A synchronization device according to a second aspect of the present invention is provided in a transmission device connected to a transmission medium for communication, and performs synchronization of a high-accuracy clock signal between these transmission devices. High-accuracy clock oscillation means (for example, high-accuracy clock oscillation circuit 39 in the embodiment) and a first synchronization signal (for example, 62.5 kHz Nyquist clock in the embodiment) by dividing the high-accuracy clock signal The first frequency dividing means for outputting (for example, the first frequency dividing circuit 40 in the embodiment) and the timing phase for receiving the specific signal transmitted from the predetermined transmission device and extracting the timing phase of the specific signal Extraction means (for example, the specific signal timing phase extraction circuit 151 and the specific signal detection circuit 152 in the embodiment), the timing phase and the first The first PLL means (for example, the phase advance in the embodiment) for comparing the signal and determining the phase advance / delay and controlling the high-precision clock oscillating means to synchronize the first synchronization signal with a predetermined transmission device. The delay determination circuit 153, the first integration circuit 154, and the second integration circuit 155) and the frequency of the signal flowing through the transmission medium are detected, and the second synchronization signal (for example, the 20 Hz synchronization signal in the embodiment) is output. A synchronization signal detection means (for example, a 20 Hz synchronization signal detection circuit 120 in the embodiment) and a first estimated synchronization signal (for example, an estimated 20 Hz synchronization signal in the embodiment) are output by dividing the first synchronization signal. The second frequency dividing means (for example, the second frequency dividing circuit 134 in the embodiment), the second synchronizing signal and the second estimated synchronizing signal are compared to determine the phase advance and delay, and the second The second PLL means (for example, the phase advance / delay determination circuit 131 in the embodiment, the first PLL circuit for outputting the synchronized second estimated synchronization signal with the first synchronization signal as a quantization unit by controlling the circumference means. 1 integrating circuit 132 and second integrating circuit 133).

  In such a synchronization apparatus according to the second aspect of the present invention, time slot selection means for selecting a time slot selected by a predetermined transmission apparatus by the second estimated synchronization signal (for example, a slave station side time slot selection circuit in the embodiment) 160), and the first PLL means is preferably configured to control the high precision clock oscillating means using the timing phase of the specific signal in the time slot selected by the time slot selecting means.

  In the synchronization device according to the second aspect of the present invention, it is preferable that the transmission medium is a power line, and the time phase of the signal flowing through the transmission medium is synchronized with the power supply frequency.

  At this time, the synchronization signal detecting means has zero cross point detecting means (for example, zero cross point detecting and time window generating circuit 121 in the embodiment) for detecting a point at which the voltage value flowing through the power line becomes zero. It is preferable that the second synchronization signal is generated by counting points where the voltage value detected by the means becomes zero.

  In addition, the synchronization signal detection means counts the points where the voltage value detected by the zero cross point detection means becomes zero, and sets a time window (for example, zero cross point detection and time window generation in the embodiment) Circuit 121), and is preferably configured to detect a specific signal transmitted from a predetermined transmission device and generate a second synchronization signal in the time window set by the time window setting means. .

  Note that in the synchronization device according to the second aspect of the present invention, it is preferable that the transmission device is configured to perform communication using a time division multiple access method.

  On the other hand, the synchronization method according to the first aspect of the present invention includes a first PLL means that synchronizes with the first synchronization signal and a second PLL means that synchronizes with the second synchronization signal. The second PLL means synchronizes with two different synchronization signals by establishing synchronization using the output signal of the first PLL means as a synchronous quantization unit of the second PLL means. Configured to establish.

  A synchronization method according to the second aspect of the present invention is a method for synchronizing a high-accuracy clock signal in a transmission method connected to a transmission medium for communication, and the transmission method divides the high-accuracy clock signal. Detecting a timing phase from a specific signal transmitted by a predetermined transmission method, and a second synchronization signal generated from a frequency of a signal flowing through the transmission medium, By controlling the high-accuracy clock oscillating means for outputting the high-accuracy clock signal from this timing phase, the first synchronization signal is synchronized with the specific signal, and the first synchronization signal is divided to obtain the second estimated synchronization. A signal is generated, and the second synchronization signal is synchronized with the second synchronization signal using the first synchronization signal as a quantization unit.

  In such a synchronization method according to the second aspect of the present invention, a time slot is selected by the second estimated synchronization signal, and the first synchronization signal is transmitted to a predetermined transmission device using the timing phase of the specific signal in the time slot. It is preferably configured to synchronize.

  In the synchronization method according to the second aspect of the present invention, it is preferable that the transmission medium is a power line, and the time phase of the signal flowing through the transmission medium is synchronized with the power supply frequency.

  At this time, it is preferable that the second synchronization signal is generated so as to be generated by counting points where the voltage value of the power flowing through the power line becomes zero.

  Alternatively, the second synchronization signal counts the point where the voltage value of the power flowing through the power line becomes zero, sets a time window, and detects a specific signal transmitted from a predetermined transmission device in this time window. It is preferably configured to be generated.

  In the synchronization method according to the second aspect of the present invention, it is preferable that the transmission apparatus is configured to perform communication using a time division multiple access method.

  When the synchronization device and the synchronization method according to the present invention are configured as described above, a high-accuracy clock signal oscillated from the same high-accuracy clock oscillation means is used to synchronize with a predetermined transmission device and a signal flowing through a transmission medium. Can do. Therefore, even if multiple systems / multiple modems coexist in the same transmission medium, they can be distinguished by a synchronization signal synchronized with a signal flowing through the transmission medium, and highly accurate in communication between transmission apparatuses. Since synchronization can be performed, high-precision and high-speed transmission is possible.

  In addition, by selecting the time slot by the second estimated synchronization signal, it is possible to accurately determine the time slot when the time division multiple access method is used, and to perform highly accurate transmission.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. First, the configuration of the multiplex transmission apparatus according to the present invention will be described with reference to FIG. This multiplex transmission apparatus shows a case of a modem configuration having both a transmission side multiplexing processing unit and a receiving side demultiplexing processing unit when applied to a power line carrier system. 2, power supply unit 3, transmission driver circuit (DV) 4, transformer 5 for transmitting / receiving signals to / from power lines, common mode choke (CMC) 6, 10BASE-T, 100BASE-TX, etc. for suppressing leakage electric field A connection portion 7 with a LAN (indoor local area network) and an RJ connector (RJ45) 8 are included.

  The digital unit 1 is a PLC media access control unit (PLC-MAC) 11 that performs transmission and reception data transmission and reception at the connection unit 7 and performs time division control, a multiplexing processing unit 12 that multiplexes and transmits transmission data, and It comprises a demultiplexing processing unit 13 that separates received signals into received data. Here, the multiplexing processing unit 12 includes a scrambler and summing circuit (SCR & summing) 14, a signal point generating unit 15 as a signal point generating unit, and an inverse fast Fourier transform unit that constitutes a main part of the multiplexing unit. (IFFT) 16, modulator (MOD) 17, and D / A converter (D / A) 18, and demultiplexing processor 13 includes A / D converter (A / D) 19, demodulator (DEM) 20, fast Fourier transform unit (FFT) 21, timing synchronization unit (TIM extraction & PLL) 22, signal point determination unit 23 as means for determining signal points, and difference and descrambling circuit 25 . In the digital unit 1, the PLC media access control unit 11 is controlled by a controller (CPU) 26. It is also possible to realize the function of each part of the digital part 1 by the arithmetic processing function of the processor.

  The analog unit 2 includes a first low-pass filter (LPF1) 31, a high-pass filter and gain switch unit (HPF & GSW) 32, a second low-pass filter (LPF2) 33, and a digital control crystal oscillator (DCXO) 34 (voltage control crystal). It can also be an oscillator). The connection unit 7 includes an Ethernet (registered trademark) processing unit (Ether PHY) 27 that processes a signal (LAN data) input / output via the RJ connector 8, a filtering process, a fragment process, a retransmission process, and an encryption process. And a PLC switch unit (PLC-SW) 28 that performs switching processing and the like.

  In such a multiplex transmission apparatus, the LAN data input to the connection unit 7 from the 10BASE-T or 100BASE-TX side via the RJ connector 8 is transmitted to the PLC switch unit via the Ethernet (registered trademark) processing unit 27. 28. The data taken in by the PLC switch unit 28 obtains functions such as filtering / framing / fragment / buffering / switching and is passed to the PLC media access control unit 11. The PLC media access control unit 11 performs time-sharing processing or the like based on an instruction from the controller 26, transfers control information (conversation between the master station and the slave station) from the controller 26, and manages time slot management of user data. To implement. The transmission data output from the PLC media access control unit 11 is input to the scrambler and summing circuit 14, the data is randomized, and stabilization of the transmission spectrum / stabilization of the leakage electric field is realized. At the same time, phase summing is performed to withstand line fluctuations. After this randomization and phase sum processing, transmission signal points of a plurality of channels are generated by the signal point generator 15 as signal point generating means. The signal point generator 15 can be configured by a ROM or the like, and can be configured to perform notch generation, spectrum spreading, and zero point insertion for noise cancellation.

  The information on the frequency axis, which is a transmission signal point of a plurality of channels, is converted into information on the time axis by the inverse fast Fourier transform unit 16, input to the modulation unit 17, waveform-shaped, and then modulated. Here, the modulation unit 17 is configured to multiplex the signal points at the Nyquist time interval on the time axis and at the Nyquist frequency interval on the frequency axis. After the modulation signal from the modulation unit 17 is input to the D / A converter 18 and converted into an analog signal, an unnecessary band on the analog signal is removed by the first low-pass filter 31 of the analog unit 2. The signal is amplified by the transmission driver circuit 4 and transmitted to the power line, for example, the AC 100V indoor distribution line side or the indoor light line side via the transformer 5 and the common mode choke 6. As described above, the multiplexing process in the multiplex transmission apparatus according to the present embodiment performs the Nyquist time interval on the time axis and a plurality of carrier frequencies at the Nyquist frequency interval on the frequency axis. Multiplexed data transmission is performed.

  On the other hand, the demultiplexing process on the reception side is the reverse of the multiplexing process on the transmission side, and the received signal input via the common mode choke 6 and the transformer 5 is a high-pass filter and a gain switch unit. After the unnecessary low-frequency components are removed by 32, the received signal is amplified to a predetermined level, and the high-frequency unnecessary band components are removed by the second low-pass filter 33. Then, it is converted into a digital signal by the A / D converter 19 of the digital unit 1.

  The received signal converted into a digital signal by the A / D converter 19 of the digital unit 1 is demodulated by the demodulating unit 20 and converted into a baseband signal, and then unnecessary bands are removed. The axis information is converted into frequency axis information. Then, after the received signal point is determined by the signal point determination unit 23 and the phase difference is obtained by the difference and descrambling circuit 25, the randomized state is returned to the original state and the transmission data is reproduced. Further, after passing through the PLC media access control unit 11, it is transferred to a terminal (not shown) through the connection unit 7.

  The phase difference processing described above is configured to be performed after determination by the signal point determination unit 23, but may be configured to perform phase difference processing before signal point determination. In synchronous modems, it is necessary to synchronize the reception clock with the transmission clock. This synchronization signal transmits a reference signal for timing at a plurality of specific frequencies on the transmission side, and this synchronization signal is extracted on the reception side. By doing so, synchronization with transmission is established. The synchronization signal may be extracted at a passband, a baseband, or after fast Fourier transform (FFT), but synchronization can be performed by extracting a signal from a place where efficient processing can be performed. In FIG. 1, extraction from the output signal of the fast Fourier transform unit 21 is possible. Then, the timing synchronization unit 22 can control the digitally controlled crystal oscillator 34 to establish a desired synchronization.

  The power supply unit 3 includes a power supply output unit 41 that supplies an operating voltage of, for example, a DC voltage of 5 V to each unit, and a power supply filter 42. The power supply output unit 41 forms a DC voltage such as DC5V from an AC voltage of AC100V by a switching power supply configuration or the like. However, when the switching power supply configuration is used, switching noise is generated. Noise is not leaked to the common mode choke 6 side and the modem side. Further, the power supply unit 3 needs to minimize the common mode current from the power supply unit 3 so that an unnecessary leakage electric field is not generated on the line side. Furthermore, by connecting this power supply unit 3 to the line, an LCL (ground-to-ground balance) in the transmission band or the like can be prevented so as not to deteriorate the ground-to-ground balance, or to prevent a small signal from being lost due to low impedance. It is necessary to set the normal mode impedance to a desired value or more.

  FIG. 2 is an explanatory diagram of the main part of the multiplexing processing unit 12 and the demultiplexing processing unit 13 of the multiplex transmission apparatus, that is, the main part of the digital unit 1 of the multiplex transmission apparatus shown in FIG. 1 is a transmission signal point generation circuit corresponding to the signal point generation unit 15 in FIG. 1, 52 is a transmission IFFT unit corresponding to the inverse fast Fourier transform unit 16 in FIG. 1, and constitutes a means for multiplexing, and 53 is a signal point determination unit in FIG. Reference numeral 54 denotes a received signal point determination circuit, and 54 denotes a reception FFT unit corresponding to the fast Fourier transform unit 21 in FIG. 55 is a real part inverse fast Fourier transform unit (Real-part IFFT), 56 is an imaginary part inverse fast Fourier transform unit (Imag-part IFFT), 57 is a time axis window function multiplication unit, and 58 is a time axis window function multiplication. Unit (1/2 delay), 59 is a waveform synthesis and convolution integration circuit, 60 is a window function multiplication and convolution integration circuit, 61 is a fast Fourier transform unit (FFT), and 62 is a signal extraction and synthesis circuit of a real part and an imaginary part. Indicates.

  The transmission data is input to the transmission signal point generating circuit 51 to be used as a transmission signal point as a vector signal, and is divided into a real part (Real) and an imaginary part (Imag) of the signal point. The imaginary part is input to the Fourier transform unit 55, and the imaginary part is input to the imaginary part inverse fast Fourier transform unit 56, and is subjected to inverse fast Fourier transform, and is input to the time axis window function multiplication units 57 and 58. Time axis window function multipliers 57 and 58 include means for multiplying a signal on the time axis by the time response waveform of the transmission Nyquist filter as a window function. Note that the window function of the time axis window function multiplier (1/2 delay) 58 is ½ Nyquist time length behind the window function of the time axis window function multiplier 57, and the imaginary value obtained by multiplying this window function is used. The part side signal is time-shifted from the real part side signal by a ½ Nyquist time length. Then, the waveform synthesis and convolution integration circuit 59 synthesizes the waveform of the real part and the imaginary part and performs the convolution integration, which is input to the modulation unit 17 in FIG. 1 and modulated, and converted into an analog signal by the D / A converter 18. And input to the analog unit 2.

  The reception FFT unit 54 receives the demodulated reception signal, and multiplies the window function corresponding to the time response waveform of the reception Nyquist filter by the window function multiplication and convolution integration circuit 60, and then convolves the Fourier transform unit. Integration is performed and input to the fast Fourier transform unit 61. The fast Fourier transform unit 61 converts the frequency information into frequency information. The real part and the imaginary part are shifted on the transmission side so as to have a ½ Nyquist time length interval. Therefore, the signal extraction and synthesis circuit 62 performs simple synthesis and inputs it to the reception signal point determination circuit 53.

  The configuration of the present invention is shown in FIG. 1 and FIG. 2, and solves the following first to sixth problems. First, the first problem is the realization of high-efficiency data transmission. The key to realizing high-efficiency data transmission is to eliminate waste on the time axis / frequency axis. As one of the implementation examples, there is a conventional Wavelet-OFDM system. This Wavelet-OFDM scheme is a scheme that realizes time-axis orthogonal / frequency-axis orthogonal, but there is a Nyquist transmission scheme as another scheme that realizes efficient data transmission on the time axis.

  The transfer function of the Nyquist transmission method is (0, 1, 0), which is the method that can transmit data at the highest speed without intersymbol interference. Is the transmission method. The present invention realizes multiplex transmission of time-axis orthogonal / frequency-axis orthogonal by applying this Nyquist transmission method and an OFDM method capable of orthogonalization on the frequency axis. Therefore, on the transmitting side, for example, the real part of the signal point is decomposed into the imaginary part, the real part is transmitted first, and then the imaginary part is transmitted after ½ Nyquist time length, so that the adjacent channel is transmitted. High-efficiency data transmission is possible without intersymbol interference.

  The second problem is leakage reduction of a specific band. This can be realized by dividing the Nyquist filter into transmission and reception. Further, in order to achieve deeper leakage reduction with a smaller number of taps, this can be realized by multiplying the transmission side cos filter by a unique window function and reducing side lobes.

  The third problem is noise suppression. As with the transmission side, the reception side is a cosine filter, and a unique window function is multiplied as with the transmission side, so that noise suppression exceeding 70 dB can be achieved.

  The fourth problem is noise cancellation. This is because a zero point is periodically inserted on the transmission side, the data signal point is transmitted between the zero point and the zero point, and the noise component on the zero point transmitted on the transmission side is transmitted on the reception side. Can be realized by performing interpolation prediction and canceling noise superimposed on the signal point.

  The fifth problem is multipath support. In order to reduce the occurrence of errors caused by superimposition of delayed signal components due to multipaths such as branch circuits, it is possible to remove multipaths stably on the receiving side by using, for example, a decision feedback equalizer. is there.

  The sixth problem is timing synchronization. There are two types of timing synchronization: frequency synchronization and phase synchronization. Regarding frequency synchronization, it is sufficient to perform frequency synchronization from synchronization signals obtained from a plurality of channels. The timing phase is adjusted by shifting the time phase by providing an adjustment filter, or the equalizer on the receiving side is not a one-tap complex equalizer but a double sampling equalizer, A configuration for matching the phases can be applied.

  FIG. 3 shows a time response of a transmission path (filter). When an input signal is input to the transmission path (filter) as an impulse, the output signal is a time response by band limitation corresponding to the transmission path (filter) characteristics. It becomes a waveform. When data (various impulse waveforms) is continuously added to the input side of this transmission line (filter), these time response waveforms are output in an overlapping manner on the output side.

  Since the data from the multiplex transmission device is a pulse signal and includes even a high frequency component, if it is sent as it is to a transmission line with band limitation, intersymbol interference occurs due to waveform distortion. Therefore, the waveform is shaped by a filter so that intersymbol interference does not occur, and a pulse is transmitted. This typical filter without intersymbol interference is a Nyquist filter, and has the following frequency characteristics and time response waveform.

First, the frequency response H (f) has a Nyquist time interval of T (s) and a roll-off rate of β (β is 0 to 1).
H (f) = 1, 0 ≦ f ≦ (1-β) / 2T
= [1-sin [πT (f−1 / 2T) / β]] / 2
(1-β) / 2T ≦ f ≦ (1 + β) / 2T
= 0, (1 + β) / 2T ≦ f
It is expressed. On the other hand, the time response waveform A (t) is
A (t) = sinc (πt / T) [cos (πβt / T) / (B)]
Where B = (1− (2βt / T) ² )
It is expressed.

  FIG. 4 is an explanatory diagram of waveforms in Nyquist transmission. As shown in the figure, if the response waveform on the time axis is a waveform that passes through the zero point at equal intervals, even if impulse transmission is performed continuously, Data transmission is possible at high speed without interference of codes. This is the aforementioned Nyquist transmission. That is, the time response of the Nyquist transmission line is (0, 1, 0), which is equivalent to a series that is orthogonal on the time axis.

  FIG. 5 shows the normalized frequency characteristics of the Nyquist transmission line, and the filter characteristics of the Nyquist filter indicate cos square characteristics, and there is an element generally called a roll-off rate. In FIG. The case of 100% is shown.

  FIG. 6 is an image diagram of orthogonal frequency division multiplexing. Each carrier frequency has an integer multiple relationship, and the carriers are orthogonal to each other. For this reason, although the spectrums overlap each other on the frequency axis, at this time, since they are orthogonal to each other on the frequency axis, frequency decomposition can be performed by fast Fourier transform on the reception side. On the transmission side, information on the frequency axis is converted into information on the time axis by inverse fast Fourier transform and transmitted.

  By multiplexing the signals having the waveform orthogonal to each other on the time axis shown in FIG. 4 as signals having the waveforms orthogonal to each other on the frequency axis shown in FIG. 6, highly efficient multiplex transmission is possible. In this case, multiplexing is performed at the Nyquist time interval on the time axis, and multiplexing is performed at the Nyquist frequency interval on the frequency axis.

  FIG. 7 shows a time response waveform when the Nyquist transmission line (cos square characteristic) is divided into transmission and reception, etc., where the transmission filter is a cos filter characteristic, the reception filter is also a cos filter characteristic, and the transmission line is a cos square characteristic. Indicates. As described above, the reason for dividing the filter characteristics into transmission and reception is to optimize the noise tolerance.

  FIG. 8 shows the time response characteristic of the cos filter, which is a response characteristic of (0, 1, 1, 0) at 1/2 Nyquist time intervals, and this is converted into a cos square as shown in FIG. The time response waveform of the filter (1/2, Nyquist time interval (0, 1, 2, 1, 0), Nyquist time interval (0, 1, 0)) can be obtained. High-speed data transmission is possible without intersymbol interference.

  FIG. 10 is an explanatory diagram of interference between adjacent channels, and shows a frequency spectrum when three channels are multiplexed. As shown in the figure, three channels of CH-1 / CH0 / CH + 1 are multiplexed on the frequency axis, but the frequency spectrum of channel CH0 is indicated by the frequency spectrum of channel CH-1 / CH + 1 and the hatching area. It overlaps with. This area causes interference on both the time axis and the frequency axis.

Since the frequency characteristic of the channel CH0 is a cosine filter on the transmission side, if the frequency characteristic of the channel CH0 is F [0] (f), f is in the range of −1 to 1 (Hz).
F [0] (f) = cos (f * π / 2) (1)
It is expressed. If the frequency characteristic of the channel CH + 1 is F [+1] (f), f is 0 to 2 (Hz).
F [+1] (f) = sin (f * π / 2) (2)
It is expressed. Therefore, the frequency spectrum F [0 + 1] (f) in the right hatched area in FIG. 10 is in the range of f = 0 to 1 (Hz).
F [0 + 1] (f) = cos (f * π / 2) * sin (f * π / 2) (3)
= 1/2 (sin (2 * f * π / 2))
= 1/2 (sin (f * π)) (4)
It becomes.

Similarly, the interference area between channel CH-1 and channel CH0 is such that f is -2 to 0 (Hz) when the frequency characteristic of channel CH-1 is F [-1] (f).
F [−1] (f) = − sin (f * π / 2) (5)
It is expressed. Therefore, the frequency spectrum F [0-1] (f) in the left hatched area in FIG. 10 is in the range of f = −1 to 0 (Hz).
F [0-1] (f) = cos (f * π / 2) * (− sin (f * π / 2)) (6)
= −1 / 2 (sin (2 * f * π / 2))
= −1 / 2 (sin (f * π)) (7)
It becomes. Although both have different polarities, they have the same sin filter in terms of power spectrum. Since the transmission side transmits with a 100% cos filter and the reception side also transmits with a 100% cos filter, when the transmission / reception filter is convoluted, the frequency spectrum (interference spectrum) between adjacent channels has a 100% sin filter characteristic.

  11 to 14 are explanatory diagrams of interference between adjacent channels, and all show waveforms when the imaginary component of the signal point is delayed by 1/2 Nyquist time length with respect to the real component. First, FIG. 11 shows a waveform when channel 0 (CH0) is transmitted 0 degrees (only the real component is transmitted) and channel 0 is received with a phase of 0 degrees. The solid line arrow indicates the sampling point of the real component and the broken line arrow indicates the sampling point of the imaginary component, but the sampling result of the real side only (0, 1, 0) is obtained, and the sampling result of the imaginary side is Since (0, 0, 0), it can be said that the waveform transmitted on the transmission side is accurately reproduced on the reception side.

  FIG. 12 is a diagram showing interference between adjacent channels. This shows a waveform (real and imaginary) when channel 0 (CH-1) is transmitted 0 degrees (only the real component is transmitted) and channel 0 is received with a phase of 0 degrees. If the real component is sampled at the point of the solid arrow, there is no interference to the real side. Further, if the imaginary component is sampled at the point of the dashed arrow, there is no interference on the imaginary side. However, if the real component is sampled at the point of the broken-line arrow, interference occurs on the imaginary side.

  FIG. 13 shows a case where 90 ° transmission is performed on channel-1 (only the imaginary component is transmitted), but this time there is no interference if the real component is sampled at the point of the solid arrow. Further, if the imaginary component is sampled at the dotted arrow point, there is no interference, but if the imaginary component is sampled at the solid arrow point, it becomes a real interference component.

  FIG. 14 shows a case where 45 degrees are transmitted on channel-1 (both real and imaginary components are transmitted), but there is no interference if the real components are sampled at the points of solid arrows. If the imaginary component is sampled at the dotted arrow point, there is no interference, but if the imaginary component is sampled at the solid arrow point and the real component is sampled at the dotted arrow point, there is interference.

  As described above, waveform transmission is performed with the imaginary component shifted by a half Nyquist time compared to the real component, the real component is the real point (solid arrow point), and the imaginary component is the imaginary point (dashed line). Sampling is performed at the point indicated by the arrow in FIG. 5, which indicates that waveform transmission is possible without inter-adjacent interference, indicating that time axis orthogonality and frequency axis orthogonality are possible.

  FIG. 15 shows a single-carrier-compatible transmission modulation unit, where 71 is a transmission low-pass filter (transmission LPF), 72 is a transmission modulation unit (transmission MOD), 73 is a transmission carrier generation unit (transmission CRR), and 69 is zero. An insertion unit, 70 is an addition unit (Σ), T is a delay circuit, and shows a part corresponding to the configuration of the modulation unit 17 in FIG. Xm + n and Xm-n indicate signals before nT time and after nT time with respect to Xm + 0, and Cn,..., C0,.

  Signals input at the Nyquist rate are usually converted to an integral multiple of the Nyquist rate and transmitted. The input data signal is first converted from a Nyquist rate to a sampling rate (an integer multiple of the Nyquist rate) by a zero insertion unit 69 of the transmission low-pass filter 71 and a filter unit including a delay circuit and an addition unit 70. Further, the transmission low pass filter 71 shapes the waveform of the data signal so that it can be transmitted at high speed without intersymbol interference. Then, the transmission modulation unit 72 multiplies the carrier signal from the transmission carrier generation unit 73 and shifts the frequency to a desired frequency band.

When this is observed on the time axis focusing on one impulse, the impulse, the filter output, the carrier signal, and the modulation signal are as shown in FIG. First, if the input impulse is Xk, the output F of the transmission low-pass filter 71 is
F = Xk * Cn ... Xk * C + n (8)
It becomes. Next, the output F of the transmission low-pass filter 71 is multiplied by the carrier signal E (jωt) = cos θ + jsin θ, where S is the modulated signal after multiplication.
S = F * E
= Xk * C-n * E (jω (tp))... Xk * C + n * E (jω (t + p))
... (9)
It becomes. This indicates that a sequence obtained by multiplying the input impulse Xk by the carrier signal E (jωt) is calculated, and the result is multiplied by the time response waveform of the cos filter as a window function. Further, since the input impulses are sequentially input in time series, the filter output multiplied by the window function is also sequentially output. In the filter calculation, convolution processing on the time axis is performed, but it is only necessary to perform simple addition on the time axis for the transmission signal finally output as a modulated waveform. It also indicates that the signals of the real part and the imaginary part may be shifted and added by ½ Nyquist time length in order to eliminate the interference of adjacent channels.

  FIG. 17 shows the main part of the transmission IFFT unit, and shows the configuration of the multiplex processing unit in FIG. 2. The same reference numerals as those in FIG. 2 denote the same parts. The transmission data subjected to the scramble processing and the summation processing is input to the transmission signal point generation circuit 51, and the transmission signal point as a vector signal is decomposed into a real part (Real) and an imaginary part (Imag) of the signal point The real part is input to the real part inverse fast Fourier transform unit 55, the imaginary part is input to the imaginary part inverse fast Fourier transform unit 56, and the inverse fast Fourier transform is performed for each, and the real part is multiplied by the time axis window function. The window 57 is multiplied by the window function, and the imaginary part is multiplied by the window function delayed by 1/2 Nyquist time length from the real part by the time axis window function multiplier (1/2 delay) 58, and waveform synthesis and convolution integration are performed. The circuit 59 synthesizes the waveform of the real part and the imaginary part and performs convolution integration, as shown in FIG. Enter the transmission modulator 72 via the signal low-pass filter 71, multiplying the transmission carrier from the transmission carrier generating unit 73.

  18 shows a real part inverse fast Fourier transform unit (Real-part IFFT) 55 and an imaginary part inverse fast Fourier transform unit (Imag-part IFFT) 56 in FIG. 17 described above, a waveform synthesis and convolution integration circuit 59, FIG. 6 is an explanatory diagram of the time axis window function multipliers 57, 58 between the real part and the imaginary part of the vector signal point from the transmission signal point generation circuit 51, respectively, as described above. Unit 55 and the imaginary repart inverse fast Fourier transform unit 56 to convert the signal component on the time axis, multiply the time response waveform of the transmission Nyquist filter as a window function, and the real part side and the imaginary part side Shift time by 1/2 Nyquist time length. This state is indicated by a symbol array of IFFT having a Nyquist time length and an impulse response waveform. Then, the waveform synthesis and convolution integration circuit 59 performs synthesis by performing vector addition on the real part side and the imaginary part side, and then outputs a signal obtained by performing the convolution integration. In addition, since continuously input transmission data is delayed by one Nyquist time length on the time axis, it is added to the previous waveform as a vector with a shift of one Nyquist time length, and the addition output is the transmission baseband. Signal. In this way, when the real part and the imaginary part of the vector signal are multiplied by the window function, one of the waveforms after the window function multiplication is reduced to 1/2 by delaying one of the window functions by ½ Nyquist time. Since the Nyquist time can be shifted, the carrier phase (real part and imaginary part) of the signal point itself does not shift.

  19 shows a main part including the modulation processing means in the multiplexing processing unit 12 in FIG. 1, 74 is a signal point generation circuit, 75 is a transmission IFFT unit, 76 is a transmission LPF unit, 77 is a transmission MOD unit, Reference numeral 78 denotes a transmission CRR unit, which has a configuration corresponding to the signal point generation unit 15, the inverse fast Fourier transform unit 16, and the modulation unit 17 in FIG. Further, the signal point generation circuit 74 corresponds to the transmission signal point generation circuit 51 of FIG. 17, and the transmission IFFT unit 75 corresponds to the transmission IFFT unit 52 of FIG. As described above, the transmission data input to the signal point generation circuit 74 is separated into a real part and an imaginary part, converted into a baseband time waveform by the transmission IFFT unit 75, and an unnecessary band by the transmission LPF unit 76. The transmission MOD unit 77 modulates the carrier frequency signal from the transmission CRR unit 78 to obtain a transmission signal that is input to the analog unit 2 (see FIG. 1) through the D / A converter 18.

  20 shows a main part including the demodulation processing means in the demultiplexing processing unit 13 in FIG. 1, 84 is a receiving DEM unit, 85 is a receiving CRR unit, 86 is a receiving LPF unit, 87 is a receiving FFT unit, 88 Indicates a signal point determination circuit, and shows a configuration corresponding to the demodulation unit 20, the fast Fourier transform unit 21, and the signal point determination unit 23 in FIG. A reception signal (see FIG. 1) output from the analog unit 2 and converted into a digital signal by the A / D converter 19 is input to the reception DEM unit 84, demodulated by the carrier signal from the reception CRR unit 85, and received by the reception LPF unit 86, an unnecessary band is removed, and a Fourier transform is performed by the reception FFT unit 87 to be a frequency domain signal. A signal point determination circuit 88 performs signal point determination to generate reception data, and the difference and descrambling circuit 25 (FIG. 1). The difference processing and descrambling processing, which are the reverse of the summing processing on the transmission side, are performed.

For reception demodulation, it is originally demodulated by each carrier signal E (jωt), and a reception signal point is obtained via a waveform shaping filter. This calculation is performed by converting a reception signal sequence (impulse sequence) When R (k−m),..., R (k + m), first, carrier signals E (jω (tp)),..., E (jω (t + p)) are multiplied.
R (k−m) * E (jω (tp)),..., R (k + m) * E (jω (t + p))
Further, the waveform shaping filter coefficients C + n,..., Cn are multiplied to obtain a filter output F represented by the following equation.

F = Σ [R (k−m) * E (jω (tp)) * C + n +.
+ R (k + m) * E (jω (t + p)) * C−n] (10)

  The above equation is obtained by decomposing the signal sequence obtained by multiplying the received signal sequence R by the window function based on the time response waveform C of the waveform shaping filter on the frequency axis by fast Fourier transform, and adding it on the time axis (convolution integration) If this is implemented, it is shown that the received waveform shaping filter process can be processed very easily. Further, since the transmission side transmits the imaginary component in a form shifted by 1/2 Nyquist time length, if the reception FFT unit 87 performs output calculation at twice the Nyquist frequency interval, the reception data is received. Can be played. Specifically, it can be processed as waveforms shown in FIGS.

  21 and 22 are explanatory diagrams of the reception FFT unit. The same reference numerals as those in FIG. 2 indicate the same parts, and reference numeral 89 in FIG. 22 indicates a window function multiplication and convolution integration circuit / FFT. 22 is a functional block for explaining the operation of the signal extraction / synthesis circuit 62, the fast Fourier transform unit 61, and the window function multiplication / convolution integration circuit 60 (means for multiplying a window function) in FIG. The received signal is multiplied by a window function (time response waveform of the received Nyquist filter) in the window function multiplication and convolution integration circuit 60, and the result of multiplication with this window function is convolved and integrated in FFT units, and in the fast Fourier transform unit 61. FFT processing is performed to obtain individual frequency information. Since the real part and the imaginary part are each shifted by ½ Nyquist time length, the multiplication of the received signal and the window function is performed at an interval twice the Nyquist frequency (time axis of the window function). Are shifted by 1/2 Nyquist time interval). As a result, after FFT, in order to obtain a desired real part signal / imaginary part signal, these are simply synthesized in the signal extraction and synthesis circuit 62 to obtain a desired received signal point. As described above, the demultiplexing processing unit 13 multiplies the time response waveform of the received Nyquist filter as a window function, and performs first fast Fourier transform on the output signal of this means at the Nyquist time interval and adds the first signal. Means, a second means for multiplying the window function by shifting by 1/2 Nyquist time length, fast Fourier transform and adding, and extracting a real part and an imaginary part from each added output signal to determine a signal point Means for performing.

FIG. 23 is an explanatory diagram of the relationship between the number of channels and the frequency. In a frequency band for 6 channels, multiplexing for 5 channels of channels CH-2 to CH + 2 is performed with a Nyquist frequency interval centered on channel CH-0. It is possible to make it possible. Therefore, the transmission efficiency Ea in this case is
Ea = (5/6) = 83.3 [%] (11)
It becomes. Similarly, when 99 channels are multiplexed,
Ea = 99/100 = 99.0 [%] (12)
Thus, by increasing the number of multiplexing, highly efficient data transmission becomes possible.

  FIG. 24 is an explanatory diagram of specific band leakage reduction. In the case of interference prevention for a specific band within a frequency band by multiple channel multiplexing, for example, at least two channels are notch ( (Leakage reduction) can be performed.

  FIG. 25 is an explanatory diagram of unnecessary band suppression. The unnecessary band of each channel is cut (suppressed) by the Nyquist filter on the receiving side, whereby noise components due to the unnecessary band can be suppressed. This amount of noise suppression is determined by the filter characteristics (filter coefficient and number of taps), but can be optimized according to the requirements on the system side.

  FIG. 26 is an explanatory diagram of interference cancellation between adjacent channels, which can be applied, for example, when performing interference cancellation between adjacent channels at the time of training. For example, for even channels CH + 0, CH-2, and CH + 2, ( (1, 1, 1, -1), and the odd channels CH + 1 and CH-1 are transmitted in the sequence (1, -1, 1, 1). The channel transmitted in the sequence of (1, -1) is received at (1, 1, 1, -1), and the channel transmitted in (1, -1, 1, 1) is (1, -1). , 1, 1). In other words, since the adjacent channels can be transmitted in an orthogonal form, the reception side can restore the received signal without interference between adjacent channels. When this means is applied, the transmission speed will be reduced by half, but it is possible to stably extract timing signals, carrier signals, etc. mainly by applying it to training signals transmitted and received prior to data transmission. can do.

  FIG. 27 shows an equivalent circuit of a low-pass filter, which can be applied to the above-described transmission low-pass filter and reception low-pass filter, where T is a delay circuit, Σ is an addition circuit, Cn,..., C0,.・, C + n indicates a tap coefficient.

  28 shows the configuration of the modulation unit 17 in FIG. 1, FIG. 29 shows the configuration of the demodulation unit 20 in FIG. 1, cos θ and −sin θ indicate the center carrier, and the modulation unit 17 has a real part (input). Real) and cos θ, and the imaginary part (input Imag) and −sin θ are combined to produce a modulated output signal. The demodulator 20 multiplies the input signal by cos θ and −sin θ, respectively, and outputs a real part (output Real) and an imaginary part (output Imag).

  On the transmission side, the window function processing is performed by multiplying the IFFT output by the time response waveform of the transmission Nyquist filter as it is. On the reception side, the window function processing on the reception side is performed by multiplying the received signal by the time response waveform of the reception Nyquist filter as it is, and then performing FFT processing. FIG. 30 shows an outline of the transmission / reception filter characteristics in this case. In the figure, the vertical axis represents amplitude characteristics, the horizontal axis represents frequency, and the Nyquist frequency interval. SBFRM indicates a subframe, and this time length is made equal to the Nyquist time length. That is, 2SBFRM indicates a filter characteristic in which the time response waveform length of the filter is set to a time length twice that of Nyquist. 8SBFRM has a filter characteristic having a Nyquist time length of 8 times. For this reason, if the number of subframes (SBFRM) is large, the filter characteristics are good, but the processing becomes heavy as the number of taps increases. As is apparent from the figure, it is shown that the processing of the time length of 8SBFRM is insufficient to achieve the target of 70 dB.

  In general, if the filter function is subjected to time axis window function processing, components outside the unnecessary band can be improved. Typical window functions include square wave / triangular wave / Hanning window / Humming window / Blackman window / flat top window. Among these, those having excellent out-of-band characteristics include Hanning window / Blackman window / flat top window. Therefore, there are two main purposes: the purpose of multiplex transmission being Nyquist transmission and the reduction / removal of components outside unnecessary bands as much as possible. This is the first data transmission part, but this is sufficient even if 1024-value transmission is performed, if the 1st peak component is about 40 dB or less in terms of transmission / reception combining characteristics. From the characteristics shown in (2), it is sufficient to have a filter with a time length of 2SBFRM. Therefore, regarding the time portion exceeding the time length of 2SBFRM, for example, it is considered that the unnecessary band can be efficiently reduced / removed by multiplying the coefficient of the Hanning window. As a feature of the hamming window, there is a case where the transition region can be sharpened. However, as a disadvantage, the attenuation in the stop band cannot be increased too much.

  As described above, there are a Hamming window function and a Hanning window function as window functions to be multiplied at both ends of the time axis. However, in the present embodiment, a window function having higher noise suppression and no intersymbol interference is used. The Hanning window function shown in Fig. 1 was selected (the window function is W (n)).

W (n) = β- (1-β) cos (2πn / (N−1)) (0 ≦ n ≦ N−1)
= 0 (Other)
However, 0 ≦ β ≦ 1
In particular, Hanning window when β = 0.5
Hamming window when β = 0.54

  FIG. 31 is an explanation of the window function. The vertical axis represents normalized amplitude, the horizontal axis represents time, the Nyquist time interval centered on 0, the time waveform of the window function, and the filter coefficient before and after the window function multiplication. Show. During the ± 1.5 Nyquist time length, the window function is multiplied by a value of 1.0 to ensure characteristics as a transmission line. For the portion where the window function exceeds ± 1.5 Nyquist time length, in order to reduce / remove unnecessary out-of-band components, the Hanning window function is multiplied to reduce / remove out of the unnecessary band. In the power line carrier system as shown in the present embodiment, the transition region is important for Nyquist waveform shaping and cannot be destroyed. In addition, as steep characteristics as possible are required for the stop band. Therefore, the central portion of the time response waveform is divided into regions of the central portion and both sides of the central portion. The central portion region is a square window function, and the both side portion regions are optimized as a Hanning window function. Note that this is an example, and a window function other than the Hanning window function can be applied.

  FIG. 32 is an explanatory diagram of filter characteristics depending on the presence or absence of window function multiplication, in which the vertical axis indicates amplitude characteristics, the horizontal axis indicates frequency, and the Nyquist frequency interval. In the case of only the rectangular window, the characteristic is a thin line, and the characteristic of the thick line is obtained by applying the function of the unique window shown in FIG. Therefore, the target of 70 dB is achieved in the vicinity of the Nyquist frequency interval 2. For this reason, it is possible to reduce leakage in the characteristic band on the transmission side and to suppress noise during large amplitude tone noise on the reception side.

  Noise suppression can be quite effective with respect to unnecessary components outside the band seen from each channel. However, it is incapable of large amplitude tone noise mixed in the same band. In this case, noise cancellation or the like is applied to narrow-band large-amplitude tone noise mixed in the band, and noise cancellation or the like is applied.

  FIG. 33 is an explanatory diagram of a main part to which the noise canceling unit is applied. The same reference numerals as those in FIGS. 19 and 20 denote the same names, 91 is a signal point generation unit, 92 is a transmission zero point insertion circuit, and 93 is An FFT unit 94 indicates a reception noise cancellation circuit. On the transmission side, the signal point generation circuit 74 includes a signal point generation unit 91 and a transmission zero point insertion circuit 92. After the transmission signal point is generated by the signal point generation unit 91, the signal is generated in the transmission zero point insertion circuit 92. A zero point is inserted between the points to obtain a transmission signal through the transmission IFFT unit 75, the transmission LPF unit 76, and the transmission MOD unit 77 by the above-described means.

  On the reception side, the reception FFT unit 87 includes an FFT unit 93 and a reception noise cancellation circuit 94, and the reception signal demodulated through the reception DEM unit 84 and the reception LPF unit 86 is input to the reception FFT unit 87. To do. The FFT unit 93 performs Fourier transform, and the reception noise cancellation circuit 94 extracts the noise component on the zero point, interpolates and predicts the noise component on the signal point between the zero points, and removes the noise component on the signal point. To the signal point determination circuit 88. Basic means for performing noise cancellation processing on the receiving side by this zero point insertion is described in detail in Japanese Patent Laid-Open No. 2002-164801, and redundant description is omitted. In the present invention, as described above, in the method of orthogonal transmission on the time axis and the frequency axis, zero points are inserted alternately on the real part side and the imaginary part side. Similarly, on the receiving side, signal points appear alternately and zero points appear differently. The reception cancel circuit 94 considers such points and performs noise thinning and interpolation prediction. Processing will be performed.

  FIG. 34 is an explanatory diagram of a main part to which a multipath countermeasure has been taken. The same reference numerals as those in FIG. 33 denote the same names, and 95 denotes a decision feedback type automatic equalizer. This decision feedback type automatic equalizer 95 removes the noise component on the signal point by the reception noise cancellation circuit 94 and inputs it, and feeds back the decision information of the signal point decision circuit 88 to perform equalization processing. . In various data transmission paths, reception distortion may occur due to multipath of the transmission paths. In response to this multipath, the OFDM scheme provides a guard time to implement a multipath countermeasure. In ISDN, since the Nyquist time length is shorter than the multipath time length, a countermeasure is implemented by using a decision feedback equalizer. In PHS, since the Nyquist time length is sufficiently longer than the multipath time length, no particular measures are taken.

  As described above, the present invention is based on Nyquist transmission and is time-axis orthogonal / frequency-axis orthogonal. Therefore, providing a guard time as in OFDM is not a good measure for performing highly efficient data transmission. When the Nyquist time interval is larger than the multipath time interval (for example, the multipath time length in a megahertz band PLC (Power Line Communication) is about 2 μs at the maximum, the Nyquist time length is doubled. Even when a decision feedback type automatic equalizer is provided, the tap coefficient does not grow (there is no value that can be grown). For this reason, it is conceivable to set the Nyquist time length sufficiently longer than the multipath time length as one means for countermeasures against multipath. In the case where the multi-value conversion rate is increased, and when a considerable accuracy is required, it is preferable to provide a decision feedback type automatic equalizer 95 as shown in FIG.

  When multiple channels are multiplexed on the frequency axis, the timing frequency is determined by the transmission timing of the master station modem, so one is sufficient. However, the timing phase depends on the group delay characteristics of individual transmission paths. Strictly speaking, time equalization is required. This time equalization is performed by adjusting the timing phase by shifting the coefficient of the low pass filter (LPF) along the time axis, or by using a double sampling type automatic equalizer that is earlier than the Nyquist interval, for example. Any of enabling reception independently can be applied. For example, a time equalizer corresponding to a channel can be provided to equalize the group delay characteristics.

  FIG. 35 is an explanatory diagram of a main part to which means for adjusting the timing phase is applied. The same reference numerals as those in FIG. 34 denote the same names, 96 is a time equalization circuit, and 97 is a TIP (timing interpolation) phase. An adjustment unit 98 is a TIM (timing) extraction unit. This time equalization circuit 96 is provided between the FFT unit 93 and the reception noise cancellation circuit 94. The timing phase corresponding to the channel of the output of the FFT unit 93 is extracted by the TIM extraction unit 98, and the TIP phase adjustment unit 97 performs phase adjustment so that the extraction result becomes a predetermined phase. The TIP phase adjustment unit 97 can be configured by a transversal filter similar to that shown in FIG. 27, for example. Further, the timing phase is adjusted by moving the filter coefficient over time. Thereby, time equalization with respect to the group delay distortion of the transmission line can be performed. The detailed description of this time equalization is described in Japanese Patent Application Laid-Open No. 2003-324360, and thus a duplicate description is omitted.

  FIG. 36 is an explanatory diagram of a main part to which the error correction means is applied. The same reference numerals as those in FIGS. 33 to 35 denote the same name parts, 99 is a transmission error correction unit, 100 is a signal point determination unit, and 101 is reception. Indicates an error correction section. A transmission error correction unit 99 is provided on the transmission side, and a reception error correction unit 101 is provided on the reception side. In the power line carrier system, amplitude characteristics / group delay characteristics / loss characteristics / signal-to-noise characteristics are shown. Varies greatly along the frequency axis, and the data transmission quality has a large correlation with the frequency when the transmission path is determined. For this reason, data is transmitted with frequency-dependent redundancy on the transmission side, and data transmission quality that depends on individual frequencies (channels) is used on the reception side, using the redundancy added on the transmission side. By providing the detection means (SQD circuit), it is possible to perform strong error correction on the receiving side. The operation in data transmission by the transmission error correction unit 99 and the reception error correction unit 101 in this case is described in, for example, Japanese Patent Application Laid-Open No. 2003-134095, and redundant description is omitted.

  Further, in the power line carrier system, there are multipath / transmission path loss / group delay distortion associated with multi-branch connection. In addition, there is noise associated with incoming radio waves from home appliances / existing wireless stations. Since the deterioration factor with respect to these data transmissions changes every moment according to the connection state of the connected home appliances and the operation status, transmission at a specific frequency may not be guaranteed. For this reason, in order to realize stable data transmission, one solution is to perform information transmission over a plurality of frequencies. As a specific means, there is a spread spectrum. Since the transmission quality using the power line as a transmission line has a strong correlation with the frequency, it is a good idea to spread the spectrum without depending on the frequency.

  In addition, switching noise generated from home appliances such as inverters is often a large number of harmonic groups. For this reason, when performing spread spectrum, it is desirable to arrange the selected frequencies irregularly (randomly) rather than regularly (for example, integer multiple intervals). Furthermore, since the distortion of the transmission line covers a wide band, it is advantageous to arrange it over a wide range, not locally. For example, when there are 49 channels and the spectrum spread is 7 times, it is roughly divided in units of 7 frequencies, and by selecting among these 7 by 7PN, random and almost wide band on the frequency axis It is a good idea to achieve uniform transmission and improve transmission quality.

  FIG. 37 is an explanatory diagram of a main part for transmitting and receiving data by performing spectral dispersion on a plurality of channels with the multiplexing unit 12 on the transmission side, and FIG. 38 with the receiving side demultiplexing processing unit 13, respectively. For example, the signal A from the signal point generation unit 91 of the signal point generation circuit 74 described above is spread-modulated and transmitted in a state of being dispersed in the channels CH0, CH5, CH10, CH15, CH16, CH21, CH26, and CH31. In this case, if there are four types of modulation points MOD0 to MOD3, the modulation points are also made different depending on the channel.

  In FIG. 38, the received signal point determination & SQD (signal quality) part of the signal point determination circuit 88 has received the determination results for the signals A of the received and demodulated channels CH0, CH5, CH10, CH15, CH16, CH21, CH26, and CH31. Weighting is performed, addition is performed by the addition unit (Σ), and the signal point determination unit 100 determines the received data. In this case, the signal quality (SQD) differs depending on the channel conditions CH0 to CH31 having different frequencies due to different transmission path conditions including noise and the like. The better the signal quality (SQD), the higher the weighting. It is possible to dramatically improve the transmission quality. In this case, the multiplexing processing unit 12 multiplexes the signal to be transmitted on either or both of the frequency axis and the time axis in a spread state, and the demultiplexing processing unit 13 performs signal point determination corresponding to the spread channel. Then, a signal point determination is performed again for the result of the addition or a spread channel corresponding to the addition result, and a coefficient corresponding to the transmission quality (signal quality SQD) is respectively multiplied as a weight. And a means for performing signal point determination again on the addition result.

  In the configuration shown in FIG. 2, the transmission signal point generation circuit 51 shows a case where the signal points corresponding to the transmission data are processed separately for the real part and the imaginary part. It is also possible to process separately. FIG. 39 shows a case where the main parts of the multiplexing processing unit 12 and the demultiplexing processing unit 13 are configured to process the signal points corresponding to the transmission data separately for the even channel and the odd channel, 51 is a transmission signal point generation circuit corresponding to the signal point generation unit 15 in FIG. 1, 52 is a transmission IFFT unit corresponding to the inverse fast Fourier transform unit 16 in FIG. 1, and 53 is corresponding to the signal point determination unit 23 in FIG. A reception signal point determination circuit 54 indicates a reception FFT unit corresponding to the fast Fourier transform unit 21 in FIG. 111 and 112 are IFFT units, 113 is a time-axis window function multiplier, 114 is a time-axis window function multiplier (1/2 delay), 115 is a waveform synthesis and convolution integration circuit, and 116 is a window function multiplication and convolution integration. Circuits 117 and 118 denote FFT units.

  In the multiplexing processing unit on the transmission side, the transmission signal point generation circuit 51 divides signal points corresponding to transmission data into even channels and odd channels, and inputs them to the IFFT units 111 and 112 of the transmission IFFT unit 52, respectively. A signal on the frequency axis is converted into a signal on the time axis and input to the time axis window function multipliers 113 and 114 to multiply the signals of the even channel and the odd channel by the window function as described above. . At this time, the window function of the time-axis window function multiplier 114 is delayed by 1/2 Nyquist time length with respect to the window function of the time-axis window function multiplier 113. Then, the waveform synthesis and convolution integration circuit 115 synthesizes and outputs the signals of the even channel and the odd channel.

  In the demultiplexing processing unit 13 on the receiving side, the signals of the even channel and the odd channel are multiplied by the window function corresponding to the window function on the transmitting side by the window function multiplication and convolution integration circuit 116, respectively. The signal on the time axis is converted into a signal on the frequency axis by 118, and the signal points of the even channel and the odd channel are determined by the reception signal point determination circuit 53 to be received data.

  Time shift of 1/2 Nyquist time length with respect to real part and imaginary part with respect to FIGS. 11 to 14 by time-shifting transmission point data of even channel and odd channel with 1/2 Nyquist time length by window function As in the above case, there is no interference between them, and multiplex transmission is possible.

  The multiplex transmission apparatus described above can be configured to include only one of the multiplex processing unit 12 and the multiplex / demultiplex processing unit 13, and multiplex processing on the transmission side in data transmission is possible. A multiplex transmission apparatus having the part 12 as a main part or a multiplex transmission apparatus having the receiving side demultiplexing processing part 13 as a main part can be provided. Similarly, only one of the multiplex transmission methods can be applied.

  When such a multiplex transmission apparatus is applied to a power line carrier system, one communication path (power line) must be used in a set of a plurality of multiplex transmission apparatuses, and when a power line is used, a wide dynamic range is required. Because it is required, it is a good idea to implement a multiplexing scheme using a time division multiple access (TDMA) system instead of a frequency division multiple access (FDMA) system. The TDMA system is a system in which time is divided and allocated to each station, and the entire bandwidth of the user communication path can be used during the allocated time (this is called “time slot”). Each station transmits a signal intermittently and periodically (this period is referred to as a “frame period”). When the TDMA system is used, the multiplex transmission apparatus set as the master station finds an unused time slot (hereinafter referred to as “empty slot”), and transmits a specific signal (ID signal) to the empty slot. The multiplex transmission apparatus set to 1 detects a specific signal of the master station to which the slave station belongs, and specifies a time slot for communicating with the master station. At this time, the slave station is configured to synchronize the clock of the master station and the clock of the local station (slave station) using a specific signal from the master station.

  The time slot selection and clock synchronization method will now be described. First, the clock synchronization method will be described. In this embodiment, as shown in FIG. 40, the first PLL means 200 that synchronizes with the first synchronization signal and the second PLL that synchronizes with the second synchronization signal. A synchronizing device having a PLL means 300 and synchronizing with these two synchronizing signals. The second PLL means 300 outputs the output signal (first estimated synchronizing signal) of the first PLL means 200 to this synchronizing means. By establishing synchronization as the synchronization quantization unit of the second PLL means 300, synchronization is established with two different synchronization signals. Then, it demonstrates concretely hereafter.

  In order for the master station and the slave station connected to the transmission path to select a time slot, a reference clock that can be referred to by both is required. In this embodiment, synchronization is performed using the power supply frequency in the power line. A signal (corresponding to the second synchronization signal described above) is generated. Since the power supply frequency in Japan is 50 Hz or 60 Hz, the present embodiment is configured to extract a synchronization signal of 20 Hz from the power supply frequency so that any frequency can be supported.

  FIG. 41 shows a 20 Hz synchronization signal detection circuit 120 configured to extract a synchronization signal of 20 Hz from the power supply frequency, 121 is a zero cross point detection circuit and time window generation circuit, 122 is a specific signal detection circuit, and 123 is A 20Hz synchronous signal selection circuit is shown. The PLC signal extracted from the power line (AC 100 V) is input to the zero cross point detection circuit and the time window generation circuit 121. As shown in FIG. 42, the zero-cross point detection circuit is configured to output a pulse signal when the power supply voltage becomes 0 V (that is, at the zero-cross point). A time window of 20 Hz is set for every 5 pulses in the case of 50 Hz and for 6 pulses in the case of 60 Hz. Further, the PLC signal extracted from the power line is input to the specific signal detection circuit 122, and the specific signal is detected. The time window set in the zero cross point detection circuit and time window generation circuit 121 and the detection result by the specific signal detection circuit 122 are input to the 20 Hz synchronization signal selection circuit 123. When a specific signal is detected in the set time window, the 20 Hz synchronization signal selection circuit 123 establishes 20 Hz synchronization based on the specific signal and outputs a 20 Hz synchronization signal, and the specific signal is not detected. Determines that there is no other master station, and independently sets and determines the 20 Hz phase and outputs it as a 20 Hz synchronization signal. The 20 Hz synchronization signal detection circuit 120 is provided in both the master station and the slave station.

  FIG. 43 shows the master station side PLL circuit 130, 131 is a phase advance / delay determination circuit, 132 is a first integration circuit, 133 is a second integration circuit, and 134 is a second frequency divider circuit. The master station side PLL circuit 130 includes a first frequency divider circuit based on an oscillation frequency (for example, 32 MHz) oscillated from a high-precision clock oscillation circuit 39 (corresponding to the digitally controlled crystal oscillator (DCXO) 34 in FIG. 1). 40 generates a Nyquist clock (for example, 62.5 kHz). Then, using this Nyquist clock as a basic unit, a secondary PLL is constructed, synchronization with the 20 Hz synchronization signal input from the 20 Hz synchronization signal detection circuit 120 is established, and an estimated 20 Hz synchronization signal is output. Here, since the power supply frequency fluctuates by about ± 2 Hz, the frequency tracking range of the PLL is 48 Hz to 62 Hz, that is, the time length is 48.3 ms to 52.1 ms.

  Therefore, the secondary PLL circuit detects the phase information by comparing the 20 Hz synchronization signal with the estimated 20 Hz synchronization signal output from the second frequency divider circuit 134 in the phase advance / delay determination circuit 131. Is input to the first integrating circuit 132, and the first integrating circuit 132 integrates and outputs the frequency information from the phase information. Then, the phase information output from the phase advance / delay determination circuit 131 and the frequency information integration result output from the first integration circuit 132 are added together and input to the second integration circuit 133. The final integration of the phase information is performed in the second integration circuit 133, and the frequency division ratio of the second frequency dividing circuit 134 is controlled using the integration result. In this embodiment, since the Nyquist clock is 62.5 kHz (16 μs), the frequency dividing ratio of the second frequency dividing circuit 134 is in the range of 3018 to 3257 counts.

  44 shows the master station time slot selection circuit 140, 141 is a specific signal demodulation circuit, 142 is a specific signal detection circuit, 143 is a controller (CPU), 144 is a specific signal transmission circuit, and the controller 143 is This corresponds to the controller 26 in FIG. The controller 143 in the master station time slot selection circuit 140 detects the specific signal by the specific signal detection circuit 142 using the PLC signal received from the power line, and based on this, the specific signal demodulation circuit 141 converts the received data RD. Reproduce. Then, an empty slot is detected based on the estimated 20 Hz synchronization signal output from the above-mentioned master station side PLL circuit 130, and the ID signal of this master station is transmitted to the power line as a specific signal by the specific signal transmission circuit 144.

  On the other hand, FIG. 45 shows the slave station side PLL circuit 150, and FIG. 46 shows the slave station side time slot selection circuit 160. In FIG. 45, 151 is a specific signal TIM (timing) phase extraction circuit, 152 is a specific signal detection circuit, 153 is a phase advance / delay determination circuit, 154 is a first integration circuit, 155 is a second integration circuit, and 156 is 20 Hz synchronous. The specific signal TIM phase extraction circuit 151 to the second integration circuit 155 correspond to the first PLL means 200 in FIG. Note that the 20 Hz synchronous PLL circuit 156 in the slave station side PLL circuit 150 corresponds to the second PLL means 300 in FIG. 40, and has the same configuration as the master station side PLL circuit 130 shown in FIG. The same reference numerals are assigned and detailed description is omitted. The 20 Hz synchronization PLL circuit 156 synchronizes the 20 Hz synchronization signal output from the 20 Hz synchronization signal detection circuit 120 with an estimated 62.5 kHz synchronization signal described later as a quantization unit, and the estimated 20 Hz synchronization signal (second in FIG. Corresponding to the estimated synchronization signal). 46, reference numeral 161 denotes a specific signal demodulation circuit, 162 denotes a specific signal detection circuit, 163 denotes a controller (CPU), and the controller 163 corresponds to the controller 26 in FIG.

  In the slave station, the controller 163 of the slave station side time slot selection circuit 160 detects the specific signal by the specific signal detection circuit 162 using the PLC signal received from the power line, and receives it by the specific signal demodulation circuit 161 based on this. Data RD is reproduced. Then, the ID signal included in the received data RD is compared with the ID signal set as the master station of the own station and input to the controller, and is output from the 20 Hz synchronous PLL circuit 156 of the slave station PLL circuit 150. A time slot set by the master station is detected based on the estimated 20 Hz synchronization signal, and the time slot is output as a specific signal time slot selection signal.

  The slave station side PLL circuit 150 is based on an oscillation frequency (for example, 32 MHz) oscillated from a high-accuracy clock oscillation circuit 39 (corresponding to the digitally controlled crystal oscillator (DCXO) 34 in FIG. 1). To generate a Nyquist clock (for example, 62.5 kHz, corresponding to the first synchronization signal in FIG. 40). Further, the specific signal is detected by the specific signal detection circuit 152 using the PLC signal received from the power line, and the timing phase information of the specific signal is extracted by the specific signal TIM phase extraction circuit 151. Then, the phase advance / delay determination circuit 153 receives the specific signal timing phase information of the time slot selected by the specific signal time slot selection signal output from the slave station side time slot selection circuit 160 and the first frequency dividing circuit 40. The output Nyquist clock (estimated 62.5 kHz synchronization signal) is compared, and a phase error is output. This phase error is integrated between the frequency information and the phase information by the first integration circuit 154 and the second integration circuit 155, and the result is used to control the high-accuracy clock oscillation circuit 39, whereby the selected specific signal is returned to the original. The Nyquist clock of the slave station can be synchronized with the Nyquist clock of the master station (this signal is the estimated 62.5 kHz synchronization signal in FIG. 45 and corresponds to the first estimated synchronization signal in FIG. 40). Thus, the estimated 20 Hz synchronization signal output from the 20 Hz synchronization PLL circuit 156 is also synchronized with the master station.

  As described above, the Nyquist clock (first estimated synchronization signal) of the slave station is micro-synchronized with the Nyquist clock of the parent station, and at the same time, the estimated 20 Hz synchronization signal (second estimated synchronization signal) is used as the power supply frequency. On the other hand, by synchronizing the Nyquist clock (first estimated synchronization signal) in a macro manner using one quantization unit, it is possible to establish synchronization with respect to the two clocks and realize high-speed data transmission.

  On the receiving side of such a multiplex transmission apparatus, it is necessary to establish various pull-in operations of timing phase, carrier phase, and carrier amplitude as a data transmission path prior to receiving user data. In particular, when applied to a power line carrier system, the line characteristics are subject to considerable fluctuations on the frequency axis, so these operations need to be performed on a channel basis. For this reason, in this embodiment, as shown in FIG. 47, prior to transmission of user data, the training signal is configured to be transmitted using all channels, and various setup operations on the receiving side are established. In this embodiment, a 10PN signal is selected as a training signal, 2 subframes are provided for the non-signal part (NTE), 10 subframes are provided for the training signal, and 4 subframes are provided before and after the training signal. In this example, 20 subframes (subframe period = about 320 μS) are used.

  By the way, since this training signal is composed of a fixed pattern and is transmitted at the same time on all channels on the time axis as described above, if transmitted as it is, the peak value of the signal increases and the peak value of the leakage electric field increases. This makes it difficult to obtain desired performance. FIG. 48 shows a main part of the multiplexing processing unit 12 configured such that the peak value of the signal does not increase even when such a training signal is transmitted, 171 is a scrambler circuit (SCR), and 172 is a G / N. Conversion and summing circuit (G / N conversion summing), 173 is a transmission signal point generating circuit, 174 is a random phase rotation circuit, 175 is a real-imaginary separation circuit, 176 is an inverse fast Fourier transform circuit (IFFT), 177 is A window function multiplication circuit is shown. Note that the scrambler circuit 171 and the G / N conversion / summing circuit 172 correspond to the scrambler / summing circuit 14 in FIG. 1, and the transmission signal point generation circuit 173, the random phase rotation circuit 174, and the real-imaginary separation circuit 175. Corresponds to the signal point generation unit 15 in FIG. 1, and the inverse fast Fourier transform circuit 176 and the window function multiplication circuit 177 correspond to the inverse fast Fourier transform unit 16 in FIG.

  Transmission data input to the scrambler circuit 171 is randomized, and the G / N conversion and summing circuit 172 takes measures against error generation uniformity and phase indefiniteness, and further inputs to the transmission signal point generation circuit 173. Thus, an original transmission signal point is generated from each transmission data. Each of these transmission signal points is multiplied by random phase rotation by a random phase rotation circuit 174 to perform random phase rotation, and phase randomization on the frequency axis is performed. By this random phase rotation circuit 174, predistortion compensation on the frequency axis is performed, and the final peak value leakage can be reduced by subsequent time dispersion. The transmission signal point subjected to the random phase rotation is separated into a real part and an imaginary part by the real-imaginary separation circuit 175, and converted into a signal component on the time axis by the inverse fast Fourier transform circuit 176, A window function multiplication circuit 177 performs window function multiplication and convolution integration, and converts the result into a desired transmission baseband (BB) output.

  FIG. 49 shows the result of reducing the leakage of the peak value by performing random phase rotation of 511PN for each channel, and the ratio of the peak value to the average value (PAR) is improved by about 8 dB. In other words, considering that the PAR of white noise is about 15 dB, the peak value leakage can be reduced by about 7 dB. It is also possible to further reduce the peak value leakage by applying a π / 4 shift method or the like to the above.

  The modulation scheme applied to the multiplex transmission apparatus shown in the present embodiment realizes orthogonal multiplex transmission on the time axis / frequency axis, and has extremely high transmission efficiency. However, since uniaxial interference occurs between adjacent channels, it is necessary to stably remove these interference axes during data communication. As described above, in the present embodiment, since it is randomized by the scrambler circuit 171, it is difficult to specify the interference axis. For this reason, a dedicated training signal is transmitted on the transmission side, and on the reception side, timing phase synchronization and carrier phase synchronization are established based on them, and the interference axis is stably extracted and removed. Yes.

  As described above, as a requirement for the training signal under the condition that there is interference between adjacent channels and the training signal itself is subjected to random phase rotation on the transmission side, first, the timing of the own carrier The phase can be accurately extracted (interference S / N = 40 dB or more), the carrier phase of the own carrier can be accurately extracted (interference S / N = 40 dB or more), and the third carrier can be received. The signal level can be accurately extracted (interference S / N = 40 dB or more), and fourthly, the above three points are required to be stably extracted even in an environment where the S / N is −10 dB.

  In order to perform information extraction with noise tolerance in a noise environment with S / N of −10 dB, correlation filter detection using a plurality of symbols is effective. However, in the orthogonal sequence using the normal M sequence, the correlation value 1 / n depending on the number of symbols n remains, so the condition that interference S / N = 40 dB or more cannot be satisfied. It is difficult to use. For this reason, it is necessary to introduce a completely orthogonal sequence that can be completely zero when correlation is obtained, such as a 4PN sequence (1, -1,1,1). In order to ensure noise immunity in an environment where the S / N is -10 dB, a signal length of at least 10 symbols is required. In this embodiment, a completely orthogonal sequence is selected from 10PN sequences. Create. When the transmission signal point is limited to a binary value of ± 1, there is no complete orthogonal sequence in the 10PN pattern. This is because a perfect orthogonal sequence requires that the result of integral correlation be zero, and as a result, at least one zero point is required.

  As described above, in this embodiment, the peak value of the correlation output is a predetermined value from among the combinations in which the leading signal point is fixed to zero and the remaining 9 subframe patterns are set to ± 1 binary signal points. A combination that is larger and has a correlation output width smaller than a predetermined value (small sample number when sampling) is selected. Furthermore, in the adjacent channel (that is, even channel and odd channel), the time phase is shifted by 180 ° to eliminate interference between adjacent channels. FIG. 50 shows the training signals (optimal training pattern) for even and odd channels.

  Now, a method of timing phase synchronization and carrier phase synchronization in this embodiment using such a training signal will be described. First, timing phase synchronization will be described. The phase of the reception carrier varies greatly depending on the state of the power line, and the carrier phase becomes indefinite on the reception side. Therefore, in the receiving unit, it is necessary to perform carrier phase extraction and timing phase extraction so that stable communication is possible even when the carrier phase is indefinite. 51 shows a configuration of a timing synchronization circuit 180 corresponding to the timing synchronization unit 22 in FIG. 1, wherein 181 is a gain switch and a first automatic gain adjustment circuit (GSW & AGC1), 182 is a correlation filter circuit (PNF), 183 is a power value calculation and nonlinear filter circuit (PWR & NLF), 184 is a demodulation / low pass filter / phase adjustment circuit (DEM & LPF & phase adjustment), 185 is a time axis / frequency axis median filter (FDMF & TDMF), and 186 is a second automatic gain. Adjustment circuits (AGC2) and 187 are secondary PLL circuits.

  The received signal converted into the frequency axis information by the fast Fourier transform unit 21 is subjected to the distortion of the line and is at a different level for each frequency. Therefore, the received signal is input to the gain switch and the first automatic gain adjustment circuit 181. The gain switch relatively suppresses large amplitude tone noise, and the first automatic gain adjustment circuit adjusts the frequency level to a constant level. Then, the correlation filter circuit 182 removes a signal having no correlation with the training signal. At this time, as shown in FIG. 50, since the training signal is set to be orthogonal to each other between the even channel and the odd channel, a signal without adjacent interference is output. Note that large amplitude tone noise is further suppressed by the correlation filter circuit 182. FIG. 52 shows a case where the correlation filter circuit 182 is constituted by a normal transversal filter (FIR).

  The signal output from the correlation filter circuit 182 is a signal that varies depending on the carrier phase. Therefore, in the power value calculation and nonlinear filter circuit 183, the power value calculation circuit calculates the power value of the signal and converts it into phase information that does not change with the carrier phase, and the nonlinear filter circuit removes unnecessary components such as interference between adjacent channels. To do. Here, the non-linear filter circuit extracts the maximum value of the power value output from the power value calculation circuit and the sample values before and after the maximum value (number of samples n), and eliminates unnecessary noise by setting all other values to zero. To do. At this time, if the number n of samples of the non-linear filter circuit is reduced, the S / N improvement amount is increased, but the timing phase information is reduced and the jitter is increased. Therefore, the number of samples n is minimized so as to reduce the jitter amount. It is necessary to select (in this embodiment, the number of samples n is set to 7). Further, in this embodiment, the power value calculation circuit calculates the power values of all the channels and adds them, and then determines a unified non-linear filter, and uses the result in common to apply the non-linear filter circuit. It is composed. As a result, the noise associated with the determination of the nonlinear filter can be minimized and the characteristics can be improved.

  The signal (timing signal) output from the power value calculation and nonlinear filter circuit 183 includes a frequency component of timing (6.25 kHz for a 10PN training signal when the Nyquist clock is 62.5 kHz). Therefore, in order to extract this phase information, the demodulation / low-pass filter / phase adjustment circuit 184 demodulates the timing signal with a carrier having a training length (6.25 Hz) and performs low-pass filter processing. Thereby, the timing phase which is a direct current component is extracted.

  At this time, the transmission side multiplies each transmission signal point by a random phase (fixed value) in order to minimize the PAR of the transmission waveform. Therefore, the demodulated signal is multiplied by a rotation opposite to the random phase rotation on the transmission side. In order to realize orthogonal multiplexing of the transmission signal on the time axis / frequency axis, the imaginary part is shifted by 1/2 Nyquist time length with respect to the real part. For this reason, when the original signal point has a phase angle (an img value that is a component of the imaginary part), the transmission waveform is shifted by a maximum of 1/2 Nyquist time length, so that the timing phase is shifted by that amount on the receiving side. Become. For this reason, on the receiving side, the combined energy of both the real component and the imaginary component of the transmission is extracted. Specifically, the timing phase is obtained by performing vector synthesis of the 0th-order component and the + 1st-order component of the correlation filter.

  FIG. 53 shows a result of simulating the rotation state of the timing phase (TIM phase) on the reception side accompanying the phase rotation on the transmission side. As is apparent from FIG. 53, when the transmission signal point is 0 degrees (real component 100%) and 90 degrees (imaginary component 100%), the reception timing phase is ± 9.0 degrees at the maximum (width is maximum 18). (Degree = 180 degrees / 10 subframes). Actually, since a clipping error occurs due to the power value calculation and the nonlinear filter circuit (seven sample extraction) constituting the nonlinear filter circuit 183, the extracted timing phase is matched with the random phase rotation θ of the transmission. It is necessary to subtract the correction amount Θ (= 8.82 * cos (2θ)). By these processes, the estimation error becomes a maximum of ± 0.30 degrees (error 0.33%).

  Although the received waveform is cut out in the nonlinear filter circuit, the time phase is slightly shifted in the timing phase on the receiving side due to the random phase rotation on the transmitting side. As a result, the extracted waveform accompanying the waveform cutting is obtained. Energy reduction occurs. As a result, a variation in timing amplitude is reduced. As shown in FIG. 54, the amplitude error associated with this clipping depends on the random phase rotation angle on the transmission side and is fixedly determined, and can be corrected on the reception side. As shown in FIG. 54, the amplitude value can be corrected by multiplying the correction curve. In a specific calculation formula for the correction value, if the transmission-side random phase rotation amount is θ (degrees), the correction value A is A = 0.103 * POWER ((sin (2θ)), 2).

  The timing phase extracted by the demodulation / low-pass filter / phase adjustment circuit 184 is added to a desired phase after the non-linear component is removed on the frequency axis / time axis by the time axis / frequency axis median filter 185. This is a timing signal. Here, the time axis / frequency axis median filter 185 includes a filter (FDMF) that takes an average on the frequency axis and a filter (TDMF) that takes an average on the time axis. Then, in order to obtain accurate phase information, the level is normalized by the second automatic gain adjustment circuit 186 and filtered by the secondary PLL circuit 187 to obtain a PLL output having a desired PLL characteristic. A controlled crystal oscillator (DCXO) 34 is controlled.

  FIG. 55 shows the result of the timing phase extracted by the above processing. In the demodulation / low-pass filter / phase adjustment circuit 184, an output waveform (output waveform after DCF) after demodulating with a training length (6.25 Hz) carrier and subjected to low-pass filtering is about 18 degrees in width as a timing phase. Variable components are observed. On the other hand, these are normalized to a single phase after antiphase correction (after antiphase randomness). Further, in the result of integrating these on the frequency axis and the time axis (after FDMF), the noise component is further suppressed, and an accurate timing phase can be extracted.

  Next, carrier phase synchronization will be described. Regarding the above-described timing phase extraction, since the delay characteristic of the power line is about 3 μs at most and the time variation is small, stable extraction by past integration operation is possible. However, with regard to the carrier phase, the phase characteristics of the power line change from moment to moment, so instantaneous reset type phase tracking different from the timing phase is essential. In addition, stable carrier phase extraction in a noisy environment is necessary. 56 shows a main part of the demultiplexing processing unit 13, 191 is a gain switch and a first automatic gain adjustment circuit (GSW & AGC1), 192 is a correlation filter circuit (PNF), 193 is a random phase reverse rotation circuit, and 194 is An inverse number arithmetic circuit, 195 is a complex conjugate circuit, 196 is a real-imaginary (Real Imag) synthesis circuit, 197 is a signal point determination circuit, and 198 is a differential / N / G / descramble circuit (differential N / G DSCR). The gain switch and first automatic gain adjustment circuit 191 to the signal point determination circuit 197 correspond to the signal point determination unit 23 in FIG. 1, and the difference / N / G / descramble circuit 198 has a difference in FIG. This corresponds to the descrambling circuit 25. The gain switch, first automatic gain adjustment circuit 191 and correlation filter circuit 192 are mounted in common with the gain switch, first automatic gain adjustment circuit 181 and correlation filter circuit 182 in the timing phase synchronization circuit 180 described above. It is also possible.

  The received signal converted into the frequency axis information by the fast Fourier transform unit 21 is input to the gain switch and the first automatic gain adjustment circuit 191, and the distortion level of the line and the level different for each frequency are adjusted. As described with reference to FIG. 47, prior to transmission of user data, a training signal is transmitted using all channels. Therefore, with respect to the training signal, the output of the gain switch and the first automatic gain adjustment circuit 191 is input to the correlation filter circuit 192, and the signal not correlated with the training signal and the interference component of the adjacent channel are removed. The random phase reverse rotation circuit 193 restores the data whose phase has been rotated on the transmission side, and the reciprocal calculation circuit 194 extracts the phase of the received carrier and detects the amplitude of the received carrier.

  The phase of the received carrier is extracted using a portion where there is no interference from adjacent channels, that is, a maximum value central portion of the correlation filter output which can maintain the orthogonal relationship. As shown in FIG. 57, on the transmission side, the imaginary part is transmitted with a delay of ½ Nyquist time compared to the real part in order to reduce the PAR of the transmission signal. For this reason, the correlation output at the receiving side is output with a delay of ½ Nyquist time on the imaginary part side compared to the real part side. On the other hand, although it is the carrier phase at this time, in the phase extraction of only the center point of the correlation output and only the 1/2 delay point, the carrier phase rotation occurs due to the reception timing phase information rotation. An accurate carrier phase cannot be extracted. However, since the carrier phase errors at the center point and the 1/2 delay point are in opposite phases as shown in FIG. 58, they can be canceled out by adding both vectors in a stable manner and stable carrier phase. Extraction is possible. Therefore, in order to realize stable extraction of the received carrier phase accompanying the random phase rotation on the transmission side, the reciprocal arithmetic circuit 194 combines the combined vector signal (0th order) of the maximum central portion of the correlation filter output and the 1/2 delay point. The sum of the correlation and the primary correlation) is used for extraction. With such a configuration, the reception carrier phase error can be made zero.

  The amplitude of the received carrier is also detected using a portion where there is no interference from the adjacent channel, that is, the maximum value central portion of the correlation filter output which can maintain the orthogonal relationship. Furthermore, in order to realize the stable extraction of the reception carrier amplitude accompanying the random phase rotation on the transmission side, it is configured to detect using the combined vector signal of the central part of the maximum value of the correlation filter output and the 1/2 delay point. ing. Also in this case, the reception carrier amplitude error can be made zero. The reciprocal arithmetic circuit 194 is configured to calculate and output the reciprocal of the received carrier amplitude.

  On the other hand, for user data, the output of the gain switch and first automatic gain adjustment circuit 191 is input to the complex conjugate circuit 195. As shown in FIG. 59, the complex conjugate circuit 195 normalizes the amplitude of the received signal by multiplying the input signal by the reciprocal value of the phase and amplitude of the received carrier obtained by the reciprocal arithmetic circuit 194. In addition, the carrier phase on the line is normalized to 0 degree. Then, the original transmission signal point is reproduced by the real-imaginary synthesis circuit 196. At this time, the reverse rotation of the random rotation performed on the transmission side is performed. Further, the signal point determination circuit 197 can reproduce the original signal point, and the difference / N / G / descramble circuit 198 can demodulate the original transmission data. In this way, a special training signal is transmitted on the transmitting side, and a reset type PLL is configured and carrier phase synchronization is performed by a short integration operation on the receiving side, thereby improving noise tolerance and stabilizing the carrier phase. Can be realized.

  As described above, by performing the timing phase synchronization and the carrier phase synchronization using the training signal, the multiplex transmission apparatus according to the present embodiment can perform stable information even in a large amplitude noise environment (S / N-70 dB). Extraction may be possible.

In mounting such a multiplex transmission apparatus, the digital unit 1 is mounted on an IC chip. Therefore, in order to manufacture a multiplex transmission apparatus at a low cost, it is important to reduce the amount of calculation and the amount of memory in the processing of the digital unit 1. For example, when the multiplexing processing unit 12 constituting the digital unit 1 shown in FIG. 48 is mounted, when sampling is performed at 32 MHz with a maximum length of 8 subframes and the bit length of one word is 16 bits, the window function The memory amount M in the multiplier circuit 177 is:
M = 16 bits * 512 points
* 8 subframe * 2 (complex number) * 2 words (real / imaginary)
= 32.768 kilobytes. Therefore, if it is mounted on an IC chip as it is, a huge memory area is required, and an inexpensive chip cannot be realized.

  FIG. 60 shows the configuration of the multiplexing processing unit 12 for reducing the chip size of the digital unit 1, and 201 shows a scrambler / G / N / summing circuit (SCR G / N summing). , 202 indicates a front-stage IFFT circuit, and 203 indicates a rear-stage IFFT circuit. The transmission data is input to the scrambler / G / N / summing circuit 201, and is randomized and converted from gray code to natural code (G / N) in the same manner as the processing shown in FIG. The phases are summed and input to the previous IFFT circuit 202. This pre-stage IFFT circuit 202 is configured to perform signal point generation, random phase rotation, real / imaginary separation, 8-point inverse fast Fourier transform, window function calculation, and convolution integration with transmission data (bit information) as the center. Has been. Here, since the number of points of the inverse fast Fourier transform is a reduction in the amount of memory, the batch calculation processing is performed with the bit information before being expanded into signal points as the center of the memory. However, the inverse fast Fourier transform processing is set to the minimum necessary 8 points in order to increase the speed and efficiency of the arithmetic processing. The signal subjected to the 8-point inverse fast Fourier transform processing in the front-stage IFFT circuit 202 is subjected to window function processing, subjected to convolution integration on the time axis, and then input to the rear-stage IFFT circuit 203.

  The post-stage IFFT circuit 203 performs 64-point inverse fast Fourier transform processing on the signal output from the pre-stage IFFT circuit 202, and further performs waveform shaping processing (interpolation filter) on the signal for the purpose of interpolation (interpolation). Window function processing and convolution integration processing) of multiplying the time response waveform of the first time response waveform as a window function to obtain a final desired transmission waveform of 32 MHz sampling.

  In FIG. 61, the front-stage IFFT circuit 202 and the rear-stage IFFT circuit 203 when the number of points of the inverse fast Fourier transform in the front-stage IFFT circuit 202 is changed to 1, 2, 4, 8, 16, 32, 64, 128, 256. The structure of the inverse fast Fourier transform process in is shown. Although the sampling frequency of the pre-stage IFFT circuit 202 changes from 62.5 kHz to 16 MHz as the number of points increases, the amount of memory requires 3.84 kilobytes regardless of the number of points as described above. On the other hand, the post-stage IFFT circuit 203 changes from 512 points to 2 points according to the number of points of the pre-stage IFFT circuit 202 (both are 512 when multiplying the number of points of the pre-stage and the post-stage), and the memory amount is the pre-stage IFFT circuit 203 The number of points increases as the number of points 202 increases (because the time length decreases as the sampling frequency increases and the amount of memory decreases).

  In the present embodiment, as described above, the filter unit in the multiplexing processing unit 12 is divided into two types: a basic waveform shaping unit (pre-stage IFFT circuit 202) and an interpolator unit (post-stage IFFT circuit 203). Realized. The basic waveform shaping unit performs essentially necessary waveform shaping processing, but in order to minimize the amount of memory, it is necessary to realize the sampling speed as low as possible. However, it is necessary that the sampling rate at the front stage does not cause spectrum folding and that sufficient interpolation can be realized after the inverse fast Fourier transform processing at the rear stage. In FIG. 61, whether or not interpolation is possible indicates whether or not interpolation can be realized by the post-stage IFFT circuit 203, and cannot be realized when the number of points in the previous stage is one or two. Further, in the waveform shaping process in the pre-stage IFFT circuit 202, if the number of points is small, the multiplication process is unnecessary or a light multiplication process can be performed. Therefore, the simple selector can be used to simplify the process. Whether or not can be used indicates whether or not this simple selector can be used.

  In this embodiment, interpolation can be realized in the subsequent processing, and a simple selector can be used. Therefore, the inverse fast Fourier transform of 8 points in the previous stage (sampling frequency is 500 kHz) and 64 points in the subsequent stage (sampling frequency is 32 MHz). It is configured to be realized by processing. As a result, the combined memory amount of the former stage and the latter stage can be realized with 5.888 kilobytes (the memory amount can be about 18% as compared with the configuration of FIG. 48 described above).

  62 shows the configuration of the pre-stage IFFT circuit 202, where 211 is a serial / parallel conversion circuit (S / P), 210 is a waveform shaping unit, and in this waveform shaping unit 210, 212 is a maximum of 10 bits. , 213 is a signal point generating ROM, 215 is a filter coefficient ROM, 216 is a real part multiplier circuit, and 217 is a 1/2 Nyquist delay circuit (T / 2). Reference numeral 218 denotes an imaginary part multiplication circuit, 219 denotes a convolution integration circuit (Σ), 220 denotes a random phase rotation circuit, 221 denotes a real part addition circuit (Σ), and 222 denotes an imaginary part addition circuit (Σ). 62, the summing circuit is omitted because the phase and amplitude of the transmission data are matched by the training signal as described above. In addition, the G / N conversion circuit is also omitted because processing is performed with an absolute phase.

Transmission data converted into parallel data by the serial / parallel conversion circuit 211 is input to the tap delay line 212 and one of 10 bits (in the case of 10-bit / Hz transmission) output from the selector 213 is selected. Are input to the signal point generation ROM 214 and corresponding signal points (real part x and imaginary part y) are generated. On the other hand, the phase signal of the sampling counter is input to the filter coefficient ROM 215, and the filter coefficient is output from the filter coefficient ROM 215 corresponding to the phase signal. At this time, the real part of the transmission baseband signal output from the waveform shaping unit 210 is X, the imaginary part is Y, the signal point after the convolution integrator 219 is x + jy, and the rotation amount of the random phase rotation is cos + jsin. Then
X + jY = (x + ji) (cos + jsin)
= (Xcos-ysin) + j (ycos + xsin)
It is expressed.

  Therefore, the filter coefficient output from the filter coefficient ROM 215 is multiplied by the real part x and the imaginary part y of the signal point by the real part multiplication circuit 216 as it is, and is subjected to convolution integration by the convolution integration circuit 219 to obtain a random phase. In the rotation circuit 220, the real part is multiplied by cos, the imaginary part is multiplied by -sin, and each is added by the real part addition circuit 221 to become the real part X of the basic transmission baseband signal, while 1/2 Nyquist The filter coefficient delayed by a ½ Nyquist time length by the delay circuit 217 is multiplied by the imaginary part multiplication circuit 218 by the real part x and the imaginary part y of the signal point, and the convolution integration is performed by the convolution integration circuit 219. Real part with random phase rotation circuit 220 in is multiplied is multiplied cos within imaginary part, respectively is added in imaginary part adder circuit 222 becomes imaginary part Y of the basic transmission baseband signal.

As described above, when the waveform shaping unit 210 of the multiplexing processing unit is configured as described above, the data extracted from the tap delay line 212 by the selector 213 is converted into a basic transmission baseband signal without requiring a memory. The Therefore, the memory amount M ′ required for the pre-stage IFFT circuit 202 is 8 subframes of 10 bits (in the case of 10 bits / Hz transmission) required by the tap delay line 210, and is realized by 384 channels. Is
Since M ′ = 10 bits * 8 subframes * 384 channels = 3.84 kilobytes, it can be 1/8 of the conventional memory amount M described above.

  As shown in FIG. 62, when the signal point is 1 bit, scrambler processing, G / N conversion processing, summation processing, signal point generation processing, ROF modulation, and D / A conversion processing are performed in the ROM. Since the method to be executed in this is described in detail in Japanese Patent Application Laid-Open No. 08-116347, description thereof is omitted here.

  By the way, as shown in FIG. 63, the band allowed by the interpolation (LPF) in the post-stage IFFT circuit 203 has a predetermined bandwidth with respect to the basic transmission baseband signal output from the pre-stage IFFT circuit 202. Therefore, if a plurality of channels are multiplexed as much as possible in the preceding process, the processing amount in the succeeding stage can be reduced. Therefore, as shown in FIG. 64, for each of the basic transmission baseband signals (X + jY) output from a plurality of waveform shaping units 210 (k waveform shaping units 210 in the case of FIG. 64), a rotation circuit unit. Rotate at 223 (multiply by Ejθ1, Ejθ2,..., Ejθk) and shift the frequency, and then synthesize a signal of a plurality of channels at the synthesis circuit (Σ) 224 and then input it to the subsequent IFFT circuit 203. It is preferable to configure. FIG. 63 shows a case where three basic transmission baseband signals are output.

  FIG. 65 shows a more detailed configuration of the multiplexing processing unit 12 in FIG. 60, in which 201 denotes a scrambler circuit (SCR), 202 denotes a front-stage IFFT circuit, 203 denotes a rear-stage IFFT circuit, and the front-stage IFFT In the circuit 202, 211 denotes a serial / parallel conversion circuit (S / P), 210 ′ denotes a waveform shaping unit, and in the subsequent IFFT circuit 203, 225 denotes an inverse fast Fourier transform unit (IFFT), 226 denotes a rotation circuit unit, 227 Indicates a waveform synthesis unit (Σ), and 228 indicates an interpolation (IPL) unit. 63 is configured to have as many waveform shaping units as the number of channels, and has the waveform shaping unit 210 shown in FIG. 62 for each channel, or as shown in FIG. It is configured to output a composite of the waveforms of a plurality of channels by frequency shifting. Note that the memory amount in this case is 80 bits / channel at the maximum in the case of 10-bit / Hz transmission as described above.

  In FIG. 65, transmission data is randomized by the scrambler circuit 201 and then converted into parallel data by the serial / parallel conversion circuit 202. Then, each of a plurality of waveform shaping units constituting the waveform shaping unit 210 ′ is converted into a basic transmission baseband signal and input to the inverse fast Fourier transform unit 225. The inverse fast Fourier transform unit 225 includes a plurality of inverse fast Fourier transform circuits (in the case of FIG. 63, composed of two 225a and 225b), and the basic transmission output from the waveform shaping unit 210 ′. Of the baseband signal, a plurality of channels are collected and input to the respective inverse fast Fourier transform circuits 225a and 225b. The signal after the inverse Fast Fourier Transform is multiplied by the frequency between adjacent channels by the rotation circuit unit 226, frequency-shifted, added by the waveform synthesis circuit 227, and then interpolated by the interpolation unit 228. Window function multiplication and convolution integration are performed, and a desired transmission baseband signal can be finally obtained.

  As described above, in the multiplexing processing unit 12, the first stage IFFT circuit 202 is subjected to 8-point inverse fast Fourier transform and the sampling frequency is set to 500 kHz, and the second stage subsequent IFFT circuit 203 is configured to be 64-point inverse fast Fourier transform. By setting the sampling frequency to 32 MHz as the conversion, the final memory amount can be reduced to about 1 / 5.5. As shown in FIG. 61, the first stage inverse fast Fourier transform is 16 points, and the second stage inverse fast Fourier transform is 32 points, thereby reducing the memory amount to 1 / 6.7. In this case, however, increasing the number of points in the first-stage inverse fast Fourier transform increases the amount of computation in the first stage.

  Next, a method for reducing the chip size of the demultiplexing processing unit 13 of the digital unit 1 will be described. FIG. 66 shows a main part of the demultiplexing processing unit. 230 is a demodulation circuit (DEM), 231 is a decimation circuit (DCM), 232 is a window function multiplication and convolution integration circuit, and 233 is a fast Fourier transform circuit (FFT). ). 66, the demodulation circuit 230 and the decimation circuit 231 correspond to the demodulation and nonlinear filter unit 20 of FIG. 1, and the window function multiplication and convolution integration circuit 232 and the fast Fourier transform circuit 233 are added to the fast Fourier transform unit 21 in FIG. Correspond.

  The reception signal output from the analog unit 2 is demodulated into a baseband signal by the demodulation circuit 230, and then the unnecessary band is removed by the decimation circuit 231 and the sampling frequency is minimized. Further, the received signal is multiplied by a window function coefficient in the window function multiplication and convolution integration circuit 232, convolution integration is performed in units of fast Fourier transform, and then converted into a frequency axis signal by the fast Fourier transform circuit 233. .

  Here, in order to simplify the explanation, the processing of the conventional circuit and the circuit in the present embodiment will be described with reference to FIGS. 67 and 68, taking as an example the case of executing 3 sub-fast Fourier transforms in 3 subframes. To do. FIG. 67 shows the process of the conventional demultiplexing processing unit 13, and each reception signal is multiplied by the reception window function (step S10). These multiplication results are fast Fourier transformed, and each received signal is multiplied by a rotator and then added for each subframe (step S20). Then, the Fourier transform results of the three subframes are added (step S30), and the final fast Fourier transform result can be obtained by the Σ equivalent calculation (step S40).

  On the other hand, according to the method of this embodiment shown in FIG. 66, as shown in FIG. 68, each received signal is multiplied by the reception window function (step S1), and the result is convolved and integrated. The result for each frame is output (step S2). Then, a final fast Fourier transform result can be obtained by performing a Fourier transform on the result of the convolution integration (step S3). That is, since the fast Fourier transform process is only required once compared to the conventional case, the processing amount can be greatly reduced. For example, when a 512-point fast Fourier transform is performed on 6 subframes, the processing amount can be reduced to about 1/10.

  As described above, the chip size of the digital unit 1 can be reduced by reducing the memory amount in the multiplexing processing unit 12 and the processing amount in the demultiplexing processing unit 13. The cost of the apparatus can be reduced.

  In the above description, the case where the multiplex transmission apparatus according to the present invention is applied to a power line carrier system is shown, but the present invention is not limited to this embodiment, and can be applied to all communications. it can.

It is explanatory drawing which shows the structure of the multiplex transmission apparatus which concerns on this invention. It is principal part explanatory drawing of the said multiplex transmission apparatus. It is explanatory drawing of the time response waveform of a transmission line. It is waveform explanatory drawing of Nyquist transmission. It is frequency characteristic explanatory drawing of a Nyquist transmission line. It is image explanatory drawing of orthogonal frequency division multiplexing. It is time response waveform explanatory drawing of a transmission / reception filter. It is time response waveform explanatory drawing of a cos filter. It is time response waveform explanatory drawing of a cos square filter. It is interference explanatory drawing between adjacent channels. It is a figure explaining the interference between adjacent channels, Comprising: It is interference explanatory drawing when transmitting 0 times in CH0 and receiving 0 times in CH0. It is a figure explaining the interference between adjacent channels, Comprising: It is interference explanatory drawing when transmitting 0 times in CH1, and receiving 0 times in CH0. It is a figure explaining interference between adjacent channels, Comprising: It is interference explanatory drawing when transmitting 90 degree | times in CH1, and receiving 0 degree | times in CH0. It is a figure explaining the interference between adjacent channels, Comprising: It is an interference explanatory drawing when transmitting 45 degrees in CH1, and receiving 0 degrees in CH0. It is explanatory drawing of a transmission modulation part. It is waveform explanatory drawing of a transmission modulation part. It is explanatory drawing of a transmission IFFT part. It is function explanatory drawing of a transmission IFFT part. It is principal part explanatory drawing of the transmission side. It is principal part explanatory drawing on the receiving side. It is explanatory drawing of a reception FFT part. It is function explanatory drawing of a reception FFT part. It is explanatory drawing of transmission efficiency. It is explanatory drawing of specific band leak reduction. It is explanatory drawing of noise suppression. It is explanatory drawing of the interference removal between adjacent channels. It is explanatory drawing of a low-pass filter. It is explanatory drawing of a modulation | alteration part. It is explanatory drawing of a demodulation part. It is filter characteristic explanatory drawing in the case of no window function. It is explanatory drawing of a window function and a filter coefficient. It is filter characteristic explanatory drawing in the case of window function multiplication. It is principal part explanatory drawing on the transmission / reception side to which the noise cancellation means is applied. It is principal part explanatory drawing of the transmission / reception side to which the multipath countermeasure is applied. It is principal part explanatory drawing of the transmission / reception side to which timing phase adjustment is applied. It is principal part explanatory drawing of the transmission / reception side to which error correction is applied. It is explanatory drawing of the frequency spreading | diffusion on the transmission side. It is explanatory drawing of the frequency spreading | diffusion on the receiving side. It is principal part explanatory drawing of the multiplex transmission apparatus which concerns on this invention when a signal point is divided | segmented into an even-numbered channel and an odd-numbered channel. It is principal part explanatory drawing of a synchronization means. It is explanatory drawing of a 20Hz synchronous signal detection circuit. It is explanatory drawing which shows the relationship between a power supply frequency and a time window. It is explanatory drawing of a master station side PLL circuit. It is explanatory drawing of the master station time slot selection circuit. It is explanatory drawing of a slave station side PLL circuit. It is explanatory drawing of a slave station side time slot selection circuit. It is explanatory drawing which shows the relationship between a training signal and user data. It is principal part explanatory drawing of the transmission side to which peak leak reduction is applied. It is explanatory drawing which shows a peak leakage reduction effect. It is explanatory drawing which shows an optimal training pattern (10PN). It is explanatory drawing of a timing phase synchronizing circuit. It is explanatory drawing of a nonlinear filter circuit. It is explanatory drawing which shows the change of the reception timing phase by transmission random phase rotation. It is explanatory drawing which shows the amplitude information correction result of a timing phase. It is explanatory drawing which shows a receiving side timing phase extraction result. It is explanatory drawing of a carrier phase synchronizing circuit. It is explanatory drawing which shows a reception correlation output. It is explanatory drawing which shows a carrier phase difference characteristic. It is explanatory drawing of a complex conjugate circuit. It is principal part explanatory drawing of the transmission side which reduced chip size. It is explanatory drawing which compared the structure of the front | former stage and back | latter stage IFFT circuits. It is principal part explanatory drawing of a front | former stage IFFT circuit. It is explanatory drawing which shows the relationship between a transmission baseband signal and an interpolation filter. It is principal part explanatory drawing of the front | former IFFT circuit which used multiple waveform shaping parts. It is principal part explanatory drawing of the transmission side. It is principal part explanatory drawing of the receiving side which reduced chip size. It is explanatory drawing which shows the process of the conventional receiving side. It is explanatory drawing which shows the process of the receiving side based on this invention employ | adopted in order to reduce chip size.

Explanation of symbols

39 High precision clock oscillation circuit (High precision clock oscillation means)
40 First frequency dividing circuit (first frequency dividing means)
120 20 Hz synchronization signal detection circuit (synchronization signal detection means)
131 Phase advance / delay determination circuit (second PLL means)
132 First integration circuit (second PLL means)
133 Second integration circuit (second PLL means)
134 Second frequency dividing circuit (second frequency dividing means)
150 Slave station side PLL circuit (synchronizer)
151 Specific signal timing phase extraction circuit (timing phase extraction means)
152 Specific signal detection circuit (timing phase extraction means)
153 Phase advance / delay determination circuit (first PLL means)
154 First integration circuit (first PLL means)
155 Second integration circuit (first PLL means)
160 Slave station time slot selection circuit (time slot selection means)
200 First PLL means 300 Second PLL means

Claims (14)

In a synchronization device that has a first PLL means that synchronizes with a first synchronization signal and a second PLL means that synchronizes with a second synchronization signal, and synchronizes with the two synchronization signals,
The second PLL means establishes synchronization with the two different synchronization signals by establishing synchronization using the output signal of the first PLL means as a synchronous quantization unit of the second PLL means. Synchronizing device characterized. A synchronization device that is provided in a transmission device connected to a transmission medium and performs communication, and synchronizes a high-accuracy clock signal between the transmission devices,
High-accuracy clock oscillation means for outputting the high-accuracy clock signal;
First frequency dividing means for frequency-dividing the high-accuracy clock signal and outputting a first synchronization signal;
Timing phase extraction means for receiving a specific signal transmitted from a predetermined transmission device and extracting a timing phase of the specific signal;
The timing phase and the first synchronization signal are compared to determine the phase advance / delay, and the high-accuracy clock oscillation means is controlled to synchronize the first synchronization signal with the predetermined transmission device. PLL means,
Synchronization signal detection means for detecting a frequency of a signal flowing in the transmission medium and outputting a second synchronization signal;
Second frequency dividing means for dividing the first synchronization signal and outputting a second estimated synchronization signal;
The second synchronization signal and the second estimated synchronization signal are compared to determine the phase advance / delay, and the second frequency dividing means is controlled to quantize the first synchronization signal. And a second PLL means for outputting the synchronized second estimated synchronization signal. A time slot selecting means for selecting a time slot selected by the predetermined transmission device based on the second estimated synchronization signal;
The synchronization according to claim 2, wherein the first PLL means is configured to control the high-accuracy clock oscillation means using a timing phase of the specific signal in the time slot selected by the time slot selecting means. apparatus. The transmission medium is a power line;
The synchronization device according to any one of claims 1 to 3, wherein a time phase of a signal flowing through the transmission medium is synchronized with a power supply frequency. The synchronization signal detecting means is
Zero cross point detection means for detecting a point at which the voltage value of the power flowing through the power line becomes zero
5. The synchronization device according to claim 4, wherein the second synchronization signal is generated by counting points where the voltage value detected by the zero-crossing point detection unit becomes zero. 6. The synchronization signal detecting means is
A time window setting means for setting a time window by counting the points at which the voltage value detected by the zero cross point detection means becomes zero,
The said specific signal transmitted from the said predetermined transmission apparatus is detected in the said time window set by the said time window setting means, It is comprised so that the said 2nd synchronizing signal may be generated. Synchronizer.   The synchronization device according to any one of claims 3 to 6, wherein the transmission device is configured to perform communication using a time division multiple access method. In a synchronization method that has a first PLL means that synchronizes with a first synchronization signal and a second PLL means that synchronizes with a second synchronization signal, and synchronizes with the two synchronization signals,
The second PLL means establishes synchronization with the two different synchronization signals by establishing synchronization using the output signal of the first PLL means as a synchronous quantization unit of the second PLL means. A featured synchronization method. In a transmission method for communicating by being connected to a transmission medium, a synchronization method for synchronizing a high-precision clock signal,
The transmission method includes a first synchronization signal generated by dividing the high-accuracy clock signal, and a second synchronization signal generated from the frequency of the signal flowing through the transmission medium,
A timing phase is detected from a specific signal transmitted by a predetermined transmission method, and a high-accuracy clock oscillating means for outputting the high-accuracy clock signal from the timing phase is controlled, whereby the first synchronization signal is converted into the specific signal. In sync with
The first synchronization signal is divided to generate a second estimated synchronization signal, and the second synchronization signal is used as the second estimated synchronization signal with the first synchronization signal as a quantization unit. Synchronization method to synchronize.   The time slot is selected based on the second estimated synchronization signal, and the first synchronization signal is synchronized with the predetermined transmission device using a timing phase of the specific signal in the time slot. The synchronization method described in. The transmission medium is a power line;
The synchronization method according to claim 9 or 10, wherein a time phase of a signal flowing through the transmission medium is synchronized with a power supply frequency.   The synchronization method according to claim 11, wherein the second synchronization signal is generated by counting a point at which a voltage value of power flowing through the power line becomes zero. The second synchronization signal counts the point where the voltage value of the power flowing through the power line becomes zero, and sets the time window,
The synchronization method according to claim 11, wherein the synchronization signal is generated by detecting the specific signal transmitted from the predetermined transmission device in the time window.   The synchronization method according to any one of claims 9 to 13, wherein the transmission device is configured to communicate by a time division multiple access method.

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