JP2007324540A - MOS type semiconductor device and manufacturing method thereof - Google Patents

Abstract

[Objective] Even without adopting a trench gate structure, the trade-off relationship between on-state voltage and turn-off loss is further improved, and excessive polishing and over-polishing are prevented to suppress variation in on-voltage and to improve gate characteristics. To provide a MOS type semiconductor device having a gate structure.
[Structure] A first insulating film having a first opening on a surface of a one-conductivity type semiconductor substrate, a substrate insulating film provided in the first opening and being thinner than the first insulating film, and a substrate insulating film A top gate structure comprising: a second opening provided; and a one-conductivity-type deposited semiconductor layer stacked on the substrate insulating film and having a thickness similar to that of the first insulating film in the first opening. The MOS type semiconductor device is a MOS type semiconductor device in which the interval between the first insulating films sandwiching the first opening is 25 μm or less.
[Selection] Figure 1

Description

  The present invention relates to a MOS type semiconductor device and a manufacturing method thereof, and more particularly to a power MOS type semiconductor device constituting an IGBT (Insulated Gate Bipolar Transistor) and a manufacturing method thereof.

  With respect to an IGBT which is a kind of MOS type semiconductor device according to the present invention, the performance has been improved by many improvements so far. Here, the performance of the IGBT means that the voltage is maintained and the current is completely cut off at the time of off, and the current can flow with the smallest possible voltage drop, that is, a small on resistance at the time of on, and the power loss is small. It is the performance as a switching device. In view of the essence of the operation of the IGBT, in this specification, the collector may be referred to as “anode” and the emitter may be referred to as “cathode”. Below, the characteristic etc. of IGBT are demonstrated.

(About IGBT performance trade-off)
There is a trade-off relationship (so-called trade-off relationship) between the maximum voltage that can be held by the IGBT, that is, the magnitude of the withstand voltage and the voltage drop at the time of ON, and the higher the withstand voltage IGBT, the higher the on-voltage. Ultimately, the limit value of this trade-off relationship is determined by the physical properties of silicon. However, in order to improve the performance of the IGBT to the limit determined by the physical properties of the silicon within the range of this trade-off relationship, it is necessary to prevent the local electric field concentration inside the device when applying the voltage to the IGBT. Ingenuity is necessary.

  As another important index representing the performance of the IGBT, there is a trade-off relationship between on-voltage and switching loss (particularly, turn-off loss). Since the IGBT is a switching device, it operates from on to off or off to on. A large loss per unit time occurs during the transition period of the switching operation. In general, an IGBT having a lower on-voltage has a slower turn-off, and therefore a turn-off loss increases. If the turn-off loss is reduced, the ON voltage increases. These are also trade-off relationships. By improving such a trade-off relationship, the performance of the IGBT can be further improved.

(Improvement of raid-off)
In order to optimize the trade-off relationship between the on-state voltage and the turn-off loss, it is effective to optimize the excess carrier distribution in the on state of the IGBT. In order to lower the on-voltage, the resistance value of the drift layer may be decreased by increasing the excess carrier amount in the drift layer. However, in order to complete the turn-off, all of the excess carriers must be swept out of the device or annihilated by electron-hole recombination. Therefore, a large number of excess carriers increases the turn-off loss. Therefore, in order to optimize this trade-off relationship, the turn-off loss may be minimized with the same on-voltage.

  To achieve the optimal trade-off relationship, the conclusion is that the carrier concentration on the anode side and the cathode side is reduced by lowering the carrier concentration on the anode side in the drift layer and increasing the carrier concentration on the cathode side. The ratio may be about 1: 5. Furthermore, the average carrier concentration in the drift layer may be increased by keeping the carrier lifetime in the drift layer as large as possible.

  The reason will be explained. When the IGBT is turned off, the depletion layer extends from the cathode-side pn junction into the n-type drift layer and progresses toward the anode layer on the back surface. At that time, of the excess carriers in the n-type drift layer, holes are extracted from the end of the depletion layer by the electric field. In this way, an electron excess state occurs, and surplus electrons pass through the neutral region and are injected into the p-type anode layer. Then, since the anode side pn junction is slightly forward-biased, holes are reversely injected according to the injected electrons. The reversely injected holes merge with the holes extracted by the electric field described above and enter the depletion layer.

  Since carriers (here, holes) that are charge carriers pass through the electric field region and escape to the cathode side, the electric field works on the carriers. The work that the carriers receive from the electric field eventually becomes lattice vibration due to collision with a crystal lattice such as silicon and dissipates as heat. This dissipating energy becomes a turn-off loss. By the way, the energy dissipated by the carriers extracted before the depletion layer is fully extended is smaller than the energy dissipated by the carriers extracted when the depletion layer is fully extended. This is because if the depletion layer is not fully extended, the potential difference when carriers pass through the depletion layer is small, so that the work received from the electric field of the depletion layer is small.

  This can be explained from the micro viewpoint of carrier movement in the device. From a macro viewpoint of the terminal voltage of the device, the current that flows before the anode-cathode voltage rises, that is, the current that flows during the rise, is the product of the voltage and current ( This means that the contribution to the loss expressed by (voltage × current) is small. From the above, the carrier distribution biased to the cathode side due to the IE effect described later turns off more than the carrier distribution of anode side bias under the condition that the proportion of carriers extracted at a low voltage is large and the on-voltage is the same. It can be seen that the loss is small.

  As a method of reducing the carrier concentration on the anode side, it is a practical method to reduce the total impurity amount of the anode layer. However, since a substrate with a high impurity concentration cannot be used to reduce the total amount of impurities in the anode layer, an IGBT with a low rated breakdown voltage such as 600 V has a thickness of about 100 μm or less during the manufacturing process. However, there is a problem that it is difficult in terms of production technology. On the other hand, the mechanism for increasing the carrier concentration on the cathode side is called the IE effect. This will be described below.

  As a cathode structure having a large IE effect, a HiGT structure in which a high-concentration n layer is inserted so as to surround a p base of a planar structure has been proposed (see, for example, Patent Document 1 and Patent Document 2). Further, in the trench gate structure, a CSTBT structure in which an n layer having a higher concentration than the drift layer is inserted in a mesa between adjacent trenches, an IEGT (Injection Enhancement Gate Transistor) structure, and the like have been proposed (for example, patents). Reference 3 and Non-Patent Document 1). In general, the IE effect in the trench type is larger than the IE effect in the planar type.

(IE effect)
The essence of the IE effect has been discussed and has already been reported (for example, see Non-Patent Document 2). An IGBT equivalent circuit that is often drawn is a combination of a MOSFET (insulated gate field effect transistor having a metal-oxide-semiconductor structure) and a bipolar transistor. However, considering the actual device operation, it is considered to be a combination of MOSFET 100, pnp bipolar transistor 200, and pin diode 300 as in the equivalent circuit shown in FIG.

FIG. 13 is a cross-sectional view of the semiconductor substrate showing the configuration of the main part of the planar IGBT. In FIG. 13, reference numeral 50 denotes a pin diode region, and reference numeral 60 denotes a pnp bipolar transistor region (hereinafter referred to as a pnp-BJT region). In FIG. 13, the solid line arrow represents the flow of the electron current, and the chain line arrow represents the flow of the hole current.
As shown in FIG. 13, electrons are transferred from the n ⁺⁺ emitter region 46 formed in the p base region on the surface in the pnp-BJT region 60 to the surface of the n ⁻ drift layer 48 along the substrate surface. The surface of the p base region 47 sandwiched between the layers enters the surface of the n ⁻ drift layer 48 through the n inversion layer 45 formed when the gate threshold voltage is applied, and passes through the n ⁺ electron storage layer 42 formed there. As shown by the solid line arrows, the air flows toward the p anode layer 49 on the back surface. A part of this electron current flows as shown by a solid line arrow parallel to the substrate surface and becomes the base current of the pnp-BJT region 60. In the pnp-BJT region 60, holes that have moved from the p anode layer 49 due to diffusion or drift are only collected in the p base layer 47, and the pn junction 44 is slightly reverse-biased. Therefore, the concentration of minority carriers, that is, holes in the n ⁻ drift layer 48 near the pn junction 44 is extremely low.

On the other hand, the cathode of the pin diode region 50 is the n ⁺ electron storage layer 42 on the surface of the n ⁻ drift layer 48. Since the junction 43 (hereinafter abbreviated as n ⁺ / n ⁻ junction) 43 between the n ⁺ electron storage layer 42 and the n ⁻ drift layer 48 is slightly forward-biased, electrons are injected into the n ⁻ drift layer 48. Is done. When the current is large, the electron concentration is much higher than the doping concentration of the n ⁻ drift layer 48 (high injection state). In order to satisfy the charge neutrality condition, holes having the same concentration as the electrons also exist. Therefore, the concentration of minority carriers, that is, holes in the n ⁻ drift layer 48 near the n ⁺ / n ⁻ junction 43 is extremely high.

In the IGBT, it is important to reduce the pnp-BJT region 60 and increase the pin diode region 50 in order to realize the optimum carrier distribution with cathode side bias. It is very important to increase the forward bias amount of the n ⁺ / n ⁻ junction 43 to promote electron injection. In the structure having the IE effect proposed so far, the forward bias of the n ⁺ / n ⁻ junction 43 is increased at the same time as the ratio of the pin diode region is increased.

By the way, in the planar structure IGBT, when the ratio of the p base in the cell pitch is reduced, the on-voltage is reduced. The reason is that the forward bias of the n ⁺ / n ⁻ junction is increased by increasing the lateral current density near the surface and increasing the voltage drop in addition to the increased ratio of the pin diode region. It is explained that the effect of increasing is great. From a different viewpoint, the forward bias of the n ⁺ / n ⁻ junction increases because the n ⁺ electron storage layer has a low resistance, so that its potential is almost equal to the cathode potential, but the n ⁻ drift layer has a high resistance. Therefore, it can be said that the potential is lifted by a voltage drop due to a large current.

Similarly, in a trench structure IGBT, the IE effect can be enhanced by reducing the ratio of the pnp-BJT region. In order to reduce the ratio of the pnp-BJT region, for example, in some mesa portions (semiconductor region between both trenches), the p-type base region may be in a floating state with respect to the potential. The IE effect can also be increased by deepening the trench and separating the bottom of the trench from the pn junction. Further, the IE effect is increased by reducing the width of the mesa portion. In any case, it is considered that the density of the hole current flowing through the mesa portion is increased, and the forward bias of the n ⁺ / n ⁻ junction due to the voltage drop is increased.

Here, when the doping concentration of the drift layer is Nd and the forward bias applied to the n ⁺ / n ⁻ junction is Vn, the electron concentration n on the n ⁻ layer side of the n ⁺ / n ⁻ junction is expressed by the following equation: . However, k is a Boltzmann constant and T is an absolute temperature.

[Equation 1]
n = Nd exp (Vn / kT)
As is apparent from the above equation, the electron concentration n on the cathode side increases exponentially according to the forward bias applied to the n ⁺ / n ⁻ junction. As means for increasing the forward bias amount, there is one that uses a voltage drop due to a large current as described above. Further, as described in Patent Documents 1 to 3, the forward bias amount can be increased by increasing the n-type impurity concentration. However, since the HiGT structure described in Patent Document 1 is a planar structure, if the n-type impurity concentration of the n ⁺ buffer layer on the surface side is too high, there is a problem that the forward breakdown voltage is greatly reduced.

On the other hand, in the CSTBT structure described in Patent Document 3, the n ⁺ buffer layer on the surface side is sandwiched between trench gate oxide films, and continues to the polysilicon potential via the gate oxide film. Therefore, when a forward voltage holding, that is, when the blocking mode, n ⁺ buffer layer on the surface side, not only the pn junction, so depleted from the boundary between the both sides of the trench gate oxide film, fully depleted at a lower forward bias Turn into. Therefore, the electric field inside the n ⁺ buffer layer on the surface side is relaxed despite the high concentration. Even if the forward bias is further increased, a local peak electric field is unlikely to appear due to the relaxation of the electric field at the mesa between the trenches.

This is a vertical parallel pn structure in which a vertical layered n-type region and a vertical layered p-type region with increased impurity concentration are alternately and repeatedly joined instead of a drift layer composed of a uniform and single conductivity type layer. This is also in accordance with the principle of a MOSFET having a super junction structure provided with a drift portion (the vertical shape is a direction perpendicular to the main surface of the substrate).
As described above, the CSTBT structure has a characteristic that the forward breakdown voltage is hardly lowered while enhancing the IE effect. The reason is that the n ⁺ buffer layer on the surface side creates a diffusion potential with the n ⁻ drift layer and becomes a potential barrier for the holes, so that the hole concentration in the drift layer increases (first Description). Another explanation (second explanation) is that electrons are injected from the n ⁺ buffer layer because the n ⁺ buffer layer and the n ⁻ layer on the surface side are forward-biased. .

That is, in the second description, in the n ⁺ / n ⁻ junction, if the n ⁺ buffer layer has a high concentration, the electron injection efficiency is improved, so that the n ⁻ layer with respect to the hole current entering the n ⁺ buffer layer is improved. The ratio of the electron current injected into is increased. In order for holes to diffuse and flow as minority carriers in the n ⁺ buffer layer, the n ⁺ / n ⁻ junction needs to be forward biased. The higher the n ⁺ buffer layer concentration, the smaller the hole concentration as minority carriers in the thermal equilibrium state. Therefore, a higher forward bias amount is required to flow the same hole current. If the forward bias amount is large, the electron current flowing into the n ⁻ layer increases, so that the electron concentration increases. This second explanation is physically a paraphrase of the first explanation.

As described above, it is preferable that the conventional IGBT also has a device structure that has a carrier distribution biased toward the cathode due to the IE effect in order to optimize the trade-off between on-voltage and turn-off loss. Various structures have been announced.
JP 2003-347549 A Japanese translation of PCT publication No. 2002-532885 JP-A-8-316479 Eye. Omura (I. Omura) and three others, "Carrier injection enhancement effect of high voltage MOS devices-Devices physics and design concept-Devices physics and design concept" , P. 217-220 Florin Udrea, 1 other, "A unified analytic model for the carrier dynamics in trench insulated gate bipolar transistors (TIGBT) ISPSD '95, p. 190-195

  However, optimization of the trade-off relationship between the on-voltage and the turn-off loss by the above-described known structure is not necessarily sufficient, and it is considered that the cathode carrier concentration in the on-state can be further increased. In other words, it cannot be said that the IE effect is still sufficiently exerted in a conventional MOS gate type semiconductor device such as an IGBT. For example, even if a trench gate structure such as the above-mentioned CSTBT structure or IEGT structure is used, the trade-off characteristic is improved as compared with the previous one, but there is still room for further improvement of the characteristic. Is that there is.

  On the other hand, the manufacturing process of the trench gate structure MOS type semiconductor device shows a certain trade-off improvement effect as described above, but is longer and complicated because of the trench formation process than the planar structure manufacturing process. Are also miniaturized. Therefore, even though the yield rate is low and the product cost tends to be high, the cell pattern is further miniaturized and the manufacturing cost is further increased if the characteristics are further improved, even if the characteristics are improved. . Therefore, it is possible for the MOS type semiconductor device to improve the trade-off even if the manufacturing process is not complicated and the cell pattern is not miniaturized or the trench gate structure is not adopted. The most preferable from the viewpoint of product cost. In addition to the above problems, the MOS type semiconductor device having a trench gate structure has a problem that an electric field is likely to be concentrated on the bottom of the trench, a breakdown voltage is liable to be lowered, and a trade-off between on-voltage and breakdown voltage is particularly likely to be deteriorated. Furthermore, the structure has a problem that when the gate is set to a negative potential with respect to the cathode, the electric field strength at the bottom of the trench increases and the breakdown voltage tends to decrease.

  The present invention has been made in view of the above-described problems, and an object of the present invention is a top gate structure that further improves the trade-off relationship between on-voltage and turn-off loss without adopting a trench gate structure. In order to obtain a MOS type semiconductor device having a top gate structure, it is possible to prevent excessive polishing and excessive polishing during formation of the epitaxial silicon layer constituting the top gate structure, thereby suppressing on-voltage variations, and to reduce the surface roughness of the polished epitaxial silicon layer. An object of the present invention is to provide a MOS semiconductor device having a top gate structure that is small and has good gate characteristics.

According to the first aspect of the present invention, the first insulating film having the first opening on the surface of the one-conductivity-type semiconductor substrate, and the first insulating film provided in the first opening, A substrate insulating film that is a thin film, a second opening provided in the substrate insulating film, and a layer on the substrate insulating film that is approximately the same thickness as the first insulating film in the first opening. Comprising one conductive type deposited semiconductor layer;
A first conductivity type buffer region in which the deposited semiconductor layer is in contact with the surface of the semiconductor substrate through the second opening; a second conductivity type base region on the substrate insulating film and adjacent to the first conductivity type buffer region; A one-conductivity-type emitter region located within the other-conductivity-type base region and sandwiching the surface of the other-conductivity-type base region with the one-conductivity-type buffer region;
In a MOS type semiconductor device having a MOS gate structure having a polycrystalline semiconductor gate electrode laminated on the surface of the other conductivity type base region via a gate insulating film, the interval between the first insulating films sandwiching the first opening is 25 μm The object is achieved by using the following MOS type semiconductor device.

According to the second aspect of the present invention, the deposited semiconductor layer is preferably an MOS type semiconductor layer according to the first aspect of the present invention which is an epitaxial silicon layer.
According to the present invention as set forth in claim 3, the width of the first insulating film sandwiching the first opening in the substrate surface direction is 1 μm to 5 μm. The MOS type semiconductor device is desirable.

According to the present invention as set forth in claim 4, the first insulating film sandwiching the first opening has a linear plane pattern. More preferably, the MOS type semiconductor device according to any one of the above is used.
According to the present invention as set forth in claim 5, the first insulating film has a plane pattern arranged in a discontinuous line at a predetermined interval. It is desirable that the MOS type semiconductor device according to any one of 4 is used.

According to the present invention of claim 6, the first insulating film has a quadrangular prism or a columnar shape arranged in a discontinuous line at a predetermined interval. The MOS type semiconductor device according to claim 5 is desirable.
According to the seventh aspect of the present invention, the first opening is formed in the first insulating film provided on the surface of the one-conductivity type semiconductor substrate, and the first opening is formed in the first opening. After forming a thin substrate insulating film, subsequently providing a second opening in the substrate insulating film, and after forming an epitaxial semiconductor layer in the first opening to a thickness greater than the thickness of the first insulating film, A MOS type semiconductor device comprising a step of polishing the surface of the epitaxial semiconductor layer so as to have the same thickness as the first insulating film, and then forming a gate electrode on the epitaxial semiconductor layer via a gate oxide film In the manufacturing method, after the surface of the epitaxial semiconductor layer is polished to the same thickness as the first insulating film, a sacrificial oxide film is formed to a thickness of 0.05 μm to 0.1 μm, and thereafter Remove the epitaxy The object can be achieved by a method for manufacturing a MOS type semiconductor device in which a gate electrode is formed on a semiconductor layer via a gate oxide film.

  According to the present invention, even if a trench gate structure is not employed, the epitaxial structure constituting the top gate structure is obtained in order to obtain a MOS type semiconductor device having a top gate structure that further improves the trade-off relationship between the on-voltage and the turn-off loss. MOS type semiconductor device having a top gate structure that prevents excessive polishing and excessive polishing during the formation of a silicon layer, suppresses variations in on-voltage, reduces the surface roughness of the polished epitaxial silicon layer, and improves gate characteristics. Can be provided.

Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1A and 1B relate to an IGBT having a surface cathode side high injection structure according to the present invention. FIG. 1A is a cross-sectional view of a main part of an IGBT semiconductor substrate, and FIG. It is a principal part perspective view. 2A and 2B are cross-sectional views of the semiconductor substrate showing the states of overpolishing and excessive polishing. FIG. 2A is a cross-sectional view of the main part of the semiconductor substrate immediately after the growth of the epitaxial silicon layer, and FIG. The principal part sectional drawing of the semiconductor substrate which shows a state, (c) is principal part sectional drawing of the semiconductor substrate which shows the excessive polishing state after epitaxial silicon layer growth. FIG. 3 is a diagram showing the relationship between the first opening width and the excessive polishing amount related to the IGBT manufacturing method according to the present invention. FIG. 4 is a relationship diagram between the epitaxial silicon layer thickness variation of the IGBT and the on-voltage according to the present invention. FIG. 5 is a plan view (a) and a sectional view (b) showing a plane pattern of the first insulating film of the IGBT according to the present invention. FIG. 6 is a plan view (a) and a sectional view (b) showing different plane patterns of the first insulating film of the IGBT according to the present invention. 7-9 is principal part sectional drawing of the semiconductor substrate which shows the main manufacturing processes of IGBT concerning Example 1, 2 of this invention. FIG. 10 is a relationship diagram between the sacrificial oxide film and the surface roughness. FIG. 11 is a relationship diagram between the sacrificial oxide film and the gate breakdown voltage.

7 to 9 are cross-sectional views of the main part of the semiconductor substrate in the main manufacturing process regarding the structure and manufacturing method of the IGBT having the top gate type high surface injection structure according to the first embodiment of the present invention. .
As shown in FIG. 7A, the mirror polishing finish of the n-type FZ-silicon substrate 1 is used as the semiconductor substrate. The specific resistance of the substrate is preferably in the range of 30 to 200 Ωcm, and is selected according to the breakdown voltage required for the IGBT. For example, if an 80 Ωcm substrate 1 is used, an IGBT with a withstand voltage of 1200 V can be obtained. Any reference oxide film 2 selected from a film thickness range of 0.3 μm to 1 μm by thermal oxidation or CVD growth is formed on the substrate 1. Next, patterning with a photoresist is performed on the film, and the reference oxide film 2 is selectively dry-etched to form a stripe-like planar pattern to form a large first opening 3 (FIG. 7B). ). At this time, the width of the first opening 3 between the reference oxide films 2 at the end portions remaining without being opened is 5 to 25 μm, and the width in the substrate surface direction of the reference oxide film 2 formed of a striped planar pattern is 0.5 μm. Any of the range of ˜2 μm is desirable. Here, the width of the reference oxide film 2 is 1 μm, and the width of the first opening 3 is 20 μm. Subsequently, as shown in FIG. 7C, a substrate oxide film 4 is formed on the entire surface in a thickness range of 0.05 μm to 0.2 μm by thermal oxidation or CVD, and then the substrate is formed by photolithography. A second opening 5 having a diameter of 1 μm is formed in the center of the oxide film 4. As described above, the protrusion amount (film thickness) of the reference oxide film 2 is preferably in the range of 0.3 μm to 1 μm, but here, the thickness of the substrate oxide film 4 is 0.1 μm and the protrusion amount of the reference oxide film 2 ( The film thickness was 0.7 μm, and the total thickness was 0.8 μm.

Thereafter, as shown in FIG. 7D, an epitaxial silicon layer 6 is grown using the surface of the silicon substrate 1 exposed through the second opening 5 as a seed layer. As a typical process gas, a main gas is dichlorosilane or trichlorosilane, hydrogen gas is a carrier gas, and arsine or phosphine is added as a doping gas. The reaction pressure is preferably 100 to 760 Torr (1 Torr = 133.3 Pa), and the silicon substrate (wafer) temperature is about 1000 ° C. Here, phosphine was used as a doping gas, and the conditions were controlled so that the phosphorus concentration in the film was 1 × 10 ¹⁶ cm ⁻³ . When growth of the n-type epitaxial silicon layer 6 starts at the second opening 5 and the growth surface exceeds the thickness of the substrate oxide film 4 and is higher than the position of the upper surface, the growth proceeds laterally on the substrate oxide film 4. . Thereafter, the gas supply is stopped when the entire surface is covered by overcoming the protruding portion (thickness portion) of the reference oxide film 2 at the end portion to stop the growth.

  Next, the silicon substrate 1 on which the n-type epitaxial silicon layer 6 is formed is carried into a CMP apparatus, and the reference oxide film 2 is used as a stopper film, as shown in FIG. ) 6 Polish until the surface has a flat cross-sectional shape. What is important at this time is that the selection ratio ((Si polishing rate / oxide film polishing rate) is increased to 50 times or more, preferably 100 times or more, so that the polishing is reliably performed on the upper surface of the reference oxide film (stopper film) 2 For this purpose, it is effective to use, for example, a high-purity colloidal silica slurry planarlite-6103 manufactured by Fujimi Incorporated Co., Ltd. Typical polishing conditions include a top ring pressure of 300 to 600 hPa. The rotational speed of the table is 50 to 100 rpm, and the selection ratio is about 100. The polishing time may be constant, but excessive polishing (the epitaxial silicon layer on the reference oxide film 2 serving as a reference) may be used. Insufficient polishing with residual residues-Fig. 2 (b)) and excessive polishing (dishing-reference oxidation as reference) It is effective to perform some kind of end point detection to suppress the occurrence of the epitaxial silicon layer being thinner than the upper surface of FIG. Detection, reflected light measurement, etc. Here, motor torque detection is used to suppress polishing defects and to make the thickness of the n-type epitaxial silicon layer 6 substantially constant.

  However, if the area of the reference oxide film (stopper film) 2 is relatively smaller than that of the silicon area, in other words, if the distance between the stopper oxide films 2 (the width of the first opening) is large, an end point detection is performed during polishing. When the reference oxide film 2 is exposed, dishing (excessive polishing) is likely to occur near the center above the first opening 3 as shown in FIG. Further, if the polishing time is shortened in order to eliminate the dent due to the dishing at the center portion, as shown in FIG. 2B, since the thickness of the epitaxial silicon layer is thicker than the thickness of the reference oxide film 2, Be careful.

  FIG. 3 shows the relationship between the width of the first opening 3 and the excessive polishing amount. When the width of the first opening 3 is shortened, the excessive polishing amount decreases. In the middle of the decrease, there is an inflection point at 25 μm, and it can be seen that the excessive polishing amount can be greatly reduced by setting the width of the first opening 3 to 25 μm or less. The width of the reference oxide film 2 for end point detection (the width in the substrate surface direction) is preferably 1 μm or more and 5 μm or less. If the thickness is less than 1 μm, detection at the time of polishing becomes difficult, and polishing cannot be stopped properly, resulting in excessive polishing. If the thickness is 5 μm or more, the inactive region increases with respect to the effective active area through which current flows. .

  FIG. 4 shows the relationship between the variation in the thickness of the epitaxial silicon layer after polishing (excessive polishing and excessive polishing) and the on-voltage. In the case of 0.2 μm surplus polishing, the ON voltage increases by 0.07V. Moreover, when it becomes 0.2 micrometer excessive polishing, it becomes 0.09V lower. Since the variation in the thickness of the epitaxial silicon layer affects the variation in the ON voltage, it is desirable that the variation is as small as possible.

  Further, as shown in FIG. 5A, by forming the reference oxide film (oxide film stopper) 2 in a rectangular cell-like discontinuous linear plane pattern, an effective current is improved as compared with the case of a normal linear plane pattern. It is possible to increase the active region through which the gas flows. The distance e between the square column cells of the oxide film stopper 2 is preferably shorter than the first opening 3 width a. As shown in FIG. 6A, the oxide film stopper 2 may have a cylindrical shape.

According to the MOS type semiconductor device having the top gate structure according to the present invention, the first opening 3 width and the planar pattern of the stopper oxide film 2 as shown in FIGS. Thus, excessive polishing and excessive polishing of the epitaxially grown silicon layer can be prevented, and variations in on-voltage can be significantly suppressed.
Next, a sacrificial oxide film having a thickness of 0.08 μm is formed on the polished surface of the epitaxial silicon layer 6, and then the sacrificial oxide film is removed with hydrofluoric acid to improve the surface state.

Subsequently, as shown in FIG. 8F, a gate oxide film 7 is formed on the entire surface of the epitaxial silicon layer 6 by thermal oxidation or CVD. Here, the thermal oxide film is formed with a thickness of 0.1 μm. Next, as shown in FIG. 8G, a polysilicon layer 8 to be a gate electrode is formed on the entire surface by CVD with a thickness of about 0.5 .mu.m. Thereafter, as shown in FIG. The silicon layer 8 is partially removed. Subsequently, boron ions with a dose of 5 × 10 ¹⁴ cm ⁻² are performed using the remaining polysilicon layer 8 as a mask, drive diffusion is performed at 1150 ° C. for 2 hours in a nitrogen atmosphere, and a dose of 1 × 10 ^{15 is} further achieved. Argon ions of cm ⁻² are ion-implanted, and drive diffusion is performed at 1000 ° C. for 30 minutes to form the p-type base region 9 and the n ⁺⁺ -type cathode region 10.

  Thereafter, as shown in FIG. 9I, a BPSG film 11 having a thickness of about 1 μm is formed on the entire surface to form an interlayer insulating film. Subsequently, a contact opening 12 for contact with the metal electrode is formed. Next, as shown in FIG. 9 (j), an aluminum electrode (cathode electrode) 13 having a film thickness of 5 μm is formed, and an anode electrode is formed on the anode side of the back surface of the substrate (not shown), whereby the IGBT according to the embodiment of the present invention is formed. This completes the semiconductor substrate.

The IGBT according to this embodiment has the following advantages.
1. By forming the channel region (p-type base region) 9 with the epitaxial silicon layer 6, the mobility increases and the resistance loss decreases.
2. By forming the channel region 9 from an epitaxial silicon layer, the leakage current during forward blocking is reduced.

3. The epitaxial silicon layer 6 can be made thin and uniform by CMP (Chemical Mechanical Polisher) using the reference oxide film 2 having a predetermined dimension as a stopper. This leads to an improvement in the breakdown voltage of the IGBT and a reduction in variation in on-voltage characteristics.
4. The gate breakdown voltage is improved and stabilized.

Next, the operation and effect of the IGBT created in Example 1 will be described.
(Regarding steady ON state)
When a positive potential is applied to the gate electrode (gate polysilicon layer 8) with respect to the cathode (emitter) electrode 13, as shown in FIG. 1A, which is an enlarged view of FIG. A region near the interface with the gate oxide film 7 on the surface of the region 9 is inverted to n-type, and an n-type inversion layer (channel) is formed. In this state, when a forward bias is applied between the collector (not shown) and the emitter (between the anode and the cathode), the electrons are stored in the channel and the electron storage layer (n ⁺ region along the gate oxide film 7 of the buffer region 15). 14, flows into the drift layer (n ⁻ single crystal silicon substrate) 1 and reaches the p ⁺ anode layer on the back surface (not shown). Thereby, a pn junction (not shown) between the p ⁺ anode layer and the drift layer is forward-biased, so that holes are injected from the p ⁺ anode layer into the drift layer.

The injected holes enter the n ⁺ buffer region 15 from the second opening 5 when they reach the upper layer of the drift layer 1. n ⁺ portion of the holes enters the buffer area 15, and disappear recombined with electrons in the n ⁺ buffer region 15 within. The remaining holes pass through the n ⁺ buffer region 15 and are collected in the p-type base region 9. Since the hole current flows through the narrow and long epitaxial silicon layer 6 which is the layer forming the n ⁺ buffer region 15 and the p-type base region 9, a voltage drop occurs. Therefore, the n ⁺ / n ⁻ junction composed of the surface n ⁺ region 14 and the n ⁻ drift layer 1 along the gate oxide film 7 of the n ⁺ buffer region 15 as the electron storage layer 14 is forward-biased. As a result, electrons are injected to increase the electron concentration on the cathode side, and accordingly, holes of the same concentration are accumulated to satisfy the charge neutrality condition.

When holes are injected into the n ⁺ buffer region 15, the n ⁺ / n ⁻ junction is further forward-biased, and electrons are injected. The epitaxial silicon layer 6 and the n ⁻ single crystal silicon substrate 1 are insulated and separated by the substrate oxide film 4 in most portions except the second opening 5. Therefore, the pnp-BJT region is a small part of the entire device, and the majority is the pin diode region. Further, the channel can be formed by fully using the area of the substrate surface, and the channel peripheral length can be freely increased. However, if the peripheral length is too large, the transfer characteristic becomes too high, the current limit at the time of short-circuiting increases, and the short-circuit withstand capability decreases, so it is necessary to determine the peripheral length in consideration of this point.

(For forward blocking state)
Next, the operation in the blocking mode in which a forward bias is applied between the collector and the emitter with the gate potential equal or negative compared to the emitter (cathode) potential will be described. A depletion layer spreads from the pn junction composed of the p-type base region 9 and the n ⁺ buffer region 15, and a depletion layer also spreads from the gate oxide film 7. This is because the n ⁺ buffer region 15 is positively biased while the gate electrode 8 is below the emitter potential. Since the n ⁺ buffer region 15 is only the thickness of the epitaxial silicon layer 6, it is completely depleted with a slight forward bias. If the total impurity amount in the n ⁺ buffer region 15 is set to a certain value or less, the maximum electric field strength in the n ⁺ buffer region 15 can be suppressed.

As the forward bias is further increased, the depletion layer extends into the n ⁻ drift layer 1. Since most of the applied forward bias is carried by the n ⁻ drift layer 1, the local peak of the electric field intensity in the n ⁺ buffer region 15 can be suppressed, and avalanche breakdown due to local electric field concentration hardly occurs. . Therefore, a sufficient forward breakdown voltage can be ensured. As a result, the on-voltage does not deteriorate even when the forward breakdown voltage is increased. This is a great advantage compared to conventional planar type or trench type IGBTs.

(About trade-off characteristics)
In the n ⁺⁺ type cathode region 10 having a high impurity concentration in the n ⁺ epitaxial silicon layer 6, since the doping concentration is very high, the resistance is low even if the carrier mobility is low, so there is almost no voltage drop. . Further, in this embodiment, the peripheral length of the p-type channel region (p-type base region 9) having a configuration obtained by converting the n ⁺ epitaxial silicon layer 6 into the p-type can be set relatively freely by pattern design. By making the peripheral length longer so as to compensate for the mobility degradation, the voltage drop can be made the same level as that of the conventional IGBT. Further, in the n ⁺ buffer region 15 composed of the n ⁺ epitaxial silicon layer 6, since the carrier mobility is low, the voltage drop slightly increases, but the contribution to the total on-voltage is small. Conversely, a merit that the potential of the n ⁻ drift layer 1 rises with respect to the cathode potential due to the voltage drop in the n ⁺ buffer region 15 is obtained.

On the other hand, the n ⁺ n ⁺ electron accumulation layer 14 composed of regions along the substrate oxide film 4 at the region and a second opening 5 along the gate oxide film 7 in the buffer area 15 within, electron concentration is very high ( ˜1 × 10 ¹⁹ cm ⁻³ ), and the electric resistance is low, so the voltage drop is small. Therefore, n ⁺ electron storage layer 14 and the n ^- drift layer 1 Metropolitan n ^{+ /} n ^- the bonding is more forward biased, easily injects electrons. That is, a major feature of the present invention is that the carrier distribution in the n ⁻ drift layer 1 becomes a surface deviated type due to a voltage drop in the n ⁺ buffer region 15. As a result, the effect of the present invention in which the trade-off between the on-voltage and the turn-off loss is optimized is exhibited. This means that the voltage drop in the n ⁻ drift layer, which occupies most of the on-voltage sharing, particularly in a high voltage IGBT, is minimized for a certain turn-off loss.

(Latch-up tolerance)
When the carrier lifetime and carrier mobility in the n ⁺ buffer region 15 are low, the diffusion length of holes that are minority carriers is shortened, and the recombination of carriers in the n ⁺ buffer region 15 is increased. As a result, the hole current that passes through the p-type base region 9 and is collected by the emitter electrode 13 is reduced. For this reason, the hole current contributing to the latch-up is reduced, and the latch-up resistance is improved.

(About micro processes)
The IGBT structure described above has an advantage in design that it is not necessary to make the surface pattern extremely fine. The cathode (emitter) contact region 12 is electrically isolated from the drift layer 1 by the substrate oxide film 4 as shown in FIG. 9 (j). The drift layer 1 is connected only at the second opening 5. Therefore, the design dimension of the cathode (emitter) contact region does not directly contribute to the characteristics of the drift layer 1. This is symmetric to the conventional planar type or trench type IGBT. In the conventional IGBT, all of the cathode (emitter) contact regions are directly connected to the drift layer, and the design dimensions are directly related to the characteristics. Therefore, the first embodiment has a feature that the trade-off characteristic is unchanged even if the n ⁺⁺ type emitter (cathode) region 10 is not particularly miniaturized as described above.

The second embodiment according to the present invention has the same structure as the IGBT having the top gate type high surface injection structure shown in FIGS. 7 to 9 described in the first embodiment, but the manufacturing method is different. Here, portions of the same manufacturing method are omitted to avoid repeated description, and only different manufacturing methods will be described.
The mirror polishing finish of the n-type FZ-silicon substrate 1 having the same specifications as in Example 1 is used. A pattern of the reference oxide film is formed, followed by epitaxial silicon growth, polishing using the reference oxide film as a stopper, and flattening to the same thickness as the reference oxide film is the same as in the first embodiment. . The following steps are different from those in the first embodiment, and will be described in detail. A 0.08 μm sacrificial oxide film is formed on the surface of the epitaxial silicon layer flatly polished to the same thickness as the reference oxide film by a thermal oxide film method, and then the sacrificial oxide film is removed with hydrofluoric acid. , Improve the surface condition. Next, a gate oxide film is formed. Subsequent steps are similar to those of the first embodiment, and the MOS semiconductor device according to the second embodiment of the present invention is completed.

  Here, a preferable formation condition of the sacrificial oxide film, which is a feature of the manufacturing method of Example 2, will be described. FIG. 3 shows the relationship between the surface roughness (vertical axis) of the epitaxial silicon layer and the thickness (horizontal axis) of the sacrificial oxide film when the manufacturing method according to Example 2 of the present invention is used. According to FIG. 3, it can be seen that when the thickness of the sacrificial oxide film is greater than 0.05 μm, the surface roughness is halved compared to the conventional product. In Example 2, the size of the surface roughness was halved compared to the conventional one, with the sacrificial oxide film formation / removal step, an oxide film grew on the rough surface roughness portion immediately after the polishing, This is considered to be the result of removing the rough portion. If the thickness of the sacrificial oxide film is too large, the thickness of the epitaxial silicon layer of the cathode layer is 0.7 μm. Therefore, if the thickness is 0.1 μm, the film thickness of the cathode layer increases, which affects the characteristics. Therefore, the thickness is preferably 0.1 μm or less. Therefore, the preferable range of the sacrificial oxide film thickness is 0.05 μm or more and 0.1 μm or less.

FIG. 4 shows the relationship between the sacrificial oxide film thickness on the horizontal axis and the gate breakdown voltage on the vertical axis. According to Example 2, it can be seen that a gate breakdown voltage of 60 V or more can be stably obtained.
According to the second embodiment of the present invention, the top gate type IGBT is made a manufacturing method for forming / removing a sacrificial oxide film immediately after polishing the epitaxial silicon layer, thereby reducing the surface roughness of the epitaxial silicon layer, Gate characteristics can be further improved.

1A is a cross-sectional view of a main part of an IGBT, and FIG. 1B is a perspective view of a main part of the IGBT according to the present invention shown in FIG. It is sectional drawing of the semiconductor substrate which shows the state of the excessive grinding | polishing and excessive grinding | polishing concerning this invention. It is a related figure between the 1st opening part width | variety regarding the manufacturing method of IGBT concerning this invention, and excessive polishing amount. It is a relationship figure between the epitaxial silicon layer thickness dispersion | variation of IGBT concerning this invention, and ON voltage. It is the top view and sectional drawing which show the plane pattern of the 1st insulating film of IGBT concerning this invention. It is a top view which shows the different plane pattern of the 1st insulating film of IGBT concerning this invention. It is a figure which shows the manufacturing method of IGBT concerning Example 1, 2 of invention (the 1). It is a figure which shows the manufacturing method of IGBT concerning Example 1, 2 of invention (the 2). It is a figure which shows the manufacturing method of IGBT concerning Example 1, 2 of invention (the 3). It is a relationship figure between the sacrificial oxide film concerning this invention, and surface roughness. FIG. 5 is a relationship diagram between a sacrificial oxide film and a gate breakdown voltage. It is a figure which shows the equivalent circuit of IGBT. It is sectional drawing which shows the structure of the principal part of planar type IGBT.

Explanation of symbols

1 One conductivity type semiconductor substrate, FZ-silicon substrate (drift layer)
2 First insulating film, reference oxide film 3 First opening 4 Substrate insulating film, substrate oxide film 5 Second opening 6 One-conductivity-type deposited semiconductor layer (epitaxial silicon layer)
7 Gate insulating film, gate oxide film 8 Polycrystalline gate electrode, polysilicon gate electrode 9 Other conductive type base region, p-type base region (channel region)
10 emitter region of one conductivity type, n ⁺⁺ type emitter region, n ⁺⁺ type cathode region 11 interlayer insulating film, BPSG film 12 emitter contact region 13 emitter electrode (cathode electrode)
14 n ⁺ accumulation layer 15 one conductivity type buffer region, n ⁺ buffer layer.

Claims (6)

A first insulating film having a first opening on the surface of the one-conductivity-type semiconductor substrate, a substrate insulating film provided in the first opening and being thinner than the first insulating film, and a first insulating film provided on the substrate insulating film A two-opening and a one-conductivity-type deposited semiconductor layer that is stacked on the substrate insulating film and in the first opening with a thickness similar to the first insulating film;
A first conductivity type buffer region in which the deposited semiconductor layer is in contact with the surface of the semiconductor substrate through the second opening; a second conductivity type base region on the substrate insulating film and adjacent to the first conductivity type buffer region; A one-conductivity-type emitter region located within the other-conductivity-type base region and sandwiching the surface of the other-conductivity-type base region with the one-conductivity-type buffer region;
In a MOS type semiconductor device having a MOS gate structure having a polycrystalline semiconductor gate electrode laminated on the surface of the other conductivity type base region via a gate insulating film, the interval between the first insulating films sandwiching the first opening is 25 μm A MOS semiconductor device characterized by the following. 2. The MOS semiconductor device according to claim 1, wherein a width of the first insulating film sandwiching the first opening in a substrate surface direction is 1 μm to 5 μm. 3. The MOS semiconductor device according to claim 1, wherein the first insulating film sandwiching the first opening has a linear plane pattern. 4. The MOS according to claim 1, wherein the first insulating film sandwiching the first opening has a planar pattern arranged in a discontinuous line at a predetermined interval. 5. Type semiconductor device. 5. The MOS semiconductor device according to claim 4, wherein the first insulating film is a quadrangular column or a columnar shape arranged in a discontinuous line at a predetermined interval. A first opening is formed in the first insulating film provided on the surface of the one-conductivity-type semiconductor substrate, a substrate insulating film having a thickness smaller than that of the first insulating film is formed in the first opening, and then the substrate insulating film is formed. And forming an epitaxial semiconductor layer in the first opening to a thickness equal to or greater than the thickness of the first insulating film, and then polishing the surface of the epitaxial semiconductor layer to obtain a thickness of the first insulating film. In the method of manufacturing a MOS type semiconductor device, the method further includes a step of forming a gate electrode on the epitaxial semiconductor layer via a gate oxide film after the thickness is made to be about the same as the thickness of the epitaxial semiconductor layer. After the thickness is made to be about the same as the thickness of one insulating film, a sacrificial oxide film is formed to a thickness of 0.05 μm to 0.1 μm and then removed, and then a gate oxide film is interposed on the epitaxial semiconductor layer. Gate electrode A method of manufacturing a MOS semiconductor device, comprising: forming a MOS semiconductor device.

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