JP2007318873A - PWM motor drive circuit - Google Patents

Abstract

Spiking noise during switching is reduced.
In parallel with a bias resistor R1, a shunt NPN transistor Q1 is connected to a source terminal and a gate terminal of a P-channel MOSFET transistor Tru ₊ of the output circuit via a current limiting resistor Ra. The series circuit S in which the cathode terminal of the second diode Da and one end of the resistor Rb are connected to the gate terminal of the N-channel MOSFET transistor _Tru- of the output circuit, and the other end of the resistor Rb is connected to the gate of the MOSFET transistor _Tru- . The terminal is connected in parallel with the third resistor R7. Thus, the charge accumulated in the gate at the time of turning off the P-channel MOSFET transistor Tru ₊ is discharged via the current limiting resistor Ra. On the other hand, the charge accumulated in the gate at the turn-off time of the N-channel MOSFET transistor _Tru- is discharged through the third resistor R7, thereby restricting the di / dt of the turn-off current and reducing spike noise.
[Selection] Figure 1

Description

  The present invention relates to a PWM motor drive circuit that reduces spike noise during switching.

  As a circuit for PWM-controlling a brushless DC motor, for example, there is a three-phase inverter circuit as shown in FIG. 3 described in (Patent Document 1).

This circuit is a driving circuit for a brushless DC motor controlled by a microcomputer. As shown in FIG. 3, an output circuit for driving motor coils (hereinafter referred to as stator coils) of each phase U, V, W is connected to a P-channel MOSFET transistor Tru _+. , Tr _{v +} , Tr _{w +} and N-channel MOSFET transistors Tr _u− , Tr _v− , Tr _w− are used to save power.

Further, as shown in FIG. 4 (the U phase is shown), the drive circuit 1 for each of U, V, and W phases of the drive circuit includes a source terminal and a gate terminal of the upper P-channel MOSFET transistor Tru _+. A bias resistor R1 is provided therebetween, and a shunt NPN transistor Q1 is provided in parallel with the bias resistor R1. The transistor Q1 is turned on when the P-channel MOSFET transistor Tru ₊ is turned off, thereby improving the turn-off speed of the P-channel MOSFET transistor Tru ₊ and reducing the switching loss.

By the way, in the drive circuit 1 described above, as shown in “a” of FIG. 5A, for example, the U-phase P-channel MOSFET transistor Tru ₊ is ON and the V-phase N-channel MOSFET transistor _Trv− is ON. Thus, the current i ₁ flows from the stator coil U → V as shown in the figure. This current i ₁ is exponential as shown in FIG. 5B according to the time constant α = L / R (s) determined by the inductance L (mH) between the stator coils U and V and the resistance R (Ω). To increase.

Next, as shown in FIG. 5 "B", the U-phase of the P-channel MOSFET transistor _{Tr u +} is switched from ON to OFF, the current _{i 2} flows as shown, when based on the constant α 5 (b) Like, it decreases exponentially.

At this time, if the direction in which the current i ₁ flows into the stator coil U → V is positive as indicated by “A” in FIG. 5A, the amount of change di / dt is positive. On the other hand, in “B” in FIG. 5A, the direction of the current flowing into the stator coil U → V does not change, but since the current decreases, the change amount di / dt becomes negative. In this way, by the sign of the variation di / dt of the current changes from positive to negative, the stator coils U, orientation inverted voltage drop generated in the V, so that the current flow path i ₂ passes through the diode D3 Changes to.

Here, the problem is firstly the turn-off speed of Tru ₊ when changing from “A” to “B” in FIG. In this case, since the current is changed from decrease → increase and increase → decrease in a short time, the current change amount di / dt is large, and the change amount is changed to the inductance value L of the stator coils U and V including the wiring inductance. A spike voltage multiplied by ± di / dt is generated. Similarly, a spike voltage is also generated when the N-channel MOSFET transistor Trv− is _turned off as indicated by “c” and “d” in FIG.

JP 2006-41571 A

  However, the noise due to the spike voltage reaches several hundreds mp-pV at a large level, and as shown in FIG. 7, the frequency ranges from several hundreds (KHZ) to several hundreds (MHZ) with an attenuation waveform including ringing. Contains ingredients.

  Therefore, when this spike noise is fed back to the AC power supply side, it becomes a noise terminal voltage or noise terminal power, and the operation margin is surely reduced. And it adversely affects the technical standard value of the Electrical Appliance and Material Safety Law.

  Therefore, an object of the present invention is to reduce spike noise that reduces the operating margin.

  In order to solve the above problems, in the present invention, between the collector and source terminals of the shunt NPN transistor connected between the source terminal and gate terminal of the P-channel MOSFET transistor of the output circuit in parallel with the bias resistor, or between the emitter and gate terminal. A current limiting resistor is provided in one or both, and a series circuit in which the cathode terminal of the second diode and one end of the resistor are connected to the gate terminal of the N-channel MOSFET transistor of the output circuit is connected to the other end side of the resistor. A configuration is adopted in which the transistor is connected in parallel with the third resistor on the gate terminal side.

  By adopting such a configuration, the NPN transistor discharges the charge (parasitic capacitance) accumulated in the gate when the P-channel MOSFET transistor is turned off through the current limiting resistor. In this way, the change in the gate voltage during discharge is moderated to regulate the current di / dt. On the other hand, in the N-channel MOSFET transistor, the N-channel MOSFET transistor is turned on via the combined resistance of the parallel circuit. When turning off, the diode of the parallel circuit is reversely connected and the series circuit is turned off. Therefore, the gate charge of the N-channel MOSFET transistor is discharged via the third resistor (the resistance value is higher than the combined resistance). By so doing, the change in the gate voltage during discharge can be moderated, so that the current di / dt can be regulated.

  According to the present invention configured as described above, a driving circuit with reduced spike noise can be realized.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

FIG. 1 shows one phase (U phase) of the three-phase brushless DC motor driving circuit controlled by the microcomputer according to the present application, and uses an output circuit using a P-channel MOSFET transistor Tru ₊ and an N-channel MOSFET transistor _Tru-. It operates with a single power supply.

The output circuit connects the drain terminal of the P-channel MOSFET transistor Tru _{+ and} the drain terminal of the N-channel MOSFET transistor _Tru- , and connects the source terminal of the P-channel MOSFET transistor Tru ₊ to the power supply (positive side) + V _DD. , The source terminal of the N channel MOSFET transistor Tr _u− is connected to the negative side GND of the power source, and the connection point of the drain terminal of the P channel MOSFET transistor Tr _{u +} and the N channel MOSFET transistor Tr _u− is connected to the stator coil U of the motor. As output.

Also, by connecting the bias resistor R1 between the P-channel MOSFET transistor _{Tr u +} source and gate terminals of the bias resistors R1 and P-channel MOSFET transistor the collector and emitter terminals of the shunt NPN transistor Q1 in parallel _{Tr v +} The current limiting resistor Ra is provided between the emitter of the NPN transistor Q1 and the gate terminal of the P-channel MOSFET transistor Tru ₊ .

The current limiting resistor Ra is for limiting the current when the shunt NPN transistor Q1 is short-circuited. Therefore, in this embodiment, it is provided between the emitter of the shunt NPN transistor Q1 and the gate terminal of the P-channel MOSFET transistor Tru ₊ , but is not limited to this, and the collector of the shunt NPN transistor Q1 and the P-channel It may be provided between the source terminals of the MOSFET transistor Tru ₊ , or may be provided separately between the emitter and gate terminals and between the collector and source terminals.

The gate terminal of the P-channel MOSFET transistor Tru ₊ is connected to one end of the first resistor R2, the other end of the resistor R2 is connected to the collector terminal of the input NPN transistor Q2, and the base of the transistor Q2 is connected. connect the terminal power supply via the (positive) + V _CC to the resistor R5, it is connected to the port P1 of the microcomputer 2 via the emitter terminal of the transistor Q2 of the second resistor R6. Thus, by providing the transistor input circuit based on the base, it becomes possible to respond at high speed, and the input impedance can be reduced, so that the margin for noise can be increased.

  A diode D4 is reversely connected to the base terminal and the emitter terminal of the input NPN transistor Q2 so that a current can flow at the output voltage of the port P1 of the microcomputer 2 so that Vbe = 0.6 V of the input NPN transistor Q2. It is like that.

On the other hand, the anode terminal of the diode D1 is connected to the connection point between the first resistor R2 and the gate terminal of the P-channel MOSFET transistor Tru ₊ , and the connection point between the first resistor R2 and the collector terminal of the input NPN transistor Q2. One end of the capacitor C1 is connected to the other end, the other end of the capacitor C1 and the cathode terminal of the diode D1 are connected via a resistor R3 (R3 <R2), and the connection point is connected to the base terminal of the shunt NPN transistor Q1. It is.

  By doing so, the diode D1 is prevented from being damaged by an excessive current flowing to the capacitor C1, thereby improving the reliability.

On the other hand, the N-channel MOSFET transistor _Tru- of the output circuit includes a series circuit S in which the gate terminal is connected to the cathode terminal of the diode Da and one end of the resistor Rb, and the other end of the resistor Rb is connected to the MOSFET transistor _Tru- . The gate terminal is connected in parallel with the third resistor R7. The other end of the parallel circuit having one end connected to the gate terminal is connected to the port P2 of the microcomputer 2, and an input signal having the same phase as the input signal is input.

  Diodes D2 and D3 are flywheel diodes. The resistor R4 is a discharge resistor for discharging the electric charge of the capacitor C1.

  The U phase is configured as described above, and the PWM motor drive circuit of the present application is configured by the U phase configured as described above, and the V phase and the W phase having the same configuration as the U phase. The difference between the U, V, and W phases of the present application configured as described above and the U, V, and W phases described in the conventional example is that a portion related to the series circuit S of the diode Da and the resistor Rb, Since this is a part related to the current limiting resistor Ra, the present invention will be described in detail for that part. In this case, in order to facilitate understanding, the excitation patterns and current paths shown in FIGS. 5 and 6 described in the conventional example are used.

For example, when the U-phase port P1 of the microcomputer 2 is “L” and the V-phase port P2 is “H”, as shown in FIG. _{u +} and the V-phase N-channel MOSFET transistor Tr _v− are turned on.

That is, the U-phase input NPN transistor Q2 is turned on by the “L” output of the port P1, and a current flows through the path of the resistor R1, the resistor R2, the NPN transistor Q2, and the resistor R6, and the P-channel MOSFET transistor Tru ₊ Is charged and turned on.

The gate voltage V _{GS at} this time is
V _GS = {R1 / (R1 + R2)} * (V _DD −V _CC ) (V)
And is controlled by this voltage.

  At this time, the capacitor C1 is charged to the polarity shown in FIG. 1 by the current flowing through the resistor R1, the diode D1, the resistor R3, and the capacitor C1.

On the other hand, the gate terminal of the V-phase N-channel MOSFET transistor Tr _v− is the “H” output of the port P2,
i _p = V _CC / {R7 * Rb / (R7 + Rb)} (A)
Next, N-channel MOSFET transistor _{Tr v-gate} in the peak current _{i p} is turned on is charged.

Next, when the U-phase port P1 changes from “L” to “H” and the U-phase P-channel MOSFET transistor Tru ₊ switches from on to off, as shown in FIG. The input NPN transistor Q2 is turned off.

At this time, the electric charge stored in the capacitor C1 flows into the base of the shunt NPN transistor Q1, turning on the NPN transistor Q1. Therefore, the shunt NPN transistor Q1 is turned on to short-circuit the source and gate terminal of the P-channel MOSFET transistor Tru ₊ , and the surplus gate carriers disappear.

At this time, the flowing current is regulated by the combined resistance of the current limiting resistor Ra and the bias resistor R1, but the time constant at this time is
CR = (Q / V _G ) * R // R1 (s)
here,
Q: charge input charge at a gate voltage _{V G} [C]
V _GS : (R1 / R1 + R2) * (V _DD −V _CC ) [V]
R // R1: Ra * R1 / (Ra + R1)
This is limited by a large time constant as compared to the conventional NPN transistor Q1 alone. Therefore, the current change amount di / dt can be moderated.

The state is shown in FIGS. 2 (a) and 2 (b). FIG. 2A is a diagram showing a case where only the conventional NPN transistor Q1 is used, and FIG. 2B is a case where the current limiting resistor Ra of the present application is applied. As shown in FIGS. 2A and 2B, as shown in FIGS. 2A and 2B, the current change amount di / dt between the conventional one and the one provided with the current limiting resistor Ra of the present application (in FIG. 2). When A, B, C, D) are compared, it is clear that A> C, B> D
It becomes. This is an effect of slowing the turn-off speed of the P-channel MOSFET transistor Tru ₊ . As described above, when the turn-off speed becomes slow, the current change amount di / dt becomes small, so that the spike voltage can be suppressed.

On the other hand, when the V-phase port P2 is switched from “H” to “L” and the N-channel MOSFET transistor Tr _v− is switched from on to off as shown in FIG. The charge at the gate terminal of the N-channel MOSFET transistor Tr _v− is discharged by the resistor R7.

  That is, when the port P2 becomes “L”, the diode Da in the parallel circuit is turned off. Therefore, the gate terminal is connected to the port P2 by the resistor R7. At this time, since the resistor R7 exhibits a value higher than the combined resistance of the parallel circuit, the current change amount di / dt at the time of turn-off can be reduced. Therefore, since the amount of change di / dt in current at turn-off can be reduced, the spike voltage can be suppressed.

  Thus, since the spike voltage at the time of switching that reduces the operation margin can be reduced, the noise sneaking into the AC power supply can be reduced and the noise terminal voltage and the noise terminal power can be reduced. Therefore, a highly reliable PWM drive circuit with a large operation margin can be realized.

  Since the present invention can realize a switching circuit with high reliability by suppressing the occurrence of spike voltage, it is also optimal for use in an inverter circuit or the like.

Circuit diagram of the embodiment Action explanatory diagram of the embodiment Block diagram of drive circuit Circuit diagram of conventional example (A), (b) Operation explanatory diagram of the conventional example (C), (D) Operation explanatory diagram of the conventional example Action explanatory diagram of conventional example

Explanation of symbols

C1 capacitor D1 first diode Da second diode GND negative side Q1 shunt NPN transistor Q2 input NPN transistor R1 bias resistor R2 first resistor R6 second resistor R7 third resistor Rb resistor Tr _{u +} P-channel MOSFET Transistor Tr _u- N channel MOSFET transistors U, V, W Stator coil + V _DD plus side + V _CC plus side

Claims (1)

The connection point of the output circuit in which the drain terminal of the P-channel MOSFET transistor (Tr _{u +} ) and the drain terminal of the N-channel MOSFET transistor (Tr _u− ) are connected is an output to the motor coil (U, V, W),
The source terminal of the P-channel MOSFET transistor (Tr _{u +} ) of the output circuit is connected to the positive side (+ V _DD ) of the power source, and the source terminal of the N-channel MOSFET transistor (Tr _u− ) is connected to the negative side (GND) of the power source. do it,
A bias resistor (R1) is connected between the source terminal and gate terminal of the P-channel MOSFET transistor (Tr _{u +} ), and the collector terminal and emitter terminal of the shunt NPN transistor (Q1) are connected in parallel with the bias resistor (R1). The channel MOSFET transistor (Tr _{u +} ) is connected to the source terminal and the gate terminal, and the shunt NPN transistor (Q1) and the P channel MOSFET transistor (Tr _{u +} ) are connected between the collector and the source terminal or between the emitter and the gate terminal. Either or both are connected through a current limiting resistor (Ra),
The collector terminal of the input NPN transistor (Q2) is connected to the gate terminal of the P-channel MOSFET transistor (Tr _{u +} ) via the first resistor (R2), and the base terminal of the input NPN transistor (Q2) is powered. the plus side connected to the _{(+ V CC),} the emitter terminal via the second resistor (R6) to an input signal, and said first resistor (R2) and P-channel MOSFET transistor _{(Tr u} +) The anode terminal of the first diode (D1) is connected to the connection point with the gate terminal of the capacitor, and the connection point between the first resistor (R2) and the collector terminal of the input NPN transistor (Q2) is the capacitor (C1). To the other end of the capacitor (C1) and the cathode terminal of the first diode (D1) to connect the shunt NPN transistor. Connected to the base terminal of the register (Q1),
On the other hand, a series circuit (S) in which the cathode terminal of the second diode (Da) and one end of the resistor (Rb) are connected to the gate terminal of the N-channel MOSFET transistor (Tr _u− ) of the output circuit is the resistor (Rb). _Is connected to the third resistor (R7) in parallel with the other terminal side of the N-channel MOSFET transistor (Tr _u− ) as the gate terminal side, and is connected to the gate terminal via the parallel circuit in phase with the input signal. PWM motor drive circuit that inputs input signals.

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