JP2007318089A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board excellent in electrical characteristics, reliability, and the like. <P>SOLUTION: The wiring board 10 includes a core substrate 11, a capacitor 101, and a resin filling portion 33a. A containing hole 90 is formed in the core substrate 11, and a core substrate major surface side conductor 51 is arranged on the core major surface 12 of the core substrate 11. On the capacitor major surface 102 of the capacitor 101, a capacitor major surface side electrode 111 is arranged. The resin filling portion 33a fills the clearance between the capacitor 101 and the core substrate 11 in the containing hole 90, and secures the capacitor 101 to the core substrate 11. The resin filling portion 33a has a portion 93 where the major surface side wiring is formed. A major surface side connection conductor 61 is arranged on the portion 93 where the major surface side wiring is formed, for connecting the core substrate major surface side conductor 51 and the capacitor major surface side electrode 111 which is connected with the end T1 of via conductors 131, 132. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring substrate in which a capacitor is embedded in a core substrate and a wiring laminated portion is formed on the surface thereof.

In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU of a computer have been increased in speed and function, and accordingly, the number of terminals is increased and the pitch between terminals tends to be narrowed. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In an IC chip mounting wiring board constituting this type of package, it has been proposed to provide a capacitor in order to reduce switching noise of the IC chip and stabilize the power supply voltage. Note that when the wiring connecting the IC chip and the capacitor becomes long, the inductance component of the wiring increases and the above effect cannot be obtained. Therefore, the capacitor is preferably arranged as close to the IC chip as possible. As an example, a wiring board in which a capacitor is arranged in a core substrate located directly under an IC chip has been proposed (see, for example, Patent Document 1).
Japanese Patent Laying-Open No. 2005-39243 (see FIG. 4 etc.)

  Incidentally, the conventional wiring board includes a plurality of power supply paths for supplying power to the IC chip. As the power supply path, a first power supply path that connects to the IC chip through a through-hole conductor that penetrates the core substrate in the thickness direction, a second power supply path that connects to the IC chip through a via conductor of the capacitor, and the like There is. However, in addition to the through-hole conductor, the first power supply path also passes through the conductor pattern constituting the build-up layer on the core substrate. Since this conductor pattern is thin and has high resistance, even if power is supplied through the first power supply path, the voltage drop becomes large. In addition, since the via conductor constituting the second power supply path is often formed mainly of nickel having a higher resistance than copper or the like, even if power is supplied via the second power supply path, The voltage drop is large as in the case of one power supply path. When these voltage drops occur, the power supply voltage supplied to the IC chip becomes insufficient, leading to a malfunction of the IC chip.

  The present invention has been made in view of the above problems, and an object thereof is to provide a wiring board excellent in electrical characteristics, reliability, and the like.

  And as a means (means 1) for solving the above-mentioned problem, a housing hole portion having a core main surface and a core back surface and opening at least on the core main surface side is formed, and the core is formed on the core main surface. A core substrate on which a substrate main surface side conductor is disposed, a capacitor main surface and a capacitor back surface, a plurality of via conductors whose ends are located on the capacitor main surface, and connected to the plurality of via conductors A capacitor having a plurality of internal electrode layers arranged via a dielectric layer and having a capacitor main surface side electrode disposed on the capacitor main surface; the capacitor housed in the housing hole; and A resin-filled portion that fills a gap with the core substrate and fixes the capacitor to the core substrate, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface. The resin filling portion has a main surface side wiring forming portion located on the core main surface and the capacitor main surface side, and the core substrate main surface side conductor is formed on the main surface side wiring forming portion. And a main surface side connection conductor connecting the capacitor main surface side electrode connected to the end portion of the via conductor.

  Therefore, according to the wiring substrate of means 1, the core substrate main surface side conductor and the capacitor main surface side electrode connected to the end portion of the via conductor are connected by the main surface side connection conductor. An electrical path is formed to connect to the capacitor main surface side electrode through the conductor and the main surface side connecting conductor. As a result, the number of electrical paths connected to the capacitor main surface side electrode increases, so that the resistance in the wiring board is reduced and the voltage drop is reduced. Therefore, since the power can be reliably supplied to the capacitor main surface side electrode, a wiring board having excellent electrical characteristics and reliability can be obtained.

  Further, as another means (means 2) for solving the problems of the present invention, a housing hole portion having a core main surface and a core back surface and opening on the core main surface side and the core back surface side is formed. A core substrate main surface side conductor disposed on the core main surface, a core substrate on which the core substrate back surface conductor is disposed on the core back surface, a capacitor main surface and a capacitor back surface, the capacitor main surface And a plurality of via conductors penetrating between the back surfaces of the capacitors, and a plurality of internal electrode layers connected to the plurality of via conductors and arranged in layers via a dielectric layer, on the capacitor main surface A capacitor main surface side electrode connected to the capacitor main surface side end of the plurality of via conductors, and disposed on the capacitor back surface and connected to the capacitor back surface side end of the plurality of via conductors A capacitor having an electrode; a resin filling portion that fills a gap between the capacitor housed in the housing hole portion and the core substrate and fixes the capacitor to the core substrate; an interlayer insulating layer and a conductor layer; A first wiring laminated portion on which a semiconductor integrated circuit element can be mounted, an interlayer insulating layer and a conductor layer on the core back surface and the capacitor back surface. A second wiring laminated portion having a laminated structure on which a mother board can be connected, and the resin filling portion is arranged on a main surface side wiring cover located on the core main surface and capacitor main surface side. A forming portion, and a back surface side wiring forming portion located on the core back surface and the capacitor back surface side, on the main surface side wiring forming portion, the core substrate main surface side conductor and the via conductor Capacitors A main surface side connection conductor for connecting the capacitor main surface side electrode connected to the surface side end is disposed, and the back surface side conductor formation portion and the via conductor on the back surface of the capacitor on the back surface side wiring formation portion There is a wiring board characterized in that a back surface side connection conductor for connecting the capacitor back surface side electrode connected to the side end portion is disposed.

  Therefore, according to the wiring board of the means 2, the core substrate main surface side conductor and the capacitor main surface side electrode connected to the capacitor main surface side end of the via conductor are connected by the main surface side connecting conductor, whereby the core An electrical path that connects to the semiconductor integrated circuit element through the substrate main surface side conductor, the main surface side connection conductor, the capacitor main surface side electrode, and the first wiring laminated portion is formed. As a result, the number of electrical paths connected to the semiconductor integrated circuit element increases, so that the resistance in the wiring board is reduced and the voltage drop is reduced. Therefore, since power can be reliably supplied to the semiconductor integrated circuit element, the semiconductor integrated circuit element can be sufficiently operated, and malfunction of the semiconductor integrated circuit element can be prevented. Therefore, it is possible to obtain a wiring board having excellent electrical characteristics and reliability.

  The core substrate constituting the wiring board forms part of the core portion of the wiring board, and is formed in a plate shape having a core main surface and a core back surface located on the opposite side, for example. Such a core substrate has an accommodation hole for accommodating a capacitor. The accommodation hole may be a non-through hole that opens only on the core main surface side, or may be a through hole that opens on both the core main surface side and the core back surface side. The “core portion” is a portion composed of a core substrate and a lowermost resin insulating layer that forms the lowermost layer of the wiring laminated portion. Further, the capacitor may be accommodated in the accommodation hole in a completely embedded state, or may be accommodated in the accommodation hole in a state in which a part protrudes from the opening of the accommodation hole.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The core substrate main surface side conductor is a plain-shaped conductor or a net-shaped conductor formed so as to surround the opening edge of the accommodation hole, and penetrates between the core main surface and the core back surface. It is preferable to be connected to a plurality of through-hole conductors formed. In this way, the cross-sectional area of the core substrate main surface side conductor is increased, and the resistance is reduced. Therefore, it is easy to supply a large current using an electrical path that connects to the capacitor main surface side electrode through the through-hole conductor, the core substrate main surface side conductor, and the main surface side connection conductor.

  The capacitor constituting the wiring board has a capacitor main surface and a capacitor back surface, and has a structure in which a plurality of internal electrode layers are stacked via a dielectric layer. The capacitor is used in a state of being accommodated in the accommodation hole. In addition, the capacitor is fixed to the core substrate in a state in which the capacitor is accommodated in the accommodation hole portion, for example, by filling a gap between the capacitor and the core substrate with a resin filling portion made of a polymer material. The resin filling portion may be a part of the lowermost resin insulating layer of the wiring laminated portion, or may be a separate body from the lowermost resin insulating layer. If the resin filling portion is a part of the lowermost resin insulating layer, it is not necessary to prepare a material different from that of the lowermost resin insulating layer when forming the resin filling portion. Therefore, since the material necessary for manufacturing the wiring board is reduced, the cost of the wiring board can be reduced. In addition, since the capacitor is fixed simultaneously with the formation of the lowermost resin insulating layer, the process for assembling the capacitor is simplified. Therefore, the wiring board can be easily manufactured, and in this case, the cost can be reduced. On the other hand, if the resin filling portion is separate from the lowermost resin insulating layer, the function of the resin filling portion can be specialized for the function of fixing the capacitor. it can.

  An example of a suitable capacitor is a via array type ceramic capacitor. That is, in the capacitor, the via conductor includes a plurality of power supply via conductors and a plurality of ground via conductors, and the plurality of internal electrode layers are connected to the plurality of power supply via conductors. An electrode layer and a plurality of second internal electrode layers connected to the plurality of ground via conductors, wherein the capacitor main surface side electrode is disposed on the capacitor main surface and is connected to ends of the plurality of power supply via conductors. A first capacitor main surface side electrode connected to the capacitor, and a second capacitor main surface side electrode disposed on the capacitor main surface and connected to the ends of the plurality of ground via conductors, the capacitor back surface side An electrode is disposed on the back surface of the capacitor and is connected to end portions of the plurality of power supply via conductors, and a plurality of ground via conductors disposed on the back surface of the capacitor. A second capacitor back surface side electrode connected to the end, wherein the main surface side connection conductor is a core substrate main surface side power supply pattern, which is the core substrate main surface side conductor, and the first capacitor main surface side electrode. It is preferable that the back surface side connection conductor connects the core substrate back surface side ground pattern, which is the core substrate back surface side conductor, and the second capacitor back surface side electrode. With this configuration, it is easy to reduce the size of the capacitor as a whole, and it is also easy to reduce the size of the entire wiring board. In addition, high capacitance can be easily achieved despite being small, and more stable power supply can be achieved.

  As the dielectric layer, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like is preferably used, and alumina for borosilicate glass or lead borosilicate glass is used. A sintered body of a low-temperature fired ceramic such as a glass ceramic to which an inorganic ceramic filler is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized.

  The material for forming the internal electrode layer and the via conductor is not particularly limited, but it is preferable to use a metal that can be sintered simultaneously with the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a low-temperature fired ceramic sintered body is selected, copper, silver, or the like can be used as a material for forming the internal electrode layer and the via conductor.

  The wiring laminated portion in means 1 has a structure in which an interlayer insulating layer mainly composed of a polymer material and a conductor layer are laminated. Although there is a large difference in the pitch between terminals between the terminal group on the semiconductor integrated circuit element side and the terminal group on the capacitor side, both can be easily connected by providing a wiring laminated portion. Further, the wiring laminated portion (that is, the first wiring laminated portion in the means 2) is formed only on the core main surface and the capacitor main surface, but the interlayer insulating layer and the conductor layer are formed on the core back surface and the capacitor back surface. The second wiring laminated portion in the means 2 having a laminated structure may be further formed. With such a configuration, since an electric circuit can be formed not only in the first wiring laminated portion but also in the second wiring laminated portion, it is possible to further enhance the functionality of the wiring board.

  The capacitor main surface side electrode can be disposed at a suitable location on the capacitor main surface, and the capacitor back surface electrode can be disposed at a suitable location on the capacitor back surface. However, it is preferable that the capacitor main surface side electrode and the capacitor back surface side electrode are also arranged particularly on the outer periphery of the capacitor. In this way, the distance between the capacitor main surface side electrode and the main surface side connection conductor is shortened, so that the connection between the core substrate main surface side conductor and the capacitor main surface side electrode by the main surface side connection conductor is facilitated. . Similarly, since the distance between the capacitor back surface side electrode and the back surface side connection conductor is shortened, the connection between the core substrate back surface side conductor and the capacitor back surface side electrode by the back surface side connection conductor is facilitated.

  Examples of the main surface side connection conductor include a plating layer, a metal paste layer, a metal foil adhesion layer, a sputtering layer, a vapor deposition layer, and an ion plating layer. Among these, a plating layer (for example, a copper plating layer) Is preferred. This is because the plating layer can be formed in a short time and is advantageous in reducing the cost of the wiring board.

  Further, when the capacitor has a substantially rectangular shape in plan view, the main surface side connection conductor may be a belt-like pattern disposed on each side of the capacitor, or each capacitor may have A plurality of belt-like patterns arranged on the side may be used. Furthermore, the main surface side connection conductor may be a rectangular frame pattern arranged so as to cover the entire area of the main surface side wiring formation portion. When the main surface side connection conductor is a strip pattern and at least one strip pattern is arranged on each side, the number of main surface side connection conductors increases and the number of electrical paths connected to the capacitor main surface side electrodes increases. Therefore, the resistance can be reduced. In addition, variation in potential is less likely to occur on each side of the capacitor. On the other hand, when the main surface side connection conductor is a belt-like pattern and a plurality of belt-like patterns are arranged on each side, the number of the main surface side connection conductors further increases and the number of the electrical paths further increases. Can be planned. Further, when the main surface side connection conductor is a rectangular frame-shaped pattern, the number of the electrical paths does not increase, but the cross-sectional area of the main surface side connection conductor is larger than that of the band-shaped pattern. Low resistance can be achieved.

  Note that if the contact area between the main surface side connection conductor and the core substrate main surface side conductor is increased, the connection reliability between the main surface side connection conductor and the core substrate main surface side conductor is increased. As a method for increasing the contact area between the two, for example, the main surface side connecting conductor may be joined on two surfaces of the core substrate main surface side conductor, that is, a side surface and an upper surface. Similarly, if the contact area between the main surface side connection conductor and the capacitor main surface side electrode is increased, the connection reliability between the main surface side connection conductor and the capacitor main surface side electrode is increased. As a method for increasing the contact area between the two, for example, the main surface side connection conductor may be joined on two surfaces of the capacitor main surface side electrode, that is, the side surface and the upper surface.

  By the way, as described above, when the main surface side connection conductor is joined to the core substrate main surface side conductor and the capacitor main surface side electrode on a plurality of surfaces, a concave portion is formed on the upper surface of the main surface side connection conductor. there is a possibility. In this case, it is preferable that the concave portion formed at the location of the main surface side connection conductor is filled with an insulating material and the upper surface thereof is flattened. In this way, it is possible to form a conductor layer on the upper surface of the main surface side connecting conductor that has been flattened with the recesses removed, and the degree of freedom of wiring in the wiring laminated portion is improved.

  The performance of the semiconductor integrated circuit element in means 2 increases as power is supplied to the center. In this case, it is preferable that the plurality of via conductors and the capacitor main surface side electrode are disposed immediately below a substantially central portion of the semiconductor integrated circuit element to be mounted on the surface of the wiring laminated portion. In this way, the current is concentrated at substantially the center of the semiconductor integrated circuit element, so that the performance of the semiconductor integrated circuit element is improved. As the performance of the semiconductor integrated circuit element is improved, more reliable power supply to the semiconductor integrated circuit element is required. For this reason, the capacitor main surface side electrode is formed from directly below the central portion of the semiconductor integrated circuit element to be mounted on the surface of the wiring laminated portion to the outer peripheral direction of the capacitor, and the main surface side connection It is preferable to be connected to the core substrate main surface side conductor via a conductor. In this way, an electrical path that connects to the semiconductor integrated circuit element through the core substrate main surface side conductor, the main surface side connection conductor, and the capacitor main surface side electrode is formed. Power can be reliably supplied to the semiconductor integrated circuit element.

[First Embodiment]

  Hereinafter, a first embodiment in which a wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of this embodiment is a wiring board for mounting an IC chip, and includes a substantially rectangular plate-like core board 11 and a core main surface 12 of the core board 11 (in FIG. 1). The first wiring laminated portion formed on the upper surface) and the second wiring laminated portion formed on the core back surface 13 (lower surface in FIG. 1) of the core substrate 11. The first wiring laminated portion is constituted by an epoxy resin lowermost resin insulating layer 33 that forms the lowermost layer of the first wiring laminated portion, and a first buildup layer 31 formed on the lowermost resin insulating layer 33. Has been. On the other hand, the second wiring laminated portion is composed of an uppermost resin insulating layer 34 made of epoxy resin that forms the uppermost layer of the second wiring laminated portion, and a second buildup layer 32 formed on the uppermost resin insulating layer 34. Has been.

  Via conductors 47 are formed at a plurality of locations in the lowermost resin insulation layer 33 constituting the first wiring laminated portion. The first buildup layer 31 constituting the first wiring laminated portion has a structure in which resin insulating layers 35 (so-called interlayer insulating layers) made of epoxy resin and conductor layers 42 made of copper are alternately laminated. ing. The conductor layer 42 is electrically connected to the via conductor 47 and the like. In addition, via conductors 43 are formed at a plurality of locations in the resin insulation layer 35, and terminal pads 44 are formed in an array on the surface of the resin insulation layer 35 at the upper end of each via conductor 43. ing. Further, the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 (semiconductor integrated circuit element). The IC chip 21 has a rectangular flat plate shape and is made of silicon. Each terminal pad 44 and each solder bump 45 are located in a region immediately above the ceramic capacitor 101 in the first buildup layer 31, and this region becomes the IC chip mounting region 23. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. That is, the IC chip 21 can be mounted on the surface 39.

  As shown in FIG. 1, the second wiring laminated portion has substantially the same structure as the first wiring laminated portion described above. That is, via conductors 47 are formed at a plurality of locations in the uppermost resin insulation layer 34 constituting the second wiring laminated portion. Further, the second buildup layer 32 constituting the second wiring laminated portion has a structure in which a resin insulating layer 36 (so-called interlayer insulating layer) made of an epoxy resin and a conductor layer 42 are alternately laminated. . The conductor layer 42 is electrically connected to the via conductor 47 and the like. In addition, via conductors 43 are formed at a plurality of locations in the resin insulation layer 36, and the conductor layer 42 is disposed on the lower surface of the resin insulation layer 36 at the lower end of each via conductor 43 via the via conductors 43. BGA pads 48 that are electrically connected to each other are formed in a grid pattern. Further, the lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (mother board) (not shown). The wiring board 10 is mounted on a mother board (not shown) by each solder bump 49. That is, a mother board can be connected to the surface of the second buildup layer 32.

  As shown in FIG. 1, the core substrate 11 includes a base material 201 made of glass epoxy and a sub-base material made of an epoxy resin formed on the upper and lower surfaces of the base material 201 and added with an inorganic filler such as silica filler. 204 and the conductor layer 203 made of copper, which is also formed on the upper and lower surfaces of the base material 201. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 203. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the core substrate 11, and is electrically connected to the conductor layer 203. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the lowermost resin insulation layer 33, and the lower end of the through-hole conductor 16 is on the lower surface of the uppermost resin insulation layer 34. Is electrically connected to a part of the conductor layer 42. In addition, the core substrate 11 has one accommodation hole 90 that is rectangular in a plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole.

  As shown in FIGS. 1 to 3, a core substrate main surface side power source pattern 51 (core substrate main surface side conductor) made of copper is disposed on the core main surface 12 of the core substrate 11. 11, a core substrate back surface side ground pattern 52 (core substrate back surface side conductor) which is also made of copper is disposed. The core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are electrically connected to the through-hole conductor 16. The core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are formed to be thicker than the conductor layer 42. In the present embodiment, the thickness of the conductor layer 42 is set to 25 μm, and the thicknesses of the core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are set to 35 μm. The core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are plain conductors formed in a rectangular frame shape so as to surround the opening edge of the accommodation hole 90 (see FIG. 2). The outer peripheral edges of the core substrate main surface side power supply pattern 51 and the core substrate rear surface side ground pattern 52 are located inside the outer peripheral edges of the core main surface 12 and the core back surface 13 of the core substrate 11, and The inner peripheral edges of the surface-side power supply pattern 51 and the core substrate rear surface side ground pattern 52 are located on the outer peripheral side of the core substrate 11 with respect to the opening edge of the accommodation hole 90.

  The ceramic capacitor 101 shown in FIGS. 4 to 6 and the like is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view of 6.0 mm length × 12.0 mm width × 0.8 mm thickness. In addition, it is preferable that the thickness of the ceramic capacitor 101 is 0.2 mm or more and 1.0 mm or less. If the thickness is less than 0.2 mm, the stress at the time of bonding the IC chip 21 onto the IC chip mounting region 23 cannot be reduced by the ceramic capacitor 101, which is insufficient as a support. On the other hand, if it is larger than 1.0 mm, the wiring board 10 becomes thick. More preferably, the thickness of the ceramic capacitor 101 is 0.4 mm or more and 0.8 mm or less. The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101. Note that the size relationship of the areas is not limited, and the area of the IC chip mounting region 23 may be larger than the area of the capacitor main surface 102.

  As shown in FIGS. 1, 4 to 6, and the like, the ceramic capacitor 101 of the present embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like object having a capacitor main surface 102 (upper surface in FIG. 1) and a capacitor back surface 103 (lower surface in FIG. 1). The lowermost resin insulation layer 33 is formed on the capacitor main surface 102 of the ceramic sintered body 104, and the uppermost resin insulation layer 34 is formed on the capacitor back surface 103 of the ceramic sintered body 104. The ceramic sintered body 104 has a structure in which the first internal electrode layers 141 and the second internal electrode layers 142 are alternately stacked via the ceramic dielectric layer 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. The upper end surfaces of the via conductors 131 and 132 are located on the capacitor main surface 102, and the lower end surfaces of the via conductors 131 and 132 are located on the capacitor back surface 103. Each power supply via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each ground via conductor 132 passes through each second internal electrode layer 142 and electrically connects them to each other. Each power supply via conductor 131 and each ground via conductor 132 are arranged in an array as a whole. For convenience of explanation, the via conductors 131 and 132 are illustrated in 5 columns × 5 columns, but there are actually more columns.

  As shown in FIGS. 2, 4 to 6, and the like, on the capacitor main surface 102 of the ceramic sintered body 104, an upper surface side power supply electrode 111 (first capacitor main surface side electrode) and a plurality of upper surfaces are formed. A side ground electrode 112 (second capacitor main surface side electrode) is projected. Further, on the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power supply electrodes 121 (first capacitor back surface side electrodes) and back surface side ground electrodes 122 (second capacitor back surface side electrodes) protrude. It is installed. Here, the upper surface side power supply electrode 111 is a plain conductor that covers substantially the entire capacitor main surface 102, and has a plurality of holes for avoiding the upper surface side ground electrodes 112. Similarly, the back surface side power supply electrode 121 is a plain conductor that covers substantially the entire capacitor back surface 103, and has a plurality of holes for avoiding each back surface side ground electrode 122. Note that the outer peripheral edges of the upper surface side power supply electrode 111 and the rear surface side power supply electrode 121 are located inside the outer peripheral edges of the capacitor main surface 102 and the capacitor back surface 103 of the ceramic capacitor 101 (see FIG. 2). The upper surface side ground electrodes 112 are band-shaped patterns arranged in parallel with each other on the capacitor main surface 102, and the rear surface side ground electrodes 122 are band-shaped patterns arranged in parallel with each other on the capacitor back surface 103. . The electrodes 111 and 112 on the capacitor main surface 102 side include the via conductor 47, the first buildup layer 31 (conductor layer 42, via conductor 43), the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. And is electrically connected to the IC chip 21. On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side pass through via conductors 47, conductor layers 42, via conductors 43, BGA pads 48, and solder bumps 49 with respect to electrodes (contactors) of a mother board (not shown). Are electrically connected. The upper surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply via conductors 131 on the capacitor main surface 102 side, and the upper surface side ground electrode 112 is connected to the plurality of ground via conductors 132. It is directly connected to the end surface on the capacitor main surface 102 side. On the other hand, the back side power supply electrode 121 is directly connected to the end face of the plurality of power supply via conductors 131 on the capacitor back side 103 side, and the back side ground electrode 122 is a capacitor in the plurality of ground via conductors 132. It is directly connected to the end surface on the back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply via conductor 131 and the first internal electrode layer 141, and the ground electrodes 112 and 122 are electrically connected to the ground via conductor 132 and the second internal electrode layer 142. Yes.

  As shown in FIG. 4 and the like, the electrodes 111 and 112 are made of nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). Similarly, the electrodes 121 and 122 are also made of nickel as a main material, and the surfaces thereof are covered with a copper plating layer (not shown). The electrodes 121 and 122 and the via conductors 131 and 132 are disposed immediately below the central portion of the IC chip 21. The upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are formed from a position just below the central portion of the IC chip 21 to the outer peripheral direction of the ceramic capacitor 101. The upper surface side power supply electrode 111 and the rear surface side ground electrode 122 are also arranged on the outer periphery of the capacitor.

  For example, when energization is performed from the motherboard side via the electrodes 121 and 122 and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, for example, positive charges are accumulated in the first internal electrode layer 141. For example, negative charges accumulate in the second internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the power supply via conductors 131 and the ground via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the power supply via conductors 131 and the ground via conductors 132 are opposite to each other. It is set to be. Thereby, the inductance component is reduced.

  As shown in FIGS. 1 to 3, etc., the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled with a resin filling portion 33 a constituting a part of the lowermost resin insulating layer 33. ing. The resin filling portion 33a has a function of fixing the ceramic capacitor 101 to the core substrate 11 and absorbing the deformation of the ceramic capacitor 101 and the core substrate 11 in the surface direction and the thickness direction by its own elastic deformation. . The ceramic capacitor 101 has a substantially square shape in plan view, and has a taper of C0.6 at the four corners. Thereby, when the resin filling portion 33a is deformed due to a temperature change, stress concentration on the corner portion of the ceramic capacitor 101 can be relieved, so that occurrence of cracks in the resin filling portion 33a can be prevented.

  The resin filling portion 33 a has a main surface side wiring formation portion 93 located on the core main surface 12 of the core substrate 11 and the capacitor main surface 102 side of the ceramic capacitor 101. Further, the resin filling portion 33 a has a back surface side wiring forming portion 94 located on the core back surface 13 of the core substrate 11 and the capacitor back surface 103 side of the ceramic capacitor 101. An upper surface side connection pattern 61 (main surface side connection conductor) is arranged on the main surface side wiring formation portion 93. The upper surface side connection pattern 61 is a belt-like pattern arranged on each side of the ceramic capacitor 101 (see FIG. 2), and the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are connected to each other. It comes to connect. More specifically, one end of the upper surface side connection pattern 61 is bonded to the side surface 53 (inner peripheral surface) and the upper surface 54 of the core substrate main surface side power supply pattern 51, and the other end of the upper surface side connection pattern 61 is used for the upper surface side power supply. The electrodes 111 are joined at the side surface (outer peripheral surface) and the upper surface (see FIG. 3). In addition, the upper surface side connection pattern 61 of this embodiment consists of a copper plating layer, and the upper surface is flat.

  As shown in FIGS. 1 and 3, a back side connection pattern 62 (back side connection conductor) is arranged on the back side wiring formation portion 94. The back surface side connection pattern 62 has substantially the same configuration as the top surface side connection pattern 61. That is, the back surface side connection pattern 62 is a belt-like pattern arranged on each of the four sides of the ceramic capacitor 101 so as to connect the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122. It has become. More specifically, the back surface side connection pattern 62 is bonded at the side surface (inner peripheral surface) and the lower surface of the core substrate back surface side ground pattern 52 and at the side surface (outer peripheral surface) and the lower surface of the back surface side ground electrode 122. is doing. In addition, the back surface side connection pattern 62 of this embodiment consists of a copper plating layer, and the lower surface is flat.

  With the above configuration, a plurality of electrical paths (a first power path and a second power path) for supplying power to the IC chip 21 are formed in the wiring board 10. The first power supply path is a path that connects to the upper surface side power supply electrode 111 through the through-hole conductor 16, the core substrate main surface side power supply pattern 51, and the upper surface side connection pattern 61. The second power supply path is a path connected to the upper surface side power supply electrode 111 through the via conductor 131. The upper surface side power supply electrode 111 is connected via the via conductor 47, the first buildup layer 31 (conductor layer 42, via conductor 43), the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. It is electrically connected to the IC chip 21.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the preparation step, the core substrate 11 and the ceramic capacitor 101 are respectively prepared by a conventionally known technique and prepared in advance.

  The core substrate 11 is manufactured as follows. First, a copper clad laminate (see FIG. 7) in which a copper foil 202 having a thickness of 35 μm is attached to both surfaces of a base material 201 having a length of 400 mm × width of 400 mm × thickness of 0.8 mm is prepared. In addition, it is preferable that the thickness of the base material 201 is 0.2 mm or more and 1.0 mm or less. Next, the copper foil 202 on both sides of the copper-clad laminate is etched to pattern the conductor layer 203 by, for example, a subtractive method (see FIG. 8). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 202 are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 201 and the conductor layer 203, an epoxy resin film (thickness 600 μm) to which an inorganic filler is added is pasted on the upper and lower surfaces of the base material 201 by thermocompression bonding. Then, the sub-base material 204 is formed (see FIG. 9).

  Next, the core substrate main surface side power supply pattern 51 is formed on the upper surface of the upper sub base material 204, and the core substrate back surface side ground pattern 52 is formed on the lower surface of the lower sub base material 204 (FIG. 10). reference). Specifically, after performing electroless copper plating on the upper surface of the upper sub-substrate 204 and the lower surface of the lower sub-substrate 204, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 201 and the sub-base material 204 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions, thereby obtaining the core substrate 11 (FIG. 11). In addition, the through-hole used as the accommodation hole part 90 is a hole of 14.0 mm in length x 30.0 mm in width | variety, and a cross-sectional substantially square shape which has a radius of 1.5 mm in four corners.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, paste is printed on the upper surface of the green sheet laminate, and the upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are formed so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. To do. Further, a paste is printed on the lower surface of the green sheet laminate, and the back-side power supply electrode 121 and the back-side ground electrode 122 are formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify the electrodes 111, 112, 121, and 122 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electroless copper plating (thickness of about 10 μm) is performed on each electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  In the subsequent insulating layer formation and fixing step, the ceramic capacitor 101 is accommodated in the accommodation hole 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 12). At this time, the opening on the core back surface 13 side of the accommodation hole 90 is sealed with a peelable adhesive tape 210. The adhesive tape 210 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 210.

  Thereafter, a photosensitive epoxy resin is applied to the core main surface 12 and the capacitor main surface 102, and the lowest resin insulation layer 33 is formed by performing exposure and development. In addition, the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled with the resin filling portion 33a which is a part of the lowermost resin insulating layer 33 (see FIG. 13). Thereafter, when heat treatment is performed, the lowermost resin insulating layer 33 and the resin filling portion 33 a are cured, and the ceramic capacitor 101 is fixed to the core substrate 11. At this point, the adhesive tape 210 is peeled off.

  Next, a photosensitive epoxy resin is applied to the core back surface 13 and the capacitor back surface 103, and exposure and development are performed to form the uppermost resin insulating layer 34 (see FIG. 14). In the subsequent opening forming step, laser drilling is performed using a YAG laser or a carbon dioxide gas laser, and openings 221 and 222 are formed at positions where the upper surface side connection pattern 61 and the rear surface side connection pattern 62 are to be formed, respectively. (See FIG. 15). Specifically, the opening 221 is formed by removing the position directly above the gap in the lowermost resin insulation layer 33 to form one of the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111. Expose the part. When the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are different in height, the bottom surface of the opening 221 is made lower than the lower upper surface to expose the both. Similarly, the position immediately below the gap in the uppermost resin insulation layer 34 is entirely removed to form an opening 222 to expose a part of the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122. . When the heights of the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122 are different from each other, the bottom surface of the opening 222 is made higher than the higher lower surface to expose the both. In addition, via holes 223 for exposing the upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are formed at positions where the via conductors 47 are to be formed in the lowermost resin insulating layer 33. Also, via holes 224 that expose the back-side power supply electrode 121 and the back-side ground electrode 122 are formed at positions where the via conductors 47 are to be formed in the uppermost resin insulation layer 34.

  Further, drilling is performed using a drill machine, and a through hole 231 that penetrates the core substrate 11 and the resin insulating layers 33 and 34 is formed in advance at a predetermined position (see FIG. 16). And a main surface side connection conductor formation process and a back surface side connection conductor formation process are implemented (refer FIG. 17). Specifically, after performing electroless copper plating on the lowermost resin insulating layer 33, the uppermost resin insulating layer 34, the inner surfaces of the openings 221, 222, and the inner surfaces of the through holes 231, an etching resist is formed, and then electrolysis is performed. Perform copper plating. Further, the etching resist is removed and soft etching is performed. As a result, the upper surface side connection pattern 61 is formed in the opening 221, and the back surface side connection pattern 62 is formed in the opening 222, and the conductor layer is formed on the lowermost resin insulating layer 33 and the uppermost resin insulating layer 34. 42 is patterned. At the same time, the through-hole conductor 16 is formed in the through hole 231, and the via conductor 47 is formed inside each via hole 223, 224. As a result, the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are connected by the upper surface side connection pattern 61, and the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122 are connected by the back surface side connection pattern 62. Is done.

  After the main surface side connecting conductor forming step and the back surface side connecting conductor forming step, a hole filling step is performed. Specifically, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form a closing body 17 (see FIG. 18).

  Next, a buildup layer forming step is performed. In the buildup layer forming step, the first buildup layer 31 is formed on the lowermost resin insulation layer 33 and the second buildup layer 32 is formed on the uppermost resin insulation layer 34 based on a conventionally known method. To do. Specifically, a resin epoxy layer having blind holes 251 and 252 at positions where via conductors 43 are to be formed by depositing a photosensitive epoxy resin on resin insulation layers 33 and 34, and performing exposure and development. 35 and 36 are formed (see FIG. 18). Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 in the blind holes 251 and 252, and terminal pads 44 are formed on the resin insulation layer 35, and the resin insulation layer 36 is formed on the resin insulation layer 36. A BGA pad 48 is formed.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. As a result, the wiring substrate 10 including the core substrate 11 and the buildup layers 31 and 32 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the wiring board 10 of the present embodiment, the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are connected by the upper surface side connection pattern 61, thereby 51, an electrical path (first power path) that connects to the IC chip 21 through the upper surface side connection pattern 61, the upper surface side power supply electrode 111, and the first wiring laminated portion is formed. As a result, the number of electrical paths connected to the IC chip 21 increases, so that the resistance in the wiring board 10 is reduced and the voltage drop is reduced. Therefore, since the power can be reliably supplied to the IC chip 21, the IC chip 21 can be sufficiently operated, and the malfunction of the IC chip 21 can be prevented. Therefore, the wiring board 10 having excellent electrical characteristics and reliability can be obtained.

  (2) Since the resin filling portion of the present embodiment is a resin filling portion 33a constituting a part of the lowermost resin insulating layer 33, a material different from that of the lowermost resin insulating layer 33 is used when forming the resin filling portion. No need to prepare. Therefore, since the material necessary for manufacturing the wiring board 10 is reduced, the cost of the wiring board 10 can be reduced.

  (3) By the way, it is conceivable to supply power to the IC chip 21 through a path connected to the IC chip 21 through the through-hole conductor 16, the via conductor 47, the conductor layer 42, the via conductor 43 and the terminal pad 44. . However, since the conductor layer 42 is thin and has high resistance, a voltage drop during power supply is large, and it is difficult to supply sufficient power to the IC chip 21.

  On the other hand, in this embodiment, as a power supply to the IC chip 21, a path (first power supply path) passing through the core substrate main surface side power supply pattern 51 is formed. Since the core substrate main surface side power supply pattern 51 is formed thicker than the conductor layer 42 constituting the buildup layers 31 and 32, the resistance of the core substrate main surface side power supply pattern 51 is small, and power supply is performed. The voltage drop is small. As a result, a large current can flow through the power supply pattern 51 on the core substrate main surface side, so that sufficient power supply to the IC chip 21 is possible.

(4) The IC chip 21 of the present embodiment is disposed immediately above the ceramic capacitor 101. Thereby, the conduction | electrical_connection path | route which electrically connects IC chip 21 and the ceramic capacitor 101 becomes the shortest. Therefore, the power supply to the IC chip 21 can be performed smoothly. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.
[Second Embodiment]

  Hereinafter, a second embodiment embodying the wiring board of the present invention will be described in detail with reference to the drawings.

  As shown in FIGS. 19 and 20, the wiring board 10 </ b> A of the present embodiment is a resin filling portion 92 that is different from the resin filling portion 33 a in which the resin filling portion forms part of the lowermost resin insulating layer 33. This is different from the first embodiment. The resin filling portion 92 is made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). Therefore, the manufacturing method of the wiring board 10A of the present embodiment is also different from that of the first embodiment.

  That is, in this embodiment, when the ceramic capacitor 101 is temporarily fixed, the resin filling is performed without forming the lowermost resin insulating layer 33 on the core main surface 12 of the core substrate 11 and the capacitor main surface 102 of the ceramic capacitor 101. The portion 92 is filled (see FIG. 19). Specifically, using a dispenser device (manufactured by Asymtek) in the gap between the inner surface of the housing hole 90 and the side surface of the ceramic capacitor 101, a resin filling portion 92 made of thermosetting resin (underfill made by NAMICS Co., Ltd.) Material). At this time, the resin filling portion 92 is filled until the main surface side wiring formation portion 93 is at the same height as the core main surface 12 and the capacitor main surface 102. Thereafter, when heat treatment is performed, the resin filling portion 92 is cured and the ceramic capacitor 101 is fixed in the accommodation hole 90.

  Next, an insulating layer forming step is performed, and the lowermost resin insulating layer 33 is formed on the core main surface 12, the capacitor main surface 102, and the resin filling portion 92 (see FIG. 19). Further, an opening forming step for the lowermost resin insulating layer 33 is performed to form the opening 221 and the via hole 223 (see FIG. 20). At this time, the adhesive tape 210 is peeled off, and the uppermost resin insulation layer 34 is formed on the core back surface 13 of the core substrate 11 and the capacitor back surface 103 of the ceramic capacitor 101.

  Therefore, in this embodiment, since the resin filling portion 92 is different from the lowermost resin insulating layer 33, the resin filling portion 92 can be formed of a material that is optimal for fixing the ceramic capacitor 101. Therefore, since the ceramic capacitor 101 is firmly fixed, the connection reliability of the upper surface side connection pattern 61 formed on the resin filling portion 92 is improved.

  In addition, you may change this embodiment as follows.

  In the second embodiment, after the filling of the resin filling portion 92 and the formation of the lowermost resin insulating layer 33 are finished, the opening 221 is formed in the lowermost resin insulating layer 33 to form the upper surface side connection pattern 61. Was. However, when the filling of the resin filling portion 92 is completed (see FIG. 21), on the main surface side wiring formation portion 93 (between the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111). The upper surface side connection pattern 61 may be formed (see FIG. 22), and then the lowermost resin insulating layer 33 may be formed. In this case, the upper surface side connection pattern 61 has a flat plate shape and has the same thickness as the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111. That is, one end of the upper surface side connection pattern 61 is bonded only to the side surface 53 of the core substrate main surface side power supply pattern 51, and the other end of the upper surface side connection pattern 61 is bonded only to the side surface of the upper surface side power supply electrode 111.

  The accommodation hole 90 in the above embodiment is a through hole that opens on both the core main surface 12 side and the core back surface 13 side of the core substrate 11, but the wiring substrate of another embodiment shown in FIG. The non-through-hole part opened only in the core main surface 12 like 10B may be sufficient.

  In the first embodiment, the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled only with the resin filling portion 33 a that constitutes a part of the lowermost resin insulating layer 33. However, like the wiring board 10C of another embodiment shown in FIG. 24, the gap constitutes a resin filling portion 33a constituting a part of the lowermost resin insulating layer 33 and a part of the uppermost resin insulating layer 34. It may be filled with the resin filling portion 33b.

  In this case, with the ceramic capacitor 101 temporarily fixed, the lowermost resin insulating layer 33 is formed on the core main surface 12 of the core substrate 11 and the capacitor main surface 102 of the ceramic capacitor 101, and the housing hole is formed by the resin filling portion 33a. The upper half of the gap between the inner surface of the portion 90 and the side surface of the ceramic capacitor 101 is filled (see FIG. 25). At this point, the adhesive tape 210 is peeled off. Next, the uppermost resin insulation layer 34 is formed on the core back surface 13 of the core substrate 11 and the capacitor back surface 103 of the ceramic capacitor 101, and the lower half of the gap is filled with the resin filling portion 33b (see FIG. 26).

  In the above embodiment, when the openings 221 and 222 are formed at the positions where the upper surface side connection pattern 61 and the rear surface side connection pattern 62 are to be formed, respectively, the inner surfaces of the accommodation holes 90 and the resin insulating layers 33 and 34 The position directly above and below the gap with the side surface of the ceramic capacitor 101 has been entirely removed. However, when forming the openings 221, 222, the resin insulation layers 33, 34 may be partially removed at positions directly above and below the gap. That is, if at least a part of the position immediately above and the position immediately below is removed, the upper surface side connection pattern 61 and the back surface side connection pattern 62 can be formed.

  In the above embodiment, the upper surface side connection pattern 61 and the back surface side connection pattern 62 have a flat upper surface (or lower surface). However, as shown in FIGS. 27 and 34, the upper surface side connection pattern 61 and the back surface side connection pattern 62 may be conductors having a recess 63. Further, as in the wiring substrate 10D shown in FIG. 27, each recess 63 is filled with the same insulating material as the insulating resin material (blocking body 17) that fills the cavity of the through-hole conductor 16, and the upper surface thereof is flattened. May be. In this way, the conductor layer 64 can be formed on the upper surface of the upper surface side connection pattern 61 and the rear surface side connection pattern 62, and the degree of freedom of wiring in the wiring laminated portion is improved.

  In the above embodiment, one upper surface side connection pattern 61 is arranged on each side of the ceramic capacitor 101. However, as shown in FIG. It may be arranged one by one (two in FIG. 28). In this way, both the upper surface side power supply electrode 111 and the upper surface side ground electrode 112 can be formed in a strip pattern arranged in parallel to each other.

  In the above embodiment, one upper surface side connection pattern 61 is arranged on each side of the ceramic capacitor 101. However, as shown in FIG. 29, a plurality of upper side connection patterns 61 are provided on each side of the ceramic capacitor 101A (FIG. 29). Then two may be arranged).

  In the above embodiment, the upper surface side connection pattern 61 is a belt-like pattern, but like the ceramic capacitor 101B shown in FIG. 30, the upper surface side connection pattern 61 covers the entire area of the main surface side wiring formation portion 93. It may be a rectangular frame-shaped pattern arranged on the screen.

  In the above embodiment, the outer peripheral edges of the upper surface side power supply electrode 111 and the rear surface side power supply electrode 121 are located inside the outer peripheral edges of the capacitor main surface 102 and the capacitor back surface 103 of the ceramic capacitor 101. 31, 34, and 35, the capacitor main surface 102 and the capacitor back surface 103 may be at the same position as the outer peripheral edge. That is, the outer peripheral surface of the upper surface side power supply electrode 111 and the back surface side power supply electrode 121 may be flush with the side surface of the ceramic capacitor 101.

  As shown in FIGS. 32 and 33, the upper surface side connection pattern 61 may be a flat plate shape, and the upper surface side connection pattern 61 (upper part of the opening 221) may be filled with a resin insulating portion 241. In this case, the upper surface side connection pattern 61 and the conductor layer 42 may be electrically connected via a via conductor 242 formed in the resin insulating portion 241 (see FIG. 33).

  As shown in FIGS. 34 and 35, the outer peripheral edges of the upper surface side power supply electrode 111 and the rear surface side power supply electrode 121 are positioned at the same positions as the outer peripheral edges of the capacitor main surface 102 and the capacitor rear surface 103, and the core substrate. The inner peripheral edges of the main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 may be at the same position as the opening edge of the accommodation hole 90. That is, the outer peripheral surfaces of the upper surface side power supply electrode 111 and the back surface side power supply electrode 121 and the side surface of the ceramic capacitor 101 are flush with each other, and the core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are included. The peripheral surface and the inner surface of the accommodation hole 90 may be flush with each other. Further, in this case, the upper surface side connection pattern 61 and the back surface side connection pattern 62 may be conductors having a recess 63 (see FIG. 34), or the upper surface (or the lower surface) becomes flat without the recess 63 being formed. It may be a conductor (see FIG. 35).

  As shown in FIG. 36, when the upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are strip-shaped patterns extending in parallel on the capacitor main surface 102, they are positioned at the extended ends of the strip-shaped patterns. It is preferable to form the upper surface side connection pattern 61 on the main surface side wiring forming portion 93 in a state of straddling the main surface side wiring forming portion 93. In other words, in the ceramic capacitor 101D having a rectangular shape in plan view having four sides, it is preferable to form the upper surface side connection pattern 61 on the side where the band-like pattern extends. With this configuration, since the energization path from the upper surface side connection pattern 61 to the center of the capacitor main surface 102 via the electrodes 111 and 112 becomes linear, the wiring distance is shortened and the electrical performance is improved. Is easier to achieve.

  As shown in FIG. 36, for example, when the power source and ground pattern forming area A1 and the signal line pattern forming area A2 are separated on the core main surface 12 of the core substrate 11, the power source and ground pattern are formed. It is preferable that the upper surface side connection pattern 61 is formed on the main surface side wiring forming portion 93 adjacent to the area A1 so as to straddle it. In other words, in the rectangular ceramic capacitor 101D having four sides, the upper surface side connection pattern 61 is preferably formed on the side facing the power supply and ground pattern formation area A1. With this configuration, the path of the core substrate main surface side power supply pattern 51 and the like → the upper surface side connection pattern 61 → the electrodes 111 and 112 is shortened, and an improvement in electrical performance is easily achieved.

  The ceramic capacitor 101 of the above embodiment has a square shape in plan view, but may have a rectangular shape in plan view having a pair of long sides and a pair of short sides. In this case, it is preferable to form the upper surface side connection pattern 61 on the main surface side wiring forming portion 93 located at the position of the long side. With this configuration, since the wiring distance is shorter than when the upper surface side connection pattern 61 is formed corresponding to the short side, an improvement in electrical performance is easily achieved.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiments described above are listed below.

  (1) a core substrate having a core main surface and a core back surface, in which an accommodation hole opening at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface; A plurality of internal conductors having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, and being stacked on and connected to the plurality of via conductors via a dielectric layer; A via array type capacitor having an electrode layer and having a capacitor main surface side electrode disposed on the capacitor main surface and connected to ends of the plurality of via conductors; and the capacitor accommodated in the accommodating hole; A wiring layer having a structure in which a resin-filled portion that fills a gap with the core substrate and fixes the capacitor to the core substrate, and an interlayer insulating layer and a conductor layer are stacked on the core main surface and the capacitor main surface. The resin filling portion has a main surface side wiring formation portion located on the core main surface and the capacitor main surface side, and the core substrate main surface side on the main surface side wiring formation portion A wiring board, wherein a main surface side connecting conductor for connecting a conductor and the capacitor main surface side electrode is disposed.

  (2) a core substrate having a core main surface and a core back surface, in which an accommodation hole opening at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface; A plurality of internal conductors having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, and being stacked on and connected to the plurality of via conductors via a dielectric layer; A ceramic capacitor having an electrode layer and having a capacitor main surface side electrode disposed on the capacitor main surface and connected to end portions of the plurality of via conductors, the ceramic capacitor and the core accommodated in the accommodating hole A resin-filled portion that fills the gap with the substrate and fixes the ceramic capacitor to the core substrate, and has a structure in which an interlayer insulating layer and a conductor layer are stacked on the core main surface and the capacitor main surface. And the resin filling portion has a main surface side wiring formation portion located on the core main surface and the capacitor main surface side, and the core is disposed on the main surface side wiring formation portion. A wiring board, wherein a main surface side connection conductor for connecting a substrate main surface side conductor and the capacitor main surface side electrode is disposed.

  (3) a core substrate having a core main surface and a core back surface, in which an accommodation hole opening at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface; A plurality of internal conductors having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, and being stacked on and connected to the plurality of via conductors via a dielectric layer; A capacitor having an electrode layer and having a capacitor main surface side electrode disposed on the capacitor main surface and connected to ends of the plurality of via conductors; the capacitor housed in the housing hole; and the core substrate; A resin filling portion for filling the gap and fixing the capacitor to the core substrate, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface, Tree The filling portion has a main surface side wiring formation portion located on the core main surface and the capacitor main surface side, and the core substrate main surface side conductor and the capacitor main surface are disposed on the main surface side wiring formation portion. A main surface side connecting conductor for connecting the side electrode, a plurality of through-hole conductors formed so as to penetrate the core main surface and the core back surface, the core substrate main surface side conductor, and the A first power supply path connected to the capacitor main surface side electrode through a main surface side connection conductor, and a second power supply path connected to the capacitor main surface side electrode through the plurality of via conductors. Wiring board.

  (4) a core substrate having a core main surface and a core back surface, in which a housing hole portion that is opened at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface; A plurality of internal conductors having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, and being stacked on and connected to the plurality of via conductors via a dielectric layer; A capacitor having an electrode layer and having a capacitor main surface side electrode disposed on the capacitor main surface and connected to ends of the plurality of via conductors; the capacitor housed in the housing hole; and the core substrate; A resin-filled portion that fills the gap and fixes the capacitor to the core substrate, and a build-up layer having a structure in which an interlayer insulating layer and a conductor layer are stacked on the core main surface and the capacitor main surface. The resin-filled portion has a main surface side wiring forming portion located on the core main surface and the capacitor main surface side, and the core substrate main surface side conductor and the capacitor main surface are formed on the main surface side wiring forming portion. A wiring board comprising a main surface side connection conductor for connecting a surface side electrode.

  (5) A core substrate having a core main surface and a core back surface, in which an accommodation hole opening at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface; A plurality of internal conductors having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, and being stacked on and connected to the plurality of via conductors via a dielectric layer; A capacitor having an electrode layer and having a capacitor main surface side electrode disposed on the capacitor main surface and connected to ends of the plurality of via conductors; the capacitor housed in the housing hole; and the core substrate; A resin filling portion for filling the gap and fixing the capacitor to the core substrate, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface, Tree The filling portion has a main surface side wiring formation portion located on the core main surface and the capacitor main surface side, and the core substrate main surface side conductor and the capacitor main surface are disposed on the main surface side wiring formation portion. A wiring board, wherein a main surface side connection conductor for connecting to a side electrode is disposed, and the main surface side connection conductor is a copper plating layer.

  (6) In any one of the above (1) to (5), the capacitor has a substantially rectangular shape in plan view, and the capacitor main surface side electrode has a belt-like pattern extending in parallel on the capacitor main surface. And the main-surface-side connecting conductor is arranged on each side of the capacitor, which is located on the side where the band-shaped pattern extends.

  (7) In any one of the above (1) to (6), the power and ground pattern formation area and the signal line pattern formation area are separated on the core main surface of the core substrate, and the capacitor is viewed in plan view. And the main surface side connection conductor is formed on a side adjacent to the power supply and ground pattern formation area among the sides of the capacitor.

  (8) In any one of the above (1) to (7), the capacitor has a rectangular shape in plan view having a pair of long sides and a pair of short sides, and the main surface side connection conductor is on the long side. A wiring board which is formed.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. Similarly, the schematic plan view which shows the relationship between a core board | substrate, a ceramic capacitor, an upper surface side connection pattern, etc. FIG. Similarly, principal part sectional drawing for demonstrating the connection by an upper surface side connection pattern. Similarly, the schematic sectional drawing which shows a ceramic capacitor. Similarly, the schematic plan view which shows the upper surface of a ceramic capacitor. Similarly, the schematic plan view which shows the lower surface of a ceramic capacitor. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of the wiring board in 2nd Embodiment. Similarly, explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. The schematic plan view which shows the relationship between the core board | substrate in other embodiment, a ceramic capacitor, and an upper surface side connection pattern. The schematic plan view which shows the relationship between the core board | substrate in other embodiment, a ceramic capacitor, and an upper surface side connection pattern. The schematic plan view which shows the relationship between the core board | substrate in other embodiment, a ceramic capacitor, and an upper surface side connection pattern. The schematic plan view which shows the relationship between the core board | substrate in other embodiment, a ceramic capacitor, and an upper surface side connection pattern. The principal part sectional drawing for demonstrating the connection by the upper surface side connection pattern in other embodiment. The principal part sectional drawing for demonstrating the connection by the upper surface side connection pattern in other embodiment. The principal part sectional drawing for demonstrating the connection by the upper surface side connection pattern in other embodiment. The principal part sectional drawing for demonstrating the connection by the upper surface side connection pattern in other embodiment. The principal part top view for demonstrating the connection by the upper surface side connection pattern in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A, 10B, 10C, 10D ... Wiring board 11 ... Core board 12 ... Core main surface 13 ... Core back surface 16 ... Through-hole conductor 21 ... IC chip 31 as a semiconductor integrated circuit element ... Wiring lamination part and 1st wiring lamination First buildup layer 32 constituting the second part ... second buildup layer 33 constituting the second wiring laminated part ... lowermost resin insulating layers 33a, 92 ... resin filling part constituting the wiring laminated part and the first wiring laminated part 34 ... Uppermost resin insulating layers 35, 36 constituting the second wiring laminated portion ... Resin insulating layer 39 as an interlayer insulating layer ... Surface 42 of the wiring laminated portion ... Conductor layer 51 ... Core substrate main as a core substrate main surface side conductor Surface side power supply pattern 52 ... Core substrate back side ground pattern 53 as a core substrate back side conductor ... Side surface 54 of the core board main side conductor ... Upper surface 61 of the core board main side conductor ... Main side connection conductor Upper surface side connection pattern 62... Rear surface side connection pattern 63 as a back surface side connection conductor... Concave portion 90 .. accommodation hole 93 .. main surface side wiring formation portion 94 .. back surface side wiring formation portion 101, 101A, 101B, 101C, DESCRIPTION OF SYMBOLS 101D ... Ceramic capacitor 102 as a capacitor ... Capacitor main surface 103 ... Capacitor back surface 105 ... Ceramic dielectric layer 111 as a dielectric layer ... Upper surface side power supply electrode 112 as a capacitor main surface side electrode and a first capacitor main surface side electrode ... upper surface side ground electrode 121 as capacitor main surface side electrode and second capacitor main surface side electrode ... back surface side power supply electrode 122 as capacitor back surface side electrode and first capacitor back surface side electrode ... capacitor back surface side electrode and second Back side ground electrode 131 as capacitor back side electrode ... Electricity as via conductor Via conductor 132 for ground Via conductor 141 as a via conductor First internal electrode layer 142 as an internal electrode layer Second internal electrode layer T1 as an internal electrode layer (capacitor main surface side) end T2 ( Capacitor back side) end

Claims (13)

A core substrate having a core main surface and a core back surface, in which an accommodation hole opening at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface;
A plurality of internal conductors having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, and being stacked on and connected to the plurality of via conductors via a dielectric layer; A capacitor having an electrode layer and having a capacitor main surface side electrode disposed on the capacitor main surface;
A resin filling portion that fills a gap between the capacitor accommodated in the accommodation hole and the core substrate and fixes the capacitor to the core substrate;
A wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface;
The resin-filled portion has a main surface side wiring forming portion located on the core main surface and the capacitor main surface side, and the core substrate main surface side conductor and the via are formed on the main surface side wiring forming portion. A wiring board, wherein a main surface side connection conductor for connecting to the capacitor main surface side electrode connected to an end portion of the conductor is disposed. The core back surface has a core main surface and a core back surface, an accommodation hole is formed that opens on the core main surface side and the core back surface side, and a core substrate main surface side conductor is disposed on the core main surface. A core substrate on which a core substrate back side conductor is disposed;
A capacitor main surface and a capacitor back surface; a plurality of via conductors penetrating between the capacitor main surface and the capacitor back surface; connected to the plurality of via conductors and stacked and disposed via a dielectric layer A plurality of internal electrode layers, a capacitor main surface side electrode disposed on the capacitor main surface and connected to a capacitor main surface side end of the plurality of via conductors, and disposed on the capacitor back surface; A capacitor having a capacitor back surface side electrode connected to the capacitor back surface side end of the via conductor;
A resin filling portion that fills a gap between the capacitor accommodated in the accommodation hole and the core substrate and fixes the capacitor to the core substrate;
A first wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface, and a semiconductor integrated circuit element can be mounted on the surface;
Having a structure in which an interlayer insulating layer and a conductor layer are laminated on the back surface of the core and the back surface of the capacitor, and a second wiring laminated portion to which a mother substrate can be connected on the surface;
The resin filling portion has a main surface side wiring formation portion located on the core main surface and the capacitor main surface side, and a back surface side wiring formation portion located on the core back surface and the capacitor back surface side, A main surface side connection conductor connecting the core substrate main surface side conductor and the capacitor main surface side electrode connected to the capacitor main surface side end of the via conductor is disposed on the main surface side wiring formation portion. A back-side connection conductor that connects the core substrate back-side conductor and the capacitor back-side electrode connected to the capacitor back-side end of the via conductor is disposed on the back-side wiring formation portion. A wiring board characterized by that. The via conductor includes a plurality of power via conductors and a plurality of ground via conductors,
The plurality of internal electrode layers include a plurality of first internal electrode layers connected to the plurality of power supply via conductors and a plurality of second internal electrode layers connected to the plurality of ground via conductors,
The capacitor main surface side electrode is disposed on the capacitor main surface and is connected to end portions of the plurality of power supply via conductors. The capacitor main surface side electrode is disposed on the capacitor main surface and the plurality of grounds. A second capacitor main surface side electrode connected to the end of the via conductor for use,
The capacitor back surface side electrode is disposed on the capacitor back surface and is connected to end portions of the plurality of power supply via conductors. The capacitor back surface side electrode is disposed on the capacitor back surface and the plurality of ground via conductors. A second capacitor back side electrode connected to the end,
The main surface side connection conductor connects the core substrate main surface side power supply pattern which is the core substrate main surface side conductor and the first capacitor main surface side electrode,
The wiring substrate according to claim 2, wherein the back surface side connection conductor connects a core substrate back surface side ground pattern, which is the core substrate back surface side conductor, and the second capacitor back surface side electrode.   4. The wiring board according to claim 1, wherein the capacitor main surface side electrode or the capacitor back surface side electrode is also disposed on the outer periphery of the capacitor. 5.   The core substrate main surface side conductor is a plain-like conductor or a net-like conductor formed so as to surround the opening edge of the accommodation hole, and is formed so as to penetrate between the core main surface and the core back surface. The wiring board according to claim 1, wherein the wiring board is connected to a plurality of through-hole conductors.   6. The capacitor according to claim 1, wherein the capacitor has a substantially rectangular shape in a plan view, and the main surface side connection conductor is a belt-like pattern disposed on each side of the capacitor. The wiring board according to item.   6. The capacitor according to claim 1, wherein the capacitor has a substantially rectangular shape in plan view, and the main surface side connection conductor is a plurality of strip patterns arranged on each side of the capacitor. The wiring board described.   2. The capacitor according to claim 1, wherein the capacitor has a substantially rectangular shape in plan view, and the main surface side connection conductor is a rectangular frame pattern arranged so as to cover the entire area of the main surface side wiring formation portion. The wiring board according to any one of 1 to 5.   The wiring board according to claim 1, wherein the main surface side connection conductor is joined at a side surface and an upper surface of the core substrate main surface side conductor.   The wiring board according to claim 1, wherein the main surface side connection conductor is a plating layer.   11. The wiring board according to claim 1, wherein a concave portion formed at a location of the main surface side connection conductor is filled with an insulating material, and an upper surface thereof is flattened.   2. The plurality of via conductors and the capacitor main surface side electrode are arranged immediately below a substantially central portion of a semiconductor integrated circuit element to be mounted on the surface of the wiring laminated portion. The wiring board according to any one of 1 to 11.   The capacitor main surface side electrode is formed from directly below the central portion of the semiconductor integrated circuit element to be mounted on the surface of the wiring laminated portion to the outer peripheral direction of the capacitor, and via the main surface side connection conductor. The wiring substrate according to claim 1, wherein the wiring substrate is connected to the core substrate main surface side conductor.

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