JP2007317923A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an occupied area of a selective gate transistor. <P>SOLUTION: A nonvolatile semiconductor memory device comprises a semiconductor substrate 11, a memory cell string provided on the semiconductor substrate 11 and constituted of a plurality of memory cells for storing data in accordance with a quantity of the electric charge of a charge storage layer connected in series, a selective gate transistor SDT connected to the end of the memory cell string in series, and a bit line BL formed over the semiconductor susbtrate 11 and connected to the selective gate transistor SDT. The channel region of the selective gate transistor SDT is formed between the semiconductor substrate 11 and the bit line BL. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a nonvolatile memory cell in which a charge storage layer and a control gate electrode are stacked.

  2. Description of the Related Art Conventionally, an EEPROM (Electrically Erasable Programmable Read Only Memory) that electrically writes and erases data is known as a semiconductor memory. Furthermore, a NAND flash memory capable of high integration is known as one of the EEPROMs.

  A memory cell transistor of a NAND flash memory has a stack gate structure in which a layer or film for charge accumulation and a control gate electrode are stacked on a semiconductor substrate via an insulating film. Then, a plurality of memory cell transistors are connected in series in the column direction so that adjacent ones share a source region or drain region, and select gate transistors are arranged at both ends to constitute a NAND cell unit. Is done.

  A memory cell array is configured by arranging NAND cell units in a matrix. A NAND cell block is configured by NAND cell units arranged in the row direction. The gates of the select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of the memory cell transistors arranged in the same row are connected to the same control gate line.

  In order to pass a current through each NAND cell unit, contacts for connecting bit lines and source lines are provided at both ends of the NAND cell unit. In order to reduce the contact occupation area, an arrangement in which one contact is shared by two adjacent NAND cell units is used. Therefore, the NAND cell unit is folded back with respect to the bit line contact and the source line contact. The bit line contact and the source line contact are provided between select gate transistors of adjacent NAND cell units.

  Although the role of the select gate transistor is diverse, the main ones are (1) cut-off of the non-selected block at the time of reading, and (2) cut-off of the boosted channel voltage in the write-inhibited NAND cell unit in the selected block. . Typically, the bias during these operations is not reduced. For this reason, miniaturization of the select gate transistor is more difficult than miniaturization of the memory cell transistor, and there is a high possibility that the scaling gate wall will be hit before the memory cell transistor.

  This increases the proportion of the select gate transistor in the NAND string length as the NAND flash memory becomes finer.

As a related technique of this type, a technique of forming a bit line contact between select gate transistors in a NAND flash memory is disclosed (see Patent Document 1).
JP 2003-197779 A

  The present invention provides a nonvolatile semiconductor memory device capable of reducing the area occupied by a select gate transistor without degrading the cut-off characteristic of the select gate transistor.

  A nonvolatile semiconductor memory device according to one aspect of the present invention includes a semiconductor substrate and a plurality of memory cells that are provided on the semiconductor substrate and store data according to the amount of charge in a charge storage layer. A memory cell column, a selection gate transistor connected in series to one end of the memory cell column, and a bit line provided above the semiconductor substrate and connected to the selection gate transistor, A channel region of the select gate transistor is provided between the semiconductor substrate and the bit line.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can reduce the area occupied by the selection gate transistor without degrading the cutoff characteristic of the selection gate transistor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a circuit diagram of a NAND flash memory according to the first embodiment of the present invention. One unit, which is a data erasing unit, is connected in series to a memory cell column composed of a plurality of memory cells MC (typically 16 memory cells MC) connected in series and one end (source side) thereof. The selection gate transistor SST and the selection gate transistor SDT connected in series to the other end (drain side).

  A word line WL is connected to the control gate terminal of the memory cell transistor as the memory cell MC. A selection gate line SGSL is connected to the gate terminal of the source side selection gate transistor SST. A source line SL is connected to the source terminal of the select gate transistor SST. A selection gate line SGDL is connected to the gate terminal of the drain side selection gate transistor SDT. A bit line BL is connected to the drain terminal of the select gate transistor SDT.

  The selection gate lines SGSL and SGDL are provided for controlling on / off of the selection gate transistors SST and SDT. The selection gate transistors SST and SDT function as gates for supplying a predetermined potential to the memory cells MC in the unit at the time of data writing and data reading.

  A plurality of units are arranged in the X direction (the extending direction of the word lines WL) to form a block. A plurality of memory cells connected to the same word line WL in one block are handled as one page, and data write and data read operations are performed for each page.

  A plurality of blocks are arranged in the Y direction (bit line extending direction). Here, the first block and the second block adjacent to one (drain side) of the first block share the selection gate transistor SDT on the drain side. That is, the plurality of blocks are arranged so as to be folded in order. The first block and the third block adjacent to the other (source side) of the first block are arranged such that the source side select gate transistor SST faces each other.

  Each memory cell MC has a structure in which a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode are stacked. The memory cell MC is connected in series by sharing the source region and the drain region of the memory cell MC between adjacent ones. The data of the memory cell MC can be changed by injecting electrons into the floating gate electrode included in the memory cell MC or by extracting electrons from the floating gate electrode. Hereinafter, an example of read and write operations will be described.

  At the time of data writing, a positive high potential, for example, 20V is applied to the word line WL of the selected memory cell MC (selected memory cell MC), and a positive intermediate potential, for example, 8V is applied to the word line WL of the non-selected memory cell MC. Apply. Then, VCC (power supply potential) is applied to the drain-side selection gate line SGDL to turn on the selection gate transistor SDT, and 0 V (ground potential) is applied to the source-side selection gate line SGSL to select the selection gate transistor SST. Cut off. Then, 0 V or VCC (for example, 3 V) is applied to the selected bit line BL according to data to be written.

  As a result, the select gate transistor SDT and the non-selected memory cell MC in the unit become conductive, the bit line potential is transmitted to the drain region of the selected memory cell MC, and the threshold voltage of the memory cell MC shifts.

  For example, when “0” is written, 0 V is applied to the bit line BL. Then, since a high electric field is generated between the channel region formed in the active region of the memory cell MC and the control gate electrode, electrons are injected into the floating gate electrode. As a result, the threshold voltage of the memory cell MC shifts in the positive direction.

  On the other hand, “1” writing is a state in which the threshold voltage of the memory cell MC is maintained without being changed (erased state is maintained), and is floating even when a positive high potential of 20 V is applied to the control gate electrode of the memory cell MC. Electrons are not injected into the gate electrode. Therefore, VCC is applied to the bit line BL. Then, after VCC is charged in the channel region of the memory cell MC at the initial stage of writing, 20 V is applied to the selected word line WL and 8 V is applied to the non-selected word line WL.

  Then, although the channel potential rises due to capacitive coupling between the control gate electrode and the channel region, the selection gate transistor SDT is cut off because the selection gate line SGDL on the drain side is VCC together with the bit line BL. As a result, the channel potential rises to about 8 V, so that electrons are not injected into the memory cell MC. That is, the threshold voltage of the memory cell MC does not change.

  At the time of data reading, for example, 0 V is applied to the word line WL of the selected memory cell MC, and a read potential slightly higher than VCC or VCC is applied to the word line WL and the selection gate lines SGDL and SGSL of the unselected memory cell MC. That is, since the select gate transistors SDT and SST and the non-selected memory cell MC are in a conductive state, the potential of the bit line BL is determined depending on whether the threshold voltage of the selected memory cell MC is positive or negative, and data is obtained by detecting this potential. Reading is possible.

  When erasing data, 0 V is applied to all word lines WL in the selected block, and 20 V is applied to the semiconductor substrate. As a result, the electrons of the floating gate electrode are emitted to the semiconductor substrate by the tunnel current in all the memory cells MC in the selected block. As a result, the threshold voltages of these memory cells shift in the negative direction.

  On the other hand, all word lines WL, selection gate lines SGDL, SGSL, and bit lines BL in the non-selected block are set in a floating state. As a result, in the non-selected block, the word line WL rises to near 20 V due to capacitive coupling with the active region, so that the erase operation is not performed.

  Next, the structure of the NAND flash memory of this embodiment will be described. FIG. 2 is a plan view of the NAND flash memory mainly showing the selection gate transistor SDT. FIG. 3 is a cross-sectional view of the NAND flash memory taken along the line III-III shown in FIG. 4 is a cross-sectional view of the NAND flash memory taken along line IV-IV shown in FIG. In the plan view of FIG. 1, the bit lines BL and the interlayer insulating layer 20 are not shown for easy understanding of the structure.

  The P-type conductive substrate 11 is, for example, a P-type semiconductor substrate, a semiconductor substrate having a P-type well, an SOI (Silicon On Insulator) type substrate having a P-type semiconductor layer, or the like. For example, silicon is used as the semiconductor substrate. For example, the P-type semiconductor substrate 11 includes an element isolation insulating layer 12 in a surface region, and an element region (active region: AA) in which the surface region of the semiconductor substrate 11 where the element isolation insulating layer 12 is not formed forms an element. Become. The element isolation insulating layer 12 is configured by, for example, STI (Shallow Trench Isolation). For example, a silicon oxide film is used as the STI 12.

  On the semiconductor substrate 11, a gate stacked body in which a tunnel insulating film 13, a floating gate electrode 14, a gate insulating film 15, and a control gate electrode 16 constituting the memory cell MC are sequentially stacked is provided. The control gate electrode 16 corresponds to the word line WL shown in FIG.

In the semiconductor substrate 11 on both sides of the gate stack, an N ⁺ type diffusion layer 17-1 that functions as a source region and a drain region of the memory cell MC is provided. The N ⁺ -type diffusion layer 17-1 is a semiconductor layer in which a high concentration N ⁺ -type impurity is diffused. Adjacent memory cells MC share one N ⁺ -type diffusion layer 17-1. In this way, the plurality of memory cells MC in the unit are connected in series.

  Side wall insulating films 18 are provided on both side surfaces of the gate stack. For example, a silicon oxide film is used as the sidewall insulating film 18. A barrier film 19 is provided on the memory cell MC. In this way, the memory cell MC is configured.

  Next, the structure of the drain side select gate transistor SDT will be described. In the present embodiment, a vertical transistor is used as the selection gate transistor SDT. Note that a vertical transistor is a transistor in which a channel is formed in a vertical direction.

An N ⁺ type diffusion layer 17-2 is provided in the semiconductor substrate 11 between adjacent blocks on the drain side (that is, a region where the select gate transistor SDT is formed). The N ⁺ type diffusion layer 17-2 functions as a source / drain region of the memory cell MC disposed at the end on the drain side.

On the N ⁺ diffusion layer 17-2, ^{N +} -type diffusion layer (source region) 21 is provided. A P ⁻ type diffusion layer (channel region) 22 is provided on the N ⁺ type diffusion layer 21. The P ⁻ type diffusion layer 22 is a semiconductor layer in which low concentration P ⁻ type impurities are diffused. An N ⁺ type diffusion layer (drain region) 23 is provided on the P ⁻ type diffusion layer 22. Specifically, the N ⁺ -type diffusion layer 23 protrudes laterally from the N ⁺ -type diffusion layer 23-1 provided on the P ⁻ -type diffusion layer 22 and the upper part of the N ⁺ -type diffusion layer 23-1. N ⁺ -type diffusion layer 23-2. The N ⁺ type diffusion layer 23-2 is provided for a margin when forming a contact electrically connected to the N ⁺ type diffusion layer 23.

A gate insulating film 24 is provided on the side surface of the laminated film composed of the N ⁺ -type diffusion layer 21, the P ⁻ -type diffusion layer 22, and the N ⁺ -type diffusion layer 23. As the gate insulating film 24, for example, a silicon oxide film is used. A gate electrode 25 is provided on the side surface of the gate insulating film 24 so as to extend in the X direction. The gate electrode 25 corresponds to the selection gate line SGDL shown in FIG. For example, polysilicon is used as the gate electrode 25.

In the present embodiment, the gate electrode 25 is provided on the side surface of the laminated film including the N ⁺ -type diffusion layer 21, the P ⁻ -type diffusion layer 22, and the N ⁺ -type diffusion layer 23 via the gate insulating film 24. Yes. However, the present invention is not limited to this, and the gate electrode 25 only needs to be provided on at least the side surface of the P ⁻ -type diffusion layer 22 as the channel region via the gate insulating film 24. In this way, the selection gate transistor SDT is configured.

As shown in FIG. 2, the plurality of N ⁺ -type diffusion layers 23-2 are alternately arranged on both sides of the gate electrode 25 in the plurality of selection transistors in the same column. That is, two N ⁺ type diffusion layers 23-2 corresponding to two units adjacent in the X direction are arranged on one side and the other side in the Y direction with respect to the gate electrode 25. In other words, the two N ⁺ -type diffusion layers 23-2 are shifted in the Y direction so as not to face each other in the X direction.

On the side ^where the ^{N +} -type diffusion layer 23-2 on the N ⁺ diffusion layer 23 is arranged, the contact layer 26 is provided. A bit line BL is provided on the contact layer 26 so as to extend in the Y direction. The interlayer insulating layer 20 is filled between the semiconductor substrate 11 and the bit line BL.

  Next, the structure of the source side select gate transistor SST will be described. FIG. 5 is a plan view of a NAND flash memory centered on the select gate transistor SST. 6 is a cross-sectional view of the NAND flash memory taken along the line VI-VI shown in FIG.

  A gate electrode 31 is provided on the semiconductor substrate 11 via a gate insulating film 13 so as to extend in the X direction. The gate electrode 31 corresponds to the selection gate line SGSL shown in FIG. For example, polysilicon is used as the gate electrode 31. Sidewall insulating films 18 are provided on both side surfaces of the gate electrode 31.

An N ⁺ type diffusion layer 17-3 is provided in the semiconductor substrate 11 between the gate electrodes 31 adjacent on the source side. The N ⁺ type diffusion layer 17-3 functions as a common source region for two adjacent select gate transistors SST. The select gate transistor SST is connected in series with the memory cell MC by sharing the N ⁺ type diffusion layer 17-1 with the adjacent memory cell MC.

A contact layer 32 is provided on the N ⁺ -type diffusion layer 17-3. As the contact layer 32, for example, tungsten (W) is used. A source line SL is provided on the contact layer 26 so as to extend in the X direction. A space between the semiconductor substrate 11 and the source line SL is filled with an interlayer insulating layer 20. In this way, the selection gate transistor SST is configured.

  Next, an example of a method for manufacturing the NAND flash memory according to this embodiment will be described. 7A to 13A are plan views showing one process of the manufacturing method. 7B to 13B are cross-sectional views along the line III-III shown in the plan views. 7C to 13C are cross-sectional views taken along line IV-IV shown in the plan views.

  An active area AA in which semiconductor elements such as transistors are formed is formed in the surface area of the P-type semiconductor substrate 11. In other words, the active region AA is formed in the surface region of the semiconductor substrate 11 by forming the STI 12 in the surface region of the P-type semiconductor substrate 11. The STI 12 is formed by forming a groove in the semiconductor substrate 11 using a lithography method and an RIE (Reactive Ion Etching) method and embedding an insulator such as a silicon oxide film in the groove.

  Next, as shown in FIGS. 7A to 7C, a tunnel insulating film 13, a floating gate electrode 14, a gate insulating film 15, and a control gate electrode 16 constituting the memory cell MC are sequentially deposited on the semiconductor substrate 11. Then, the control gate electrode 16, the gate insulating film 15, and the floating gate electrode 14 are patterned into a desired shape by using a lithography method and an RIE method.

  For example, a silicon oxide film is used as the tunnel insulating film 13. For example, polysilicon is used as the floating gate electrode 14. As the gate insulating film 15, for example, an ONO film (a laminated film including an oxide film, a nitride film, and an oxide film) is used. For example, polysilicon is used as the control gate electrode 16.

Next, as shown in FIGS. 8A to 8C, by introducing N ⁺ -type impurities (phosphorus (P), arsenic (As), etc.) into the P-type semiconductor substrate 11, N ⁺ -type diffusion layers 17− 1, 17-2. Next, sidewall insulating films 18 are formed on the side surfaces of the control gate electrode 16 and the floating gate electrode 14. At this time, the memory cells MC in the same block are filled with the sidewall insulating film 18. Note that the tunnel insulating film 13 between adjacent blocks is etched by the step of forming the sidewall insulating film 18.

  Next, a barrier film 19 is deposited on the entire surface of the device for the purpose of a stopper during an etching process for forming an opening between adjacent blocks. For example, a silicon nitride film is used as the barrier film 19.

  Next, as shown in FIGS. 9A to 9C, an insulating layer 20-1 is deposited on the entire surface of the device. As the insulating layer 20-1, for example, a silicon oxide film is used. Alternatively, BPSG (Boron Phosphorus Silicate Glass), BSG (Boron Silicate Glass), PSG (Phosphorus Silicate Glass), or the like in which B and P are included in the silicon oxide film may be used.

Next, as shown in FIGS. 10A to 10C, the insulating layer 20-1 and the barrier film 19 are etched using the lithography method and the RIE method so as to expose the upper surface of the N ⁺ type diffusion layer 17-2. . Thereby, the opening 41-1 exposing the upper surface of the N ⁺ type diffusion layer 17-2 is formed.

  Further, an opening 41-2 is formed in the surface region of the insulating layer 20-1 by using a lithography method and an RIE method. The opening 41-2 is formed so as to protrude from the upper part of the opening 41-1 in the Y direction. As shown in FIG. 10A, the plurality of openings 41-2 are alternately formed on one side and the other side in the Y direction with respect to the opening 41-1.

Next, as shown in FIGS. 11A to 11C, the N ⁺ type diffusion layer 21 is formed on the N ⁺ type diffusion layer 17-2 by, for example, a selective growth method (specifically, so as to embed the lower portion of the opening 41-1. For this, selective CVD (Chemical Vapor Deposition) method is used. Next, the P ⁻ -type diffusion layer 22 is formed on the N ⁺ -type diffusion layer 21 by using, for example, a selective growth method so as to embed an intermediate portion of the opening 41-1.

Next, the N ⁺ -type diffusion layer 23 is formed on the P ⁻ -type diffusion layer 22 using, for example, a selective growth method so as to fill the upper portion of the opening 41-1 and the opening 41-2. Thus, P ^- type diffusion layer ^{N +} -type diffusion layer 23-1 formed on the 22, the ^{N +} -type diffusion layer 23-2 which projects in the Y direction from the top of the ^{N +} -type diffusion layer 23-1 Is formed. Thereafter, the upper surfaces of the N ⁺ -type diffusion layer 23 and the insulating layer 20-1 are planarized using a CMP (Chemical Mechanical Polishing) method. Then, an insulating layer 20-2 is deposited on the N ⁺ -type diffusion layer 23 and the insulating layer 20-1.

Next, as shown in FIGS. 12A to 12C, lithography is performed so that the side surfaces of the N ⁺ -type diffusion layers 23-1 and 23 and 21 and the P ⁻ -type diffusion layer 22 and the upper surface of the N ⁺ -type diffusion layer 17-2 are exposed. The insulating layer 20-2, the N ⁺ -type diffusion layers 23-1, 21 and the P ⁻ -type diffusion layer 22 are selectively etched using the method and the RIE method. As a result, an opening 42 is formed that exposes the side surfaces of the N ⁺ -type diffusion layers 23-1 and 21 and the P ⁻ -type diffusion layer 22 and extends in the X direction. Note that the opening 42 does not necessarily reach the N ⁺ -type diffusion layer 17-2 as long as it reaches the bottom surface of the P ⁻ -type diffusion layer 22.

Next, as shown in FIGS. 13A to 13C, on the side surface of the laminated film (consisting of the N ⁺ -type diffusion layers 23-1, 21 and the P ⁻ -type diffusion layer 22) and on the N ⁺ -type diffusion layer 17-2. Then, a gate insulating film 24 is deposited. Next, the gate electrode 25 is formed on the side surface of the gate insulating film 24 so as to fill the opening 42. Thereafter, the upper surfaces of the gate electrode 25 and the insulating layer 20-2 are planarized using a CMP method.

Next, as shown in FIGS. 2 to 4, an insulating layer is deposited on the gate electrode 25 and the insulating layer 20-2. Then, the upper surface of the insulating layer is planarized using a CMP method. Thereby, the interlayer insulating layer 20 is formed. Next, the contact layer 26 is formed in the interlayer insulating layer 20 so as to reach the N ⁺ type diffusion layers 23-1 and 23-2. Thereby, the contact layer 26 electrically connected to the N ⁺ type diffusion layers 23-1 and 23-2 is formed. As the contact layer 26, for example, tungsten (W) is used. The plurality of contact layers 26 are alternately formed on both sides of the gate electrode 25.

Next, a bit line BL extending in the Y direction is formed on the contact layer 26 and the interlayer insulating layer 20. Thereby, the bit line BL electrically connected to the N ⁺ type diffusion layer 23 is formed.

  In the NAND flash memory configured as described above, since the vertical transistor is used as the selection gate transistor SDT, the area occupied by the selection gate transistor SDT can be reduced. That is, the select gate transistor SDT can be miniaturized.

  In addition, the area occupied by the select gate transistor SDT can be reduced without degrading the cut-off characteristics of the select gate transistor SDT. As a result, it is not necessary to reduce the bias during operation of the NAND flash memory, and the NAND flash memory can be operated in an optimum state.

  In addition, one select gate transistor SDT is shared between adjacent blocks. Even with this configuration, the data write and data read operations of the NAND flash memory can be performed accurately. As a result, the NAND flash memory can be further miniaturized.

  In addition, contact layers 26 that electrically connect the select gate transistors SDT and the bit lines BL are alternately arranged on both sides of the gate electrode 25. As a result, the contact layers 26 adjacent in the X direction are arranged with a sufficient distance. As a result, the size of each contact layer 26 can be increased. Furthermore, the process of forming the contact layer 26 can be facilitated.

  The channel region, source region, and drain region of the select gate transistor SDT are provided on the side surface of the interlayer insulating layer 20. That is, the channel region, source region, and drain region of the select gate transistor SDT are equivalent to those formed in an SOI (Silicon On Insulator) layer provided on the insulating layer. Therefore, the parasitic capacitance of the select gate transistor SDT can be reduced. As a result, the operation speed of the select gate transistor SDT can be increased.

  Note that a vertical transistor may be applied to the selection gate transistor SST on the source side. That is, the first block and the second block adjacent to one (source side) of the first block share one select gate transistor SST. Two selection gate transistors SDT are arranged between the first block and a third block adjacent to the other (drain side) of the first block, and the two selection gate transistors SDT are arranged. Are connected in series. Even when the NAND flash memory is configured in this manner, the present invention can be similarly implemented.

(Second Embodiment)
The second embodiment is another configuration example of the selection gate transistor SDT, and a NAND flash memory is miniaturized without using a vertical transistor.

  FIG. 14 is a plan view of a NAND flash memory according to the second embodiment of the present invention. FIG. 14 mainly shows the selection gate transistor SDT. FIG. 15 is a cross-sectional view of the NAND flash memory taken along the line III-III shown in FIG. FIG. 16 is a cross-sectional view of the NAND flash memory taken along line IV-IV shown in FIG. In the plan view of FIG. 14, the bit line BL and the interlayer insulating layers 20 and 58 are not shown for easy understanding of the structure.

An N ⁺ type diffusion layer 17-2 is provided in the semiconductor substrate 11 between adjacent blocks on the drain side (that is, a region where the select gate transistor SDT is formed). The N ⁺ type diffusion layer 17-2 functions as a source / drain region of the memory cell MC disposed at the end on the drain side. The structure of the memory cell MC is the same as that in the first embodiment.

A contact layer 51 electrically connected to the N ⁺ type diffusion layer 17-2 is provided on the N ⁺ type diffusion layer 17-2 in the interlayer insulating layer 20. The contact layer 51 is constituted by, for example, an N ⁺ type diffusion layer into which a high concentration N ⁺ impurity is introduced.

A P ⁻ type semiconductor layer 52 into which a low concentration of P ⁻ type impurity is introduced is provided on the interlayer insulating layer 20 so as to be in contact with the side surface of the contact layer 51. The P ⁻ type semiconductor layer 52 functions as an active layer of the select gate transistor SDT.

Further, as shown in FIG. 14, in the plurality of selection transistors in the same column, the plurality of P ⁻ type semiconductor layers 52 are alternately arranged on both sides of the contact layer 51. That is, the two P ⁻ type semiconductor layers 52 corresponding to the two units adjacent in the X direction are arranged on one side and the other side in the Y direction with respect to the contact layer 51. In other words, the P ⁻ type semiconductor layer 52 is shifted in the Y direction so as not to face in the X direction.

A gate insulating film 55 is provided on the P ⁻ type semiconductor layer 52. For example, a silicon oxide film is used as the gate insulating film 55. A gate electrode 56 is provided on the gate insulating film 55 so as to extend in the X direction. The gate electrode 56 corresponds to the selection gate line SGDL shown in FIG. For example, polysilicon is used as the gate electrode 56.

An N ⁺ type diffusion layer 53 as a source region and an N ⁺ type diffusion layer 54 as a drain region are provided on both sides of the gate electrode 56 in the P ⁻ type semiconductor layer 52. In this way, the selection gate transistor SDT is configured.

An interlayer insulating layer 58 is provided on the select gate transistor SDT. A bit line BL extending in the Y direction is provided on the interlayer insulating layer 58. In the interlayer insulating layer 58, a contact layer 57 for electrically connecting the N ⁺ type diffusion layer 54 and the bit line BL is provided.

  Next, an example of a method for manufacturing the NAND flash memory according to this embodiment will be described. 17A to 21A are plan views showing one process of the manufacturing method. FIGS. 17B to 21B are cross-sectional views taken along line III-III shown in the plan views. FIGS. 17C to 21C are cross-sectional views taken along the line IV-IV shown in the plan views.

The manufacturing process until the insulating layer 20-1 described in the first embodiment is formed (that is, the manufacturing process up to FIGS. 9A to 9C) is the same as that in the first embodiment. Next, as illustrated in FIGS. 17A to 17C, the interlayer insulating layer 20 and the barrier film 19 are etched using the lithography method and the RIE method so that the upper surface of the N ⁺ -type diffusion layer 17-2 is exposed. As a result, an opening 61 exposing the upper surface of the N ⁺ -type diffusion layer 17-2 is formed.

Next, as shown in FIG. 18A to FIG. 18C, on ^{the N +} diffusion layer 17-2, so as to fill the opening 61, the ^{N +} -type diffusion layer serving as a contact layer 51 using, for example, a selective growth method Form. Thereafter, the upper surfaces of the contact layer 51 and the interlayer insulating layer 20 are planarized using a CMP method.

  Next, as shown in FIGS. 19A to 19C, an opening 62 that exposes the side surface of the contact layer 51 in the interlayer insulating layer 20 is formed by lithography and RIE. As shown in FIG. 19A, the plurality of openings 62 are alternately formed on both sides of the contact layer 51.

Next, as shown in FIGS. 20A to 20C, a polysilicon layer into which no impurity is introduced (undoped polysilicon layer) is deposited so as to fill the opening 62. Next, the upper surface of the polysilicon layer is planarized using a CMP method. Next, a low-concentration P ^- type impurity is introduced into the polysilicon layer. As a result, a P ⁻ type semiconductor layer 52 as an active region of the select gate transistor SDT is formed in the opening 62.

Next, as shown in FIGS. 21A to 21C, a gate insulating film 55 is formed on the P ⁻ type semiconductor layer 52. Next, a gate electrode 56 extending in the X direction is formed on the gate insulating film 55 by lithography and RIE.

Next, high-concentration N ⁺ -type impurities are introduced into the P ⁻ -type semiconductor layer 52 using the gate electrode 56 as a mask. As a result, an N ⁺ type diffusion layer 53 as a source region and an N ⁺ type diffusion layer 54 as a drain region are formed on both sides of the gate electrode 56 in the P ⁻ type semiconductor layer 52.

Next, as shown in FIGS. 14 to 16, an interlayer insulating layer 58 is deposited on the gate electrode 56 and the gate insulating film 55. Then, the upper surface of the interlayer insulating layer 58 is planarized using a CMP method. Next, a contact layer 57 is formed in the interlayer insulating layer 58 so as to reach the N ⁺ -type diffusion layer 54. As a result, a contact layer 57 electrically connected to the N ⁺ -type diffusion layer 54 is formed. As the contact layer 57, for example, tungsten (W) is used.

Next, a bit line BL extending in the Y direction is formed on the contact layer 57 and the interlayer insulating layer 58. Thereby, the bit line BL electrically connected to the N ⁺ type diffusion layer 54 is formed. In this way, a NAND flash memory is formed.

  In the NAND flash memory configured as described above, the select gate transistor SDT is formed in an interlayer insulating layer between the semiconductor substrate 11 and the bit line BL. That is, the select gate transistor SDT is not formed on the semiconductor substrate 11. Further, only the contact layer 51 is disposed between the two memory cells connected to the select gate transistor SDT. Thereby, the area between adjacent blocks can be reduced, and the NAND flash memory can be miniaturized.

  Further, the size of the select gate transistor SDT is not reduced. As a result, it is not necessary to reduce the bias during operation of the NAND flash memory, and the NAND flash memory can be operated in an optimum state.

  The select gate transistors SDT are alternately arranged on both sides of the contact layer 51. Further, contact layers 57 that electrically connect the select gate transistors SDT and the bit lines BL are alternately arranged on both sides of the contact layer 51. Thereby, the contact layer 57 adjacent in the X direction is arranged with a sufficient distance. As a result, the size of each contact layer 57 can be increased.

  The select gate transistor SDT is provided on the interlayer insulating layer 20. That is, the select gate transistor SDT is formed in the SOI layer provided on the interlayer insulating layer 20. Thereby, the operation speed of the select gate transistor SDT can be increased.

  Of course, the second embodiment can be applied to the select gate transistor SST.

  In the first and second embodiments, the NAND flash memory using NAND cells has been described as an example. However, the present invention is not limited to this and can be applied to all EEPROMs using nonvolatile memory cells.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the components without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a circuit diagram of a NAND flash memory according to a first embodiment of the present invention. FIG. 3 is a plan view of the NAND flash memory mainly showing the selection gate transistor SDT according to the first embodiment. FIG. 3 is a cross-sectional view of the NAND flash memory taken along line III-III shown in FIG. 2. FIG. 4 is a cross-sectional view of the NAND flash memory taken along line IV-IV shown in FIG. 2. 1 is a plan view of a NAND flash memory mainly showing a selection gate transistor SST according to a first embodiment. FIG. 6 is a cross-sectional view of the NAND flash memory along the line VI-VI shown in FIG. 5. FIG. 3 is a plan view showing a manufacturing process of the NAND flash memory according to the first embodiment. FIG. 7B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 7A. FIG. 7B is a cross-sectional view showing a manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 7A. FIG. 7B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 7A. FIG. 8B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 8A. FIG. 8B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 8A. FIG. 8B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 8A. FIG. 9B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 9A. FIG. 9B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 9A. FIG. 9B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 9A. FIG. 10B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 10A. FIG. 10B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 10A. FIG. 10B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 10A. FIG. 11B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 11A. FIG. 11B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 11A. FIG. 11B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 11A. FIG. 12B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 12A. FIG. 12B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 12A. FIG. 12B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 12A. FIG. 13B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 13A. FIG. 14B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 13A. FIG. 6 is a plan view of a NAND flash memory mainly showing a selection gate transistor SDT according to a second embodiment of the present invention. FIG. 15 is a cross-sectional view of the NAND flash memory taken along line III-III shown in FIG. 14. FIG. 15 is a cross-sectional view of the NAND flash memory taken along line IV-IV shown in FIG. 14. FIG. 6 is a plan view showing a manufacturing process of a NAND flash memory according to a second embodiment. FIG. 17B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 17A. FIG. 17B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 17A. FIG. 17B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 17A. FIG. 18B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 18A. FIG. 18B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 18A. FIG. 18B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 18A. FIG. 19B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 19A. FIG. 19B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 19A. FIG. 19B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 19A. FIG. 20B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 20A. FIG. 20B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 20A. FIG. 20B is a plan view showing a manufacturing process of the NAND flash memory following FIG. 20A. FIG. 21B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line III-III shown in FIG. 21A. FIG. 21B is a cross-sectional view showing the manufacturing process of the NAND flash memory along the line IV-IV shown in FIG. 21A.

Explanation of symbols

MC ... memory cell, SST, SDT ... selection gate transistor, WL ... word line, SGSL, SGDL ... selection gate line, SL ... source line, BL ... bit line, AA ... active region, 11 ... P-type semiconductor substrate, 12 ... Element isolation insulating layer (STI), 13 ... tunnel insulating film (gate insulating film), 14 ... floating gate electrode, 15 ... gate insulating film, 16 ... control gate electrode, 17-1, 17-2, 17-3 ... N ⁺ Type diffusion layer, 18 ... sidewall insulating film, 19 ... barrier film, 20, 58 ... interlayer insulating layer, 21 ... N ⁺ type diffusion layer, 22 ... P ^- type diffusion layer, 23, 23-1, 23-2 ... N ⁺ type diffusion layer, 24, 55 ... gate insulating film, 25, 31, 56 ... gate electrode, 26, 32, 51, 57 ... contact layer, 41, 42, 61, 62 ... opening, 52 ... P ^- type semiconductor layer, 53,54 ... N Type diffusion layer.

Claims (5)

A semiconductor substrate;
A memory cell array configured by connecting a plurality of memory cells provided in the semiconductor substrate and storing data according to the amount of charge in the charge storage layer; and
A select gate transistor connected in series to one end of the memory cell column;
A bit line provided above the semiconductor substrate and connected to the select gate transistor;
A non-volatile semiconductor memory device, wherein a channel region of the select gate transistor is provided between the semiconductor substrate and the bit line. The memory cell includes a source region and a drain region provided in the semiconductor substrate,
The selection gate transistor is:
A first diffusion layer provided on a source / drain region at one end of the memory cell row and having a first conductivity type;
A second diffusion layer provided on the first diffusion layer and having a channel and having a second conductivity type;
A third diffusion layer provided on the second diffusion layer and electrically connected to the bit line and comprising the first conductivity type;
The nonvolatile semiconductor memory device according to claim 1, further comprising: a gate electrode provided on the second diffusion layer via a gate insulating film. A contact layer that electrically connects the bit line and the third diffusion layer;
3. The nonvolatile semiconductor memory device according to claim 2, wherein two contact layers corresponding to two adjacent memory cell columns are arranged so as not to face each other in the extending direction of the gate electrode. An interlayer insulating layer provided on the plurality of memory cells;
The memory cell includes a source region and a drain region provided in the semiconductor substrate,
The selection gate transistor is:
An active layer provided in the interlayer insulating layer;
A gate electrode provided on the active layer via a gate insulating film;
A source region provided in the active layer and electrically connected to a source / drain region at one end of the memory cell column via a first contact layer;
The nonvolatile semiconductor memory device according to claim 1, further comprising: a drain region provided in the active layer and electrically connected to the bit line. A second contact layer for electrically connecting the bit line and the drain region of the select gate transistor;
5. The nonvolatile semiconductor according to claim 4, wherein two second contact layers corresponding to two adjacent memory cell columns are arranged so as not to face each other in an extending direction of the gate electrode. Storage device.

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