JP2007311488A - Magnetic storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic storage having a large operation margin. <P>SOLUTION: The magnetic storage contains a memory cell array arranging magnetoresistance-effect elements in a line. A first writing line 4a is extended along the first direction, and supplied only with a current directed in the first direction. A second writing line 4b is extended along the first direction, and supplied only with the current directed in the second direction opposite to the first direction. A third writing line 3a is extended along the third direction orthogonal to the first direction. A first electrode 54a is fitted between the first and third writing lines. A first plug 55a is connected to the first electrode, and fitted on the lower side along the third direction by the first writing line. A second electrode 54b is mounted between the second and third writing lines. A second plug 55b is connected to the second electrode, and mounted on the upper side along the third direction by the second writing line. The magnetoresistance-effect elements are arranged at a place where the first writing line crosses with the third writing line, and the place where the second writing line crosses with the third writing line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a magnetic memory device, for example, to the shape and arrangement of each part in a memory cell.

  A memory cell of a magnetic random access memory (MRAM) is mainly a 1T1R type including one magnetoresistive element and one select transistor. A write current circuit is connected to both ends of two types of write lines for generating a magnetic field applied to each magnetoresistive effect element, and a current flows from the write current circuit at one end to the write current circuit at the other end. By providing the write current circuit between adjacent memory cell arrays, the circuit configuration can be simplified by making the write current circuit common among a plurality of memory cell arrays or sharing a control signal.

  In the case of the 1T1R type memory cell, the magnetoresistive effect element is electrically connected to the selection transistor through the lower electrode and the plug. Since it is necessary to dispose the magnetoresistive element between the two write lines, the plug is disposed so as to avoid the intersection of the write lines. Since the lower electrode needs to be connected to the plug, it has a planar shape different from the planar shape of the magnetoresistive element. Further, the lower electrode may take a planar shape such as an L shape in order to highly integrate memory cells.

  It is desirable that all memory cells behave the same in order to ensure an operating margin. In order to achieve this requirement, the characteristics of each memory cell can be made uniform by aligning the physical shape of each part such as an electrode, a magnetoresistive effect element, and wiring (Non-Patent Document 1).

  Non-Patent Document 1 does not mention the write magnetic field. However, in order to make the characteristics of each memory cell uniform, it is preferable that the characteristics such as the direction and the magnitude of the write magnetic field are made uniform among the memory cells. For this purpose, it is required to make the relative positional relationship of the electrode, the magnetoresistive effect element (particularly, the free layer), the wiring, etc. uniform.

  However, when a write current circuit having only a function of supplying a write current is provided between adjacent memory cell arrays, the direction of the magnetic field applied to the memory cell is such that the memory cell in one memory cell array and the other memory It differs depending on the memory cell in the cell array. Therefore, the manner in which the magnetic field is applied to the memory cells differs between the memory cells.

  Further, it is known that the shape of the lower electrode affects the write magnetic field. One reason is that the writing magnetic field and the lower electrode are electromagnetically coupled to affect the writing magnetic field, and this coupling depends on the shape of the lower electrode. In particular, when the planar shape of the lower electrode is asymmetric, the manner in which the magnetic field is applied to the memory cells differs greatly between the memory cells.

  Furthermore, the fixed layer may take the same shape as the lower electrode for convenience of the manufacturing process. The magnetization of the fixed layer forms a leakage magnetic field in a direction corresponding to the direction, and changes the writing magnetic field. This leakage magnetic field is affected by the shape of the fixed layer, that is, the shape of the lower electrode. For this reason as well, the shape of the lower electrode varies between the memory cells in how the magnetic field is applied to the memory cells.

  As described above, the characteristics of the magnetic field applied to the memory cell differ depending on the combination of the difference in the physical shape of each part such as the electrode, magnetoresistive effect element, and wiring, and the difference in relative positional relationship. As a result, the operation margin is narrowed.

FIG. 8 of Patent Document 1 discloses that two MRAM macros RMCA and RMCB are mirror-symmetric (line target) with respect to a virtual axis parallel to the hard axis of magnetization of the magnetoresistive element VR. FIG. 27 discloses that the two MRAM macros RMCJ and RMCK are mirror-symmetrical (line target) with respect to a virtual axis parallel to the easy axis of the magnetoresistive element VR. By doing this, it is stated that the effect of maintaining the consistency between the write data and the read data can be obtained. In Patent Document 1, as long as data of the same logic (“0” or “1”) is written, the direction of the write magnetic field is the same regardless of the structure of the MRAM macro.
JP 2005-236177 A U.S. Pat.No. 6,545,906 Dietmar Gogl et al., "A 16-Mb MRAM Featuring Bootstrapped Write Drivers", IEEE journal of Solid-state Circuits, April 2005, vol. 40 pp.902

  The present invention seeks to provide a magnetic storage device with a large operating margin.

  A magnetic memory device according to an aspect of the present invention includes a memory cell array in which magnetoresistive effect elements are arranged in a matrix, a first write line that extends along a first direction and is supplied with only a current in the first direction, A second write line that extends along the first direction and is supplied only with a current in a second direction opposite to the first direction; and a second write line that extends along a third direction orthogonal to the first direction. 3 write lines, a first electrode provided between the first write line and the third write line, and connected to the first electrode and below the first write line along the third direction. A first plug provided on the side, a second electrode provided between the second write line and the third write line, and the third electrode connected to the second electrode and from the second write line. A second plug provided on the upper side in the direction. , The magnetoresistive element is characterized in that it is disposed in the said first write line third write line and crosses position, and said second write line and the third write line intersect position.

  According to an aspect of the present invention, a magnetic memory device includes a first memory cell array and a second memory cell array in which magnetoresistive elements are arranged in a matrix, the first memory cell array extending along a first direction, and the first direction. A first write line to which only a current directed to the first line is supplied, and only a current extending in the first direction in the second memory cell array and directed in a second direction opposite to the first direction is supplied. A second write line; a third write line extending in a third direction orthogonal to the first direction in the first memory cell array; and a fourth write line extending in the third direction in the second memory cell array. A write line, a first electrode provided between the first write line and the third write line, and a first electrode connected to the first electrode and below the first write line along the third direction Established in A first plug, a second electrode provided between the second write line and the fourth write line, and a second electrode connected to the second electrode and extending in the third direction from the second write line. A second plug provided on the upper side, wherein the magnetoresistive effect element has a position where the first write line and the third write line intersect in the first memory cell array, and in the second memory cell array. The second write line and the fourth write line are arranged at positions where they intersect.

  A magnetic memory device according to an aspect of the present invention includes a memory cell array in which magnetoresistive effect elements are arranged in a matrix, a first write line that extends along a first direction and is supplied with only a current in the first direction, A second write line that extends along the first direction and is supplied only with a current in a second direction opposite to the first direction; and a second write line that extends along a third direction orthogonal to the first direction. 3 write lines, a first electrode provided between the first write line and the third write line, and connected to the first electrode and below the first write line along the third direction. A first plug provided on the side, a second electrode provided between the second write line and the third write line, and the third electrode connected to the second electrode and from the second write line. A second plug provided on the upper side in the direction. The magnetoresistive element is disposed at a position where the first write line and the third write line intersect, and a position where the second write line and the third write line intersect, and the first plug and the The second plug is arranged along the first direction between the first write line and the second write line.

  According to the present invention, a magnetic storage device having a large operation margin can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  The expressions “upper, lower, left, and right” used in this specification are used in accordance with the orientation of the corresponding drawing for convenience of explanation. Similarly, the expressions “up, down, left, and right” used in the claims are also used for easy understanding of the contents of the invention. For this reason, this expression does not mean an absolute position, and structures that match the relationships shown in the present specification, drawings, and claims by appropriately rotating are also included in the scope of the present invention.

(First embodiment)
The first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram of the magnetic memory device according to the first embodiment. As shown in FIG. 1, the magnetic storage device includes two memory cell arrays 1a and 1b. Each of the memory cell arrays 1a and 1b is composed of a plurality of memory cells 2a and 2b arranged in a matrix as will be described later (only one is shown in FIG. 1). Memory cells 2a and 2b (generally referred to as memory cell 2) include magnetoresistive elements as will be described later.

  The memory cell arrays 1a and 1b include a plurality of write lines 3 and 4 (FIG. 1 shows only one line per memory cell array). The write lines 3 and 4 extend along a direction intersecting each other. For example, the write line 3 extends along the vertical direction of the paper surface, and the write line 4 extends along the horizontal direction of the paper surface. The write line 3 and the write line 4 intersect at the position of the memory cell 2 and sandwich the memory cell 2 therebetween.

  Around the memory cell arrays 1a and 1b, a control circuit 5 is provided along each side of the memory cell arrays 1a and 1b.

  A current source / sink 6 is provided in parallel with the two control circuits 5 aligned with the upper and lower sides of each of the memory cell arrays 1a and 1b. The current source / sink 6 is connected to the write line 3 via the control circuit 5. Each current source / sink 6 is electrically connected to at least one write line 3 by a control circuit 5 including a set of switch circuits such as transistors.

  In response to a control signal (not shown), one of the pair of current sources / sinks 6 connected to both ends of the write line 3 supplies a write current to the write line 3, and the other draws a current from the write line 3. Therefore, both the upward current and downward current in the figure can flow through the write line 3 (write line 3a) passing through the memory cell array 1 and the write line 3 (write line 3b) passing through the memory cell array 1b. Information written to the memory cell to be written is controlled by the direction of the current flowing through the write line 3.

  A current source 7 is provided between the control circuit 5 aligned with the left side of the memory cell array 1a and the control circuit 5 aligned with the right side of the memory cell array 1b. A current sink 8 is provided in parallel with the control circuit 5 aligned with the right side of the memory cell array 1a and in parallel with the control circuit 5 aligned with the left side of the memory cell array 1a.

  One set of current source 7 and current sink 8 are electrically connected to both ends of at least one write line 4 by a control circuit 5. Then, a write current is supplied to the write line 4 to which the current source 7 is connected, and the current sink 8 extracts the write current. Therefore, only a current in one direction flows through the write line 4. Specifically, only the current flowing in the right direction of the paper surface flows through the write line 4 (write line 4a) passing through the memory cell array 1a, and the left direction of the paper surface through the write line 4 (write line 4b) passing through the memory cell array 1b. Only the current going to

  Since the current source 7 is shared by the two memory cell arrays 1a and 1b, a highly integrated layout such that only one constant current source and control circuit for the current source 7 is required for the two memory cell arrays 1a and 1b. Can be realized.

  FIG. 2 is a circuit diagram showing an example of the detailed configuration of FIG. FIG. 2 corresponds to the configuration of the memory cell array 1a. The circuit configuration of the memory cell array 1b is the same as that of the memory cell array 1a except that the positions of the current source 7 and the current sink 8 in FIG. 2 are inverted. Therefore, the description of the memory cell array 1b is omitted.

  As shown in FIG. 2, the memory cell 2 includes a magnetoresistive effect element 11 and a switch element, for example, a selection transistor 12 connected in series with the magnetoresistive effect element 11. The end of the memory cell 2 on the magnetoresistive effect element 11 side is connected to the write line 3, and the end of the select transistor 12 side is grounded (connected to the common potential end). The gate electrode of the select transistor 12 of each memory cell 2 connected to the same write line 4 is connected to a read line (not shown).

  Both ends of each write line 3 are connected to a common line 15 via a switch circuit 13 made of, for example, a transistor. The set of switch circuits 13 constitutes the control circuit 5. Both ends of each write line 4 are connected to the common line 14 via the switch circuit 13.

  Each common line 15 is connected to a current source / sink 6. The current source / sink 6 includes, for example, a constant current source 31, a switch circuit 32, and a switch circuit 33 connected in series. The end of the current source / sink 6 on the switch circuit 33 side is grounded. The common line 15 is connected to a connection node between the switch circuit 32 and the switch circuit 33.

  One of the two common lines 14 (left side in the figure) is connected to the current source 7. The current source 7 includes, for example, a constant current source 21 and a switch circuit 22 connected in series. The other (right side in the figure) of the two common lines 14 is connected to the current sink 8. The current sink 8 is composed of, for example, a switch circuit 23 having one end grounded.

  As shown in FIG. 3, a control signal is supplied to the control terminals (gate electrodes in the case of transistors) of the switch circuits 13, 22, 23, 32, and 33. The control signal is supplied from the decoder 41. The decoder 41 is supplied with a control signal including an address signal, and generates a control signal so that data corresponding to the external control signal is written in a memory cell at a position corresponding to the external control signal. When the switch circuits 13, 22, 23, 32, and 33 are turned on or off according to this control signal, a current in a predetermined direction flows through the write lines 3 and 4 specified by the address signal, and the specified memory cell 2 Data is written to

  At the time of reading, the selection transistor 12 of the memory cell 2 to be read is turned on, and a current is supplied to the write line 3 connected to the target memory cell 2. The current value or voltage value at this time is compared with a reference value by a sense amplifier, whereby the data held in the memory cell 2 is determined.

  Next, the structure of the memory cells 2a and 2b will be described with reference to FIGS. 4 is a plan view of the memory cell 2a, and FIG. 5 is a plan view of the memory cell 2b. The orientations of the top, bottom, left and right of the paper surface of FIGS. 4 and 5 are the same as those of FIG. That is, for example, the lower side in FIG. 1 is also the lower side in FIGS.

  6 is a sectional view taken along line VI-VI in FIG. 4, and FIG. 7 is a sectional view taken along line VII-VII in FIG.

  As shown in FIGS. 4 to 7, the memory cell 2 includes an upper electrode 52, a magnetoresistive effect element 11, a lower electrode 54, and a selection transistor 12.

  Write lines 3 a and 3 b are provided above the semiconductor substrate 51. The magnetoresistive effect element 11 (magnetoresistance effect element 11a) of the memory cell 2a and the magnetoresistive effect element 11 (magnetoresistance effect element 11b) of the memory cell 2b are respectively connected to the lower ends of the write lines 3a and 3b via the upper electrode 52. It is connected. The easy axis of the magnetoresistive effect element 11 is along the direction in which the write line 4 extends, and the hard axis is perpendicular to the easy axis.

  The currents I3a and I3b flowing through the write lines 3a and 3b can take both directions.

  The lower surfaces of the magnetoresistive elements 11a and 11b are connected to the lower electrode 54 (lower electrode 54a) of the memory cell 2a and the upper surface of the lower electrode (lower electrode 54b) of the memory cell 2b, respectively. The sectional area of the lower electrode 54 is larger than the sectional area of the magnetoresistive effect element 11.

  As shown in FIG. 8, the magnetoresistive effect element 11 includes a fixed layer 101, a nonmagnetic layer 102, and a free layer (recording layer) 103 that are stacked in order from the bottom. The fixed layer 101 has a laminated structure of a ferromagnetic layer and an antiferromagnetic layer, and the magnetization direction of the ferromagnetic layer is fixed along the easy magnetization axis (horizontal direction in FIGS. 4 to 7) by the antiferromagnetic layer. The fixed layer 101 has a fixed magnetization. The lower surface of the fixed layer 101 is in contact with the upper surface of the lower electrode 54.

The nonmagnetic layer 102 is made of a nonmagnetic material, and a material that causes the nonmagnetic layer 102 to function as a tunnel barrier layer may be used in order to increase the magnetoresistance effect of the magnetoresistive element 11. An example of such a material is AlO ₂ .

  The free layer 103 is made of a ferromagnetic material, and the direction of magnetization is variable. The easy axis of free layer 103 is along the easy axis of free layer 103. The upper surface of the free layer 103 is in contact with the lower surface of the upper electrode.

  The magnetoresistive effect element 11 may have the structure shown in FIG. As shown in FIG. 9, the free layer 101 has the same planar shape as the lower electrode 54.

  As shown in FIGS. 4 to 7, the write lines 4a and 4b are provided below the lower electrodes 54a and 54b and immediately below the magnetoresistive elements 11a and 11b, respectively. Write currents I4a and I4b flowing through the write lines 4a and 4b are only in one direction. Therefore, a downward write magnetic field Ba is applied to the memory cell 2a by the current I4a, and an upward write magnetic field Bb is applied to the memory cell 2b by the current I4b. The lower electrodes 54a and 54b and the surface of the semiconductor substrate 51 are connected by a plug 55 (plug 55a) of the memory cell array 2a and a plug 55 (plug 55b) of the memory cell array 2b, respectively.

  The magnetoresistive effect element 11a is disposed in the upper half region of the lower electrode 54a in FIG. 4 (the right half region of the lower electrode 54a in FIG. 6). Further, the plug 55a is disposed in the lower half region of the lower electrode 54a in FIG. 4 (the left half region of the lower electrode 54a in FIG. 6).

  On the other hand, the magnetoresistive effect element 11b is arranged in the lower half region of the lower electrode 54b in FIG. 5 (the left half region of the lower electrode 54b in FIG. 7). Further, the plug 55b is arranged in the upper half region of the lower electrode 54b in FIG. 5 (the right half region of the lower electrode 54b in FIG. 7).

  The magnetoresistive effect element 11, the write line 3, the write line 4, the lower electrode 54, and the plug 55 have substantially the same shape regardless of the memory cell 2. Here, being the same means that each part is formed with the expectation that the same shape can be formed by the same process, and that an error is allowed.

  Since the memory cells 2a and 2b have the above-described configuration, they have a mirror-symmetrical relationship with respect to a virtual axis parallel to the easy axis. That is, the shape and relative positional relationship of the write lines 3 and 4, the magnetoresistive effect element 11, and the lower electrode 54 are the same in all the memory cells 2a and 2b.

  As shown in FIGS. 6 and 7, one of the pair of source / drain diffusion regions 56 is provided at a position where the plug 55 of the semiconductor substrate 51 contacts. The other of the source / drain diffusion regions 56 is connected to the wiring layer 62 through the plug 61.

  A gate electrode 58 is provided on the semiconductor substrate 51 between the pair of source / drain diffusion regions 56 via a gate insulating film 57. The source / drain diffusion region 56, the gate insulating film 57, and the gate electrode 58 constitute the selection transistor 12. An element isolation insulating film 63 is also provided on the surface of the semiconductor substrate 51.

  According to the magnetic memory device according to the first embodiment, the memory cell 2a and the memory cell 2b have a mirror symmetry relationship. Therefore, even if the directions of the magnetic fields Ba and Bb (generally, the magnetic field B) are different between the memory cells 2a and 2b, the magnetic fields Ba and Bb are transferred to the magnetoresistive effect elements 11a and 11b and the lower electrodes 54a and 54b. The same is applied to all the memory cells 2a and 2b.

  Specifically, for any of the magnetoresistive effect elements 11a and 11b, the magnetic fields Ba and Bb of the lower electrodes 54a and 54b from the magnetoresistive effect element 11a and 11b side toward the plugs 55a and 55b are generated. Applied. As a result, the interaction between the lower electrodes 54a and 54b and the magnetic fields Ba and Bb is unified between the memory cells 2a and 2b. Therefore, the write characteristics to the memory cells 2a and 2b are unified, and a magnetic memory device having a large write margin between the memory cells 2a and 2b can be realized.

  The first embodiment does not necessarily require each part of the memory cells 2a and 2b to be mirror-symmetric. If the shape and direction of each part are the same between the memory cells 2, at least the relative positional relationship among the write line 3, the lower electrode 54, and the magnetoresistive effect element 11, and the lower electrode 54 and the magnetoresistance The direction of the magnetic field B with respect to the effect element 11 only needs to be uniform between the memory cells 2. In this way, the magnetic field B is applied from the magnetoresistive effect element 11 side of the lower electrode 54 to the plug 55 side in all the memory cells 2. As a result, a larger write margin can be ensured than in the case where the position of the magnetoresistive effect element in the lower electrode and the direction of the magnetic field in which the direction with respect to the lower electrode and the magnetoresistive effect element is fixed are not unified by the memory cells.

  However, in addition to the above, if the positions of the magnetoresistive elements 11a and 11b in the lower electrodes 54a and 54b are also mirror-symmetric, the effect of unifying the writing characteristics is higher.

  The first embodiment is particularly effective when the fixed layer 101 and the lower electrode 54 have the same planar shape as shown in FIG. That is, in the magnetoresistive effect element having such a configuration, if the manner in which the leakage magnetic field from the fixed layer is applied to the magnetoresistive effect element is not uniform between the memory cells, the writing characteristics are affected by the leakage magnetic field. It varies widely between each other. On the other hand, according to the first embodiment, even when the magnetoresistive effect elements 11a and 11b having the configuration of FIG. 9 are used, the influence of the leakage magnetic field from the lower electrodes 54a and 54b is not affected by all the memory cells 2a, Since it is unified in 2b, a large write margin can be secured.

(Second Embodiment)
The second embodiment is different from the first embodiment in the shape of the lower electrode.

  The second embodiment will be described with reference to FIGS. 10 to 12. FIG. 10 is a block diagram of a magnetic memory device according to the second embodiment. FIG. 11 is a circuit diagram showing an example of the detailed configuration of FIG. As shown in FIGS. 10 and 11, write lines 4a and 4b extending along the horizontal direction of the drawings are alternately provided in the vertical direction of the drawings.

  A write current is configured to flow in both directions also to the write line 4 (4a, 4b). That is, current sources / sinks 6 are provided at positions aligned with the control circuits 5 on the left and right sides of the memory cell array 1.

  The left and right current sources / sinks 6 of the memory cell array 1 are electrically connected to the write lines 4 via the left and right control circuits 5 of the memory cell array 1. The pair of current sources / sinks 6 are electrically connected to both ends of at least one write line 4 by the control circuit 5.

  In response to a control signal (not shown), one of a pair of current sources / sinks 6 connected to both ends of the write line 4 supplies a write current to the write line 4, and the other draws a current from the write line 4. The direction of the current flowing through the write line 4 is specific to the write line 4 and flows in the right direction of the drawing in the write line 4a and in the left direction of the drawing in the write line 4b.

  The memory cell array 1 is composed of memory cells 2c and 2d, and the memory cells 2c and 2d have a planar shape different from that of the first embodiment, as will be described later. A memory cell 2 c is provided for a certain write line 4, and a memory cell 2 d is provided for the write line 4 adjacent to the write line 4. Therefore, the memory cells 2 c and 2 d are alternately arranged along the write lines 3.

  In the current source / sink 6 on the left and right of the memory cell array 1, the connection node between the switch circuit 32 and the switch circuit 33 is connected to the common line 14.

  Other configurations are the same as those of the first embodiment.

  Next, the structure of the memory cells 2c and 2d will be described with reference to FIG. FIG. 12 is a plan view of the memory cells 2c and 2d. The orientation of the top, bottom, left, and right of the paper surface of FIG. 12 is the same as that of FIG. That is, for example, the lower side in FIG. 10 is also the lower side in FIG.

  As shown in FIG. 12, the memory cell 2c includes a magnetoresistive effect element 11a, a lower electrode 54c, and a plug 55a, and the memory cell 2d includes a magnetoresistive effect element 11b, a lower electrode 54d, and a plug 55b.

  Adjacent memory cells 2c and 2d constitute one set with the memory cell 2c on the upper side and the memory cell 2d on the lower side. The memory cells 2c and 2d are provided on the lower electrodes 54c and 54d, respectively.

  The lower electrode 54c and the lower electrode 54d have a rotationally symmetric (point symmetric) relationship. For example, the lower electrodes 54c and 54d have the following shapes.

  The lower electrode 54c has a planar shape in which an L-shape is rotated by 180 °, and includes a portion 54c1 extending along the left-right direction and a portion 54c2 extending along the vertical direction. The portion 54c1 is located on the upper side and the portion 54c2 is located on the lower side in the drawing. Plug 55a is connected to portion 54c2. The magnetoresistive effect element 11a is located between the write line 3 and the write line 4a, and its easy axis is along the write line 4a.

The lower electrode 54d has an L-shaped planar shape and includes a portion 54d1 extending along the left-right direction and a portion 54d2 extending along the vertical direction. The portion 54d1 is located on the lower side and the portion 54d2 is located on the upper side in the drawing. Plug 55b is connected to portion 54d2. The magnetoresistive effect element 11b is located between the write line 3 and the write line 4b, and its easy axis is along the write line 4b. The left side of the portion 54c2 faces the right side of the portion 54d2, and the lower side of the portion 54c2 Faces the upper side of the portion 54d1. The upper side of the portion 54d2 faces the lower side of the portion 54c1.

  Since the current I4a flowing through the write line 4a flows in the right direction, the magnetic field Ba generated by the current I4a is directed downward in the magnetoresistive element 11a. Since the current I4b flowing through the write line 4b flows in the left direction, the magnetic field Bb generated by the current I4b is directed upward in the magnetoresistive element 11b.

  As for the cross-sectional shapes of the memory cells 2c and 2d, the shape along the VI-VI line is shown in FIG. 6, and the shape along the VII-VII line is shown in FIG. The configuration of the magnetoresistive effect elements 2c and 2d may be any of FIGS.

  The memory cells 2c and 2d have the configuration as described above, and have a point target relationship.

  According to the magnetic memory device of the second embodiment, the lower electrodes 54c and 54d through which the adjacent write lines 4a and 4b pass have a point-symmetric relationship with each other and the direction in which the write lines 4a and 4b flow is fixed. The written currents I4a and I4b are directed in opposite directions. For this reason, even if the shapes of the lower electrodes 54c and 54d are different, the magnetic fields Ba and Bb are similarly applied to the magnetoresistive elements 11a and 11b and the lower electrodes 54c and 54d in all the memory cells 2c and 2d. .

  Specifically, the magnetic fields Ba and Bb of the lower electrodes 54c and 54d from the magnetoresistive element side toward the plugs 55a and 55b are applied to any of the magnetoresistive effect elements 11a and 11b. For this reason, a magnetic memory device having a large write margin between the memory cells 2c and 2d can be realized.

  As in the first embodiment, at least the relative positional relationship among the write line 3, the lower electrode 54, and the magnetoresistive effect element 11, and the magnetic field B with respect to the lower electrode 54 and the magnetoresistive effect element 11. If the orientations are aligned between the memory cells 2, the effect of increasing the write margin can be obtained.

  The second embodiment is also particularly effective when the fixed layer 101 and the lower electrodes 54c and 54d have the same planar shape for the same reason as described in the first embodiment.

(Third embodiment)
The third embodiment relates to a case where a toggle writing method is applied to the first embodiment.

  In the toggle writing method, as disclosed in Patent Document 2, the easy axis of magnetization of each magnetoresistive effect element has an angle of 45 ° with respect to both of the two types of write lines in a plane composed of the two types of write lines. Along the direction. The structure of the magnetoresistive element and the timing for supplying the write current are also different from the conventional one.

  13 and 14 are plan views of the memory cell according to the third embodiment, and show a case where the third embodiment is applied to the first embodiment. FIG. 13 shows memory cells (corresponding to the memory cell 2a) provided in the memory cell array 1a of FIG. FIG. 14 shows memory cells (corresponding to the memory cell 2b) provided in the memory cell array 1b of FIG. The cross-sectional structure is the same as in the first embodiment.

  As shown in FIGS. 13 and 14, the memory cells 2a and 2b in the third embodiment are the same except that they include magnetoresistive elements 11c and 11d instead of the magnetoresistive elements 11a and 11b, respectively. The same as in the first embodiment.

  The magnetoresistive effect element 11c is provided on the lower electrode 54a. The magnetization easy axis of the magnetoresistive effect element 11c is along the direction of 45 ° with respect to both the write line 3a and the write line 4a. The hard axis is perpendicular to the easy axis. Therefore, the magnetic field B3a by the write line 3a and the magnetic field B4a by the write line 4a have an angle of 45 ° with respect to the easy axis and the hard axis.

  The magnetoresistive effect element 11d is provided on the lower electrode 54b. The magnetization easy axis of the magnetoresistive effect element 11d is along the direction of 45 ° with respect to both the write line 3b and the write line 4b. The hard axis is perpendicular to the easy axis. Therefore, the magnetic field B3b by the write line 3b and the magnetic field B4b by the write line 4b have an angle of 45 ° with respect to the easy axis and the hard axis.

  The easy axes of the magnetoresistive effect element 11 (the magnetoresistive effect elements 11c and 11d) are both in the same direction.

  Since the memory cell 2 (memory cells 2c and 2d) has the above-described configuration, it has a mirror surface relationship.

  The magnetoresistive effect elements 11c and 11d have the structure shown in FIGS. 15 and 16 are side views schematically showing the structure of an MTJ element that can be used in a toggle MRAM. FIG. 15 shows a state where the magnetization directions of the free layer and the pinned layer are parallel. FIG. 16 shows a state where the magnetization directions of the free layer and the pinned layer are antiparallel.

  As shown in FIGS. 15 and 16, the fixed layer 101 includes two ferromagnetic layers 111 and 112 made of ferromagnetic metal, and a paramagnetic layer 113 made of paramagnetic metal sandwiched between the ferromagnetic layers 111 and 112. And an antiferromagnetic layer 114 made of an antiferromagnetic metal. A structure including these ferromagnetic layers 111 and 112 and a paramagnetic layer 113 is provided on the antiferromagnetic layer 114. The two ferromagnetic layers 111 and 112 are antiferromagnetically coupled.

  The free layer 103 has two ferromagnetic layers 121 and 122 made of a ferromagnetic metal, and a paramagnetic layer 123 made of a paramagnetic metal sandwiched between the ferromagnetic layers. The two ferromagnetic layers 121 and 122 are antiferromagnetically coupled.

  As shown in FIG. 15, in the parallel state, the magnetization directions of the two ferromagnetic layers 111 and 122 sandwiching the nonmagnetic layer 102 are in a parallel state. As shown in FIG. 16, the nonmagnetic layer 102 is in an antiparallel state. The magnetization directions of the two ferromagnetic layers 111 and 122 sandwiched are antiparallel.

  In writing by the toggle writing method, data of a magnetoresistive effect element to be written is read, and if the data and the write data match, writing is not performed, but writing is performed only when the two do not match.

  In the toggle writing method, when writing is performed, the state of the MTJ element changes regardless of the state of the magnetoresistive element before writing. For example, by writing, an antiparallel magnetoresistive element changes to a parallel state, and a parallel magnetoresistive element changes to an antiparallel state.

  In order to invert the state of the magnetoresistive effect element, the write currents I3a and I3b are passed through the write lines 3a and 3b, respectively, and the write currents I4a and I4b are passed through the write lines 4a and 4b, respectively.

  The directions of the currents I3a, I3b, I4a, and I4b are fixed regardless of the write data. The directions in which the currents I3a, I3b, I4a, and I4b flow are set so that the direction of the current I3a and the direction of the current I3b, and the direction of the current I4a and the direction of the current I4b are opposite. For example, as shown in FIGS. 13 and 14, the current I3a flows upward, the current I4a flows rightward, the current I3b flows downward, and the current I4b flows leftward.

  The timing for applying the current I3 (currents I3a and I3b) and the current I4 (currents I4a and I4b) is, for example, as shown in FIG. As shown in FIG. 17, supply of current I4 is started at time T1. Supply of the current I4 is continued.

  Next, supply of current I3 is started at time T2 after time A has elapsed from time T1. Thereafter, the supply of currents I3 and I4 is continued until time T3. Next, at time T3, the supply of the current I4 is stopped. Next, supply of the current I3 is stopped at time T4.

  By supplying the above current, the states of the magnetoresistive effect elements 11c and 11d are reversed.

  Note that the supply start timing of the current I3 may be set so as to be earlier than the supply start timing of the current I4 by a certain delay time A.

  According to the magnetic memory device of the third embodiment, the memory cell 2c and the memory cell 2d have a mirror symmetry relationship as in the first embodiment, and the direction of the current I3a, the direction of the current I3b, and the direction of the current I4a And the direction of the current I4b is opposite. For this reason, even when the toggle write method is used, the write characteristics to the memory cells 2c and 2d are unified, and a magnetic memory device having a large write margin between the memory cells 2c and 2d can be realized.

  As in the first embodiment, at least the relative positional relationship between the write line 3, the write line 4, the lower electrode 54, and the magnetoresistive effect element 11, and the lower electrode 54 and the magnetoresistive effect element 11. If the direction of the magnetic field B3 (B3a, B3b) and the direction of the magnetic field B4 (B4a, B4b) with respect to the lower electrode 54 and the magnetoresistive effect element 11 are aligned between the memory cells 2, an effect of increasing the write margin can be obtained.

(Fourth embodiment)
The fourth embodiment relates to a case where a toggle writing method is applied to the second embodiment.

  FIG. 18 is a plan view of the memory cell according to the fourth embodiment, and shows a case where the toggle writing method is applied to the second embodiment. The cross-sectional structure is the same as in the first embodiment.

  As shown in FIG. 18, the memory cells 2c and 2d in the fourth embodiment are different from those in the second embodiment except that they include magnetoresistive elements 11c and 11d instead of the magnetoresistive elements 11a and 11b, respectively. Is the same.

  The magnetoresistive effect elements 11c and 11d are provided on the lower electrodes 54c and 54d, respectively. The magnetization easy axis and the magnetization difficult axis of the magnetoresistive effect elements 11c and 11d are along the direction of 45 ° with respect to both the write line 3a and the write line 4a. Further, the easy axes of the magnetoresistive elements 11c and 11d are along the same direction.

  The memory cells 2c and 2d have the configuration as described above and have a point-symmetric relationship.

  The direction in which the write current I3 flows is different between writing to the memory cell 2c and writing to the memory cell 2d. That is, the current I3 flows downward when writing to the memory cell 2c, and flows upward when writing to the memory cell 2d. Other write operations are the same as those described with reference to FIGS.

  According to the magnetic memory device according to the fourth embodiment, as in the second embodiment, the lower electrodes 54c and 54d through which the adjacent write lines 4a and 4b pass have a point-symmetric relationship with each other, and the current I3a The direction and the direction of the current I3b and the direction of the current I4a and the direction of the current I4b are opposite. For this reason, even when the toggle write method is used, the write characteristics to the memory cells 2c and 2d are unified, and a magnetic memory device having a large write margin between the memory cells 2c and 2d can be realized.

  As in the first embodiment, at least the relative positional relationship between the write line 3, the write line 4, the lower electrode 54, and the magnetoresistive effect element 11, and the lower electrode 54 and the magnetoresistive effect element 11. If the direction of the magnetic field B3 (B3a, B3b) and the direction of the magnetic field B4 (B4a, B4b) with respect to the lower electrode 54 and the magnetoresistive effect element 11 are aligned between the memory cells 2, an effect of increasing the write margin can be obtained.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a block diagram of a magnetic storage device according to a first embodiment. FIG. 1 is a circuit diagram showing an example of a detailed configuration of a magnetic storage device according to a first embodiment. The figure which shows the flow of the control signal to each switch circuit of 1st Embodiment. FIG. 3 is a plan view of the memory cell according to the first embodiment. FIG. 3 is a plan view of the memory cell according to the first embodiment. 1 is a side view of a magnetic storage device according to a first embodiment. 1 is a side view of a magnetic storage device according to a first embodiment. Sectional drawing of a magnetoresistive effect element. Sectional drawing of a magnetoresistive effect element. The block diagram of the magnetic memory | storage device which concerns on 2nd Embodiment. A circuit diagram showing an example of detailed composition of a magnetic memory device of a 2nd embodiment. The top view of the memory cell of 2nd Embodiment. The top view of the memory cell of 3rd Embodiment. The top view of the memory cell of 3rd Embodiment. The side view of the magnetoresistive effect element of 3rd Embodiment. The side view of the magnetoresistive effect element of 3rd Embodiment. 6 is a timing chart of write current. The top view of the memory cell of 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, 1b ... Memory cell array, 2a, 2b ... Memory cell, 3a, 3b, 4a, 4b ... Write line, 5 ... Control circuit, 6 ... Current source / sink, 7 ... Current source, 8 ... Current sink, 11 ... Magnetic Resistance effect element, 12 ... select transistor, 13 ... switch circuit, 14, 15 ... common line, 54a, 54b ... lower electrode, 55a, 55b ... plug.

Claims (5)

A memory cell array in which magnetoresistive elements are arranged in a matrix;
A first write line that extends along the first direction and is supplied only with a current directed to the first direction;
A second write line that extends along the first direction and is supplied only with a current in a second direction opposite to the first direction;
A third write line extending along a third direction orthogonal to the first direction;
A first electrode provided between the first write line and the third write line;
A first plug connected to the first electrode and provided below the first write line along the third direction;
A second electrode provided between the second write line and the third write line;
A second plug connected to the second electrode and provided above the second write line along the third direction;
With
The magnetoresistive element is disposed at a position where the first write line and the third write line intersect, and a position where the second write line and the third write line intersect. apparatus. A first memory cell array and a second memory cell array in which magnetoresistive elements are arranged in a matrix;
A first write line extending in the first direction in the first memory cell array and supplied only with a current in the first direction;
A second write line that extends along the first direction in the second memory cell array and is supplied only with a current in a second direction opposite to the first direction;
A third write line extending along a third direction orthogonal to the first direction in the first memory cell array;
A fourth write line extending along the third direction in the second memory cell array;
A first electrode provided between the first write line and the third write line;
A first plug connected to the first electrode and provided below the first write line along the third direction;
A second electrode provided between the second write line and the fourth write line;
A second plug connected to the second electrode and provided above the second write line along the third direction;
With
The magnetoresistive element includes a position where the first write line and the third write line in the first memory cell array intersect, and the second write line and the fourth write line in the second memory cell array. A magnetic storage device characterized in that the magnetic storage device is disposed at a position where the two cross.   3. The device according to claim 2, further comprising a current source that supplies current to the first write line and the second write line and is disposed between the first memory cell array and the second memory cell array. The magnetic storage device described. A memory cell array in which magnetoresistive elements are arranged in a matrix;
A first write line that extends along the first direction and is supplied only with a current directed to the first direction;
A second write line that extends along the first direction and is supplied only with a current in a second direction opposite to the first direction;
A third write line extending along a third direction orthogonal to the first direction;
A first electrode provided between the first write line and the third write line;
A first plug connected to the first electrode and provided below the first write line along the third direction;
A second electrode provided between the second write line and the third write line;
A second plug connected to the second electrode and provided above the second write line along the third direction;
With
The magnetoresistive element is disposed at a position where the first write line and the third write line intersect, and a position where the second write line and the third write line intersect,
The first plug and the second plug are arranged along the first direction between the first write line and the second write line.
A magnetic storage device.   5. The magnetic memory device according to claim 1, wherein the first electrode, the second electrode, and the magnetoresistive element have the same shape. 6.

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